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powerpc/85xx: add hardware automatically enter pw20 state
Using hardware features make core automatically enter PW20 state. Set a TB count to hardware, the effective count begins when PW10 is entered. When the effective period has expired, the core will proceed from PW10 to PW20 if no exit conditions have occurred during the period. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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parent
202e059ce3
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1d47ddf7c3
@ -53,6 +53,25 @@ _GLOBAL(__e500_dcache_setup)
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isync
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blr
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/*
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* FIXME - we haven't yet done testing to determine a reasonable default
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* value for PW20_WAIT_IDLE_BIT.
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*/
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#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
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_GLOBAL(setup_pw20_idle)
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mfspr r3, SPRN_PWRMGTCR0
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/* Set PW20_WAIT bit, enable pw20 state*/
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ori r3, r3, PWRMGTCR0_PW20_WAIT
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li r11, PW20_WAIT_IDLE_BIT
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/* Set Automatic PW20 Core Idle Count */
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rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
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mtspr SPRN_PWRMGTCR0, r3
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blr
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/*
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* FIXME - we haven't yet done testing to determine a reasonable default
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* value for AV_WAIT_IDLE_BIT.
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@ -83,6 +102,7 @@ _GLOBAL(__setup_cpu_e6500)
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bl .setup_lrat_ivor
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1:
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#endif
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bl setup_pw20_idle
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bl setup_altivec_idle
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bl __setup_cpu_e5500
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mtlr r6
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@ -151,6 +171,7 @@ _GLOBAL(__restore_cpu_e6500)
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beq 1f
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bl .setup_lrat_ivor
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1:
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bl .setup_pw20_idle
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bl .setup_altivec_idle
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bl __restore_cpu_e5500
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mtlr r5
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