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ARM: dts: rockchip: add more iommu nodes on rk3288
Add IEP/ISP/VPU/HEVC iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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1cc47e6359
@ -953,6 +953,25 @@
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status = "okay";
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};
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iep_mmu: iommu@ff900800 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff900800 0x0 0x40>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "iep_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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isp_mmu: iommu@ff914000 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "isp_mmu";
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#iommu-cells = <0>;
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rockchip,disable-mmu-reset;
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status = "disabled";
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};
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vopb: vop@ff930000 {
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compatible = "rockchip,rk3288-vop";
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reg = <0x0 0xff930000 0x0 0x19c>;
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@ -1126,6 +1145,24 @@
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};
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};
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vpu_mmu: iommu@ff9a0800 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff9a0800 0x0 0x100>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vpu_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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hevc_mmu: iommu@ff9c0440 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hevc_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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gpu: mali@ffa30000 {
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compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
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reg = <0x0 0xffa30000 0x0 0x10000>;
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