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drm/amdgpu: add a df 1.7 implementation of enable_ecc_force_par_wr_rmw

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Needed for proper memory setup depending on whether ECC is
enabled on a particular board.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2018-05-10 15:06:55 -05:00
parent 8f9b2e5061
commit 1ca2393b73
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/amd/amdgpu/df_v1_7.c
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@ -102,6 +102,13 @@ static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
*flags |= AMD_CG_SUPPORT_DF_MGCG;
}
static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
bool enable)
{
WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
ForceParWrRMW, enable);
}
const struct amdgpu_df_funcs df_v1_7_funcs = {
.init = df_v1_7_init,
.enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
@ -109,4 +116,5 @@ const struct amdgpu_df_funcs df_v1_7_funcs = {
.get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
.update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
.get_clockgating_state = df_v1_7_get_clockgating_state,
.enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
};