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ice: Initilialize VF RSS tables
Set configuration for hardware RSS tables for VFs. Signed-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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1c01c8c6c9
@ -38,6 +38,11 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
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ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP, 0, sizeof(__be16)),
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/* ICE_FLOW_FIELD_IDX_UDP_DST_PORT */
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ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP, 2, sizeof(__be16)),
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/* ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT */
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ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 0, sizeof(__be16)),
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/* ICE_FLOW_FIELD_IDX_SCTP_DST_PORT */
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ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 2, sizeof(__be16)),
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};
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/* Bitmaps indicating relevant packet types for a particular protocol header
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@ -266,6 +271,10 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
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case ICE_FLOW_FIELD_IDX_UDP_DST_PORT:
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prot_id = ICE_PROT_UDP_IL_OR_S;
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break;
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case ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT:
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case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
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prot_id = ICE_PROT_SCTP_IL;
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break;
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default:
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return ICE_ERR_NOT_IMPL;
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}
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@ -1081,6 +1090,132 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
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return status;
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}
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/* Mapping of AVF hash bit fields to an L3-L4 hash combination.
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* As the ice_flow_avf_hdr_field represent individual bit shifts in a hash,
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* convert its values to their appropriate flow L3, L4 values.
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*/
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#define ICE_FLOW_AVF_RSS_IPV4_MASKS \
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(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4))
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#define ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS \
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(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP))
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#define ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS \
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(BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP))
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#define ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS \
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(ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS | ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS | \
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ICE_FLOW_AVF_RSS_IPV4_MASKS | BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP))
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#define ICE_FLOW_AVF_RSS_IPV6_MASKS \
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(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6))
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#define ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS \
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(BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP))
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#define ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS \
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(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP))
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#define ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS \
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(ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS | ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS | \
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ICE_FLOW_AVF_RSS_IPV6_MASKS | BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP))
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/**
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* ice_add_avf_rss_cfg - add an RSS configuration for AVF driver
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* @hw: pointer to the hardware structure
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* @vsi_handle: software VSI handle
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* @avf_hash: hash bit fields (ICE_AVF_FLOW_FIELD_*) to configure
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*
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* This function will take the hash bitmap provided by the AVF driver via a
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* message, convert it to ICE-compatible values, and configure RSS flow
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* profiles.
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*/
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enum ice_status
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ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash)
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{
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enum ice_status status = 0;
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u64 hash_flds;
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if (avf_hash == ICE_AVF_FLOW_FIELD_INVALID ||
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!ice_is_vsi_valid(hw, vsi_handle))
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return ICE_ERR_PARAM;
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/* Make sure no unsupported bits are specified */
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if (avf_hash & ~(ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS |
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ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS))
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return ICE_ERR_CFG;
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hash_flds = avf_hash;
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/* Always create an L3 RSS configuration for any L4 RSS configuration */
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if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS)
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hash_flds |= ICE_FLOW_AVF_RSS_IPV4_MASKS;
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if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS)
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hash_flds |= ICE_FLOW_AVF_RSS_IPV6_MASKS;
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/* Create the corresponding RSS configuration for each valid hash bit */
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while (hash_flds) {
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u64 rss_hash = ICE_HASH_INVALID;
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if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV4_MASKS) {
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if (hash_flds & ICE_FLOW_AVF_RSS_IPV4_MASKS) {
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rss_hash = ICE_FLOW_HASH_IPV4;
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hash_flds &= ~ICE_FLOW_AVF_RSS_IPV4_MASKS;
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} else if (hash_flds &
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ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS) {
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rss_hash = ICE_FLOW_HASH_IPV4 |
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ICE_FLOW_HASH_TCP_PORT;
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hash_flds &= ~ICE_FLOW_AVF_RSS_TCP_IPV4_MASKS;
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} else if (hash_flds &
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ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS) {
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rss_hash = ICE_FLOW_HASH_IPV4 |
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ICE_FLOW_HASH_UDP_PORT;
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hash_flds &= ~ICE_FLOW_AVF_RSS_UDP_IPV4_MASKS;
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} else if (hash_flds &
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP)) {
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rss_hash = ICE_FLOW_HASH_IPV4 |
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ICE_FLOW_HASH_SCTP_PORT;
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hash_flds &=
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~BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP);
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}
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} else if (hash_flds & ICE_FLOW_AVF_RSS_ALL_IPV6_MASKS) {
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if (hash_flds & ICE_FLOW_AVF_RSS_IPV6_MASKS) {
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rss_hash = ICE_FLOW_HASH_IPV6;
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hash_flds &= ~ICE_FLOW_AVF_RSS_IPV6_MASKS;
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} else if (hash_flds &
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ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS) {
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rss_hash = ICE_FLOW_HASH_IPV6 |
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ICE_FLOW_HASH_TCP_PORT;
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hash_flds &= ~ICE_FLOW_AVF_RSS_TCP_IPV6_MASKS;
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} else if (hash_flds &
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ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS) {
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rss_hash = ICE_FLOW_HASH_IPV6 |
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ICE_FLOW_HASH_UDP_PORT;
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hash_flds &= ~ICE_FLOW_AVF_RSS_UDP_IPV6_MASKS;
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} else if (hash_flds &
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP)) {
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rss_hash = ICE_FLOW_HASH_IPV6 |
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ICE_FLOW_HASH_SCTP_PORT;
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hash_flds &=
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~BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP);
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}
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}
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if (rss_hash == ICE_HASH_INVALID)
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return ICE_ERR_OUT_OF_RANGE;
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status = ice_add_rss_cfg(hw, vsi_handle, rss_hash,
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ICE_FLOW_SEG_HDR_NONE);
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if (status)
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break;
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}
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return status;
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}
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/**
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* ice_replay_rss_cfg - replay RSS configurations associated with VSI
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* @hw: pointer to the hardware structure
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@ -20,6 +20,9 @@
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#define ICE_FLOW_HASH_UDP_PORT \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
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#define ICE_FLOW_HASH_SCTP_PORT \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
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#define ICE_HASH_INVALID 0
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#define ICE_HASH_TCP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_TCP_PORT)
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@ -53,10 +56,64 @@ enum ice_flow_field {
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ICE_FLOW_FIELD_IDX_TCP_DST_PORT,
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ICE_FLOW_FIELD_IDX_UDP_SRC_PORT,
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ICE_FLOW_FIELD_IDX_UDP_DST_PORT,
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ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT,
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ICE_FLOW_FIELD_IDX_SCTP_DST_PORT,
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/* The total number of enums must not exceed 64 */
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ICE_FLOW_FIELD_IDX_MAX
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};
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/* Flow headers and fields for AVF support */
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enum ice_flow_avf_hdr_field {
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/* Values 0 - 28 are reserved for future use */
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ICE_AVF_FLOW_FIELD_INVALID = 0,
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ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP = 29,
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ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP,
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ICE_AVF_FLOW_FIELD_IPV4_UDP,
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ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK,
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ICE_AVF_FLOW_FIELD_IPV4_TCP,
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ICE_AVF_FLOW_FIELD_IPV4_SCTP,
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ICE_AVF_FLOW_FIELD_IPV4_OTHER,
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ICE_AVF_FLOW_FIELD_FRAG_IPV4,
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/* Values 37-38 are reserved */
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ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP = 39,
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ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP,
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ICE_AVF_FLOW_FIELD_IPV6_UDP,
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ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK,
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ICE_AVF_FLOW_FIELD_IPV6_TCP,
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ICE_AVF_FLOW_FIELD_IPV6_SCTP,
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ICE_AVF_FLOW_FIELD_IPV6_OTHER,
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ICE_AVF_FLOW_FIELD_FRAG_IPV6,
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ICE_AVF_FLOW_FIELD_RSVD47,
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ICE_AVF_FLOW_FIELD_FCOE_OX,
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ICE_AVF_FLOW_FIELD_FCOE_RX,
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ICE_AVF_FLOW_FIELD_FCOE_OTHER,
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/* Values 51-62 are reserved */
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ICE_AVF_FLOW_FIELD_L2_PAYLOAD = 63,
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ICE_AVF_FLOW_FIELD_MAX
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};
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/* Supported RSS offloads This macro is defined to support
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* VIRTCHNL_OP_GET_RSS_HENA_CAPS ops. PF driver sends the RSS hardware
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* capabilities to the caller of this ops.
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*/
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#define ICE_DEFAULT_RSS_HENA ( \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP))
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enum ice_flow_dir {
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ICE_FLOW_RX = 0x02,
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};
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@ -140,6 +197,8 @@ struct ice_rss_cfg {
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enum ice_status ice_flow_rem_entry(struct ice_hw *hw, u64 entry_h);
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void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle);
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enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
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enum ice_status
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ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds);
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enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
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enum ice_status
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ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
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@ -1113,6 +1113,33 @@ ice_vsi_cfg_rss_exit:
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return err;
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}
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/**
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* ice_vsi_set_vf_rss_flow_fld - Sets VF VSI RSS input set for different flows
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* @vsi: VSI to be configured
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*
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* This function will only be called during the VF VSI setup. Upon successful
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* completion of package download, this function will configure default RSS
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* input sets for VF VSI.
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*/
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static void ice_vsi_set_vf_rss_flow_fld(struct ice_vsi *vsi)
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{
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struct ice_pf *pf = vsi->back;
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enum ice_status status;
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struct device *dev;
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dev = ice_pf_to_dev(pf);
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if (ice_is_safe_mode(pf)) {
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dev_dbg(dev, "Advanced RSS disabled. Package download failed, vsi num = %d\n",
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vsi->vsi_num);
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return;
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}
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status = ice_add_avf_rss_cfg(&pf->hw, vsi->idx, ICE_DEFAULT_RSS_HENA);
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if (status)
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dev_dbg(dev, "ice_add_avf_rss_cfg failed for vsi = %d, error = %d\n",
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vsi->vsi_num, status);
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}
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/**
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* ice_vsi_set_rss_flow_fld - Sets RSS input set for different flows
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* @vsi: VSI to be configured
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@ -2037,8 +2064,10 @@ ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
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* receive traffic on first queue. Hence no need to capture
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* return value
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*/
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if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
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if (test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
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ice_vsi_cfg_rss_lut_key(vsi);
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ice_vsi_set_vf_rss_flow_fld(vsi);
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}
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break;
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case ICE_VSI_LB:
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ret = ice_vsi_alloc_rings(vsi);
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@ -18,6 +18,7 @@ enum ice_prot_id {
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ICE_PROT_IPV6_IL = 41,
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ICE_PROT_TCP_IL = 49,
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ICE_PROT_UDP_IL_OR_S = 53,
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ICE_PROT_SCTP_IL = 96,
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ICE_PROT_META_ID = 255, /* when offset == metadata */
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ICE_PROT_INVALID = 255 /* when offset == ICE_FV_OFFSET_INVAL */
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};
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