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Merge branch 'for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata updates from Tejun Heo: "Nothing too interesting or alarming. Other than a new power saving mode addition to ahci and crash fix on a tracepoint, all changes are trivial or device-specific" * 'for-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (22 commits) ahci: imx: Handle increased read failures for IMX53 temperature sensor in low frequency mode. ata: sata_dwc_460ex: Propagate platform device ID to DMA driver ata: fixes kernel crash while tracing ata_eh_link_autopsy event ata: pata_pdc2027x: Fix space before '[' error. libata: fix spelling mistake: 'ambigious' -> 'ambiguous' ata: ceva: Add SMMU support for SATA IP ata: ceva: Correct the suspend and resume logic for SATA ata: ceva: Correct the AXI bus configuration for SATA ports ata: ceva: Add CCI support for SATA if CCI is enabled ata: ceva: Make RxWaterMark value as module parameter ata: ceva: Disable Device Sleep capability ata: ceva: Add gen 3 mode support in driver ata: ceva: Move sata port phy oob settings to device-tree devicetree: bindings: Add sata port phy config parameters in ahci-ceva ata: mark expected switch fall-throughs ata: sata_mv: remove a redundant assignment to pointer ehi ahci: Add support for Cavium's fifth generation SATA controller ata: sata_rcar: Use of_device_get_match_data() helper libata: make ata_port_type const libata: make static arrays const, reduces object code size ...
This commit is contained in:
Linus Torvalds
commit
1bc03573e1
@ -5,6 +5,36 @@ Required properties:
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- compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
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- clocks: Input clock specifier. Refer to common clock bindings.
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- interrupts: Interrupt specifier. Refer to interrupt binding.
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- ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
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- ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
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The fields for the above parameter must be as shown below:
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ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
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CINMP : COMINIT Negate Minimum Period.
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CIBGN : COMINIT Burst Gap Nominal.
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CIBGMX: COMINIT Burst Gap Maximum.
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CIBGMN: COMINIT Burst Gap Minimum.
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- ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
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- ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
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The fields for the above parameter must be as shown below:
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ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
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CWBGMN: COMWAKE Burst Gap Minimum.
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CWBGMX: COMWAKE Burst Gap Maximum.
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CWBGN: COMWAKE Burst Gap Nominal.
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CWNMP: COMWAKE Negate Minimum Period.
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- ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
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- ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
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The fields for the above parameter must be as shown below:
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ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
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BMX: COM Burst Maximum.
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BNM: COM Burst Nominal.
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SFD: Signal Failure Detection value.
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PTST: Partial to Slumber timer value.
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- ceva,p0-retry-params: Retry interval timing value for port 0.
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- ceva,p1-retry-params: Retry interval timing value for port 1.
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The fields for the above parameter must be as shown below:
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ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
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RIT: Retry Interval Timer.
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RCT: Rate Change Timer.
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Optional properties:
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- ceva,broken-gen2: limit to gen1 speed instead of gen2.
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@ -16,5 +46,14 @@ Examples:
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interrupt-parent = <&gic>;
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interrupts = <0 133 4>;
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clocks = <&clkc SATA_CLK_ID>;
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ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
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ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
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ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
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ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
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ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
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ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
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ceva,broken-gen2;
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};
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@ -57,6 +57,7 @@ enum {
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AHCI_PCI_BAR_STA2X11 = 0,
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AHCI_PCI_BAR_CAVIUM = 0,
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AHCI_PCI_BAR_ENMOTUS = 2,
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AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
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AHCI_PCI_BAR_STANDARD = 5,
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};
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@ -1570,8 +1571,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
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else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
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ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
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else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
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ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
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else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
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if (pdev->device == 0xa01c)
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ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
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if (pdev->device == 0xa084)
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ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
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}
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/* acquire resources */
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rc = pcim_enable_device(pdev);
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@ -32,15 +32,27 @@
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#define AHCI_VEND_PP3C 0xB0
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#define AHCI_VEND_PP4C 0xB4
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#define AHCI_VEND_PP5C 0xB8
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#define AHCI_VEND_AXICC 0xBC
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#define AHCI_VEND_PAXIC 0xC0
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#define AHCI_VEND_PTC 0xC8
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/* Vendor Specific Register bit definitions */
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#define PAXIC_ADBW_BW64 0x1
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#define PAXIC_MAWIDD (1 << 8)
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#define PAXIC_MARIDD (1 << 16)
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#define PAXIC_MAWID(i) (((i) * 2) << 4)
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#define PAXIC_MARID(i) (((i) * 2) << 12)
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#define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16)
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#define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8)
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#define PAXIC_OTL (0x4 << 20)
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/* Register bit definitions for cache control */
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#define AXICC_ARCA_VAL (0xF << 0)
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#define AXICC_ARCF_VAL (0xF << 4)
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#define AXICC_ARCH_VAL (0xF << 8)
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#define AXICC_ARCP_VAL (0xF << 12)
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#define AXICC_AWCFD_VAL (0xF << 16)
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#define AXICC_AWCD_VAL (0xF << 20)
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#define AXICC_AWCF_VAL (0xF << 24)
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#define PCFG_TPSS_VAL (0x32 << 16)
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#define PCFG_TPRS_VAL (0x2 << 12)
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#define PCFG_PAD_VAL 0x2
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@ -50,21 +62,6 @@
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#define PPCFG_PSS_EN (1 << 29)
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#define PPCFG_ESDF_EN (1 << 31)
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#define PP2C_CIBGMN 0x0F
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#define PP2C_CIBGMX (0x25 << 8)
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#define PP2C_CIBGN (0x18 << 16)
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#define PP2C_CINMP (0x29 << 24)
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#define PP3C_CWBGMN 0x04
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#define PP3C_CWBGMX (0x0B << 8)
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#define PP3C_CWBGN (0x08 << 16)
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#define PP3C_CWNMP (0x0F << 24)
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#define PP4C_BMX 0x0a
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#define PP4C_BNM (0x08 << 8)
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#define PP4C_SFD (0x4a << 16)
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#define PP4C_PTST (0x06 << 24)
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#define PP5C_RIT 0x60216
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#define PP5C_RCT (0x7f0 << 20)
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@ -75,6 +72,7 @@
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#define PORT1_BASE 0x180
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/* Port Control Register Bit Definitions */
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#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
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#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
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#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
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#define PORT_SCTL_IPM (0x3 << 8)
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@ -85,13 +83,43 @@
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#define DRV_NAME "ahci-ceva"
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#define CEVA_FLAG_BROKEN_GEN2 1
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static unsigned int rx_watermark = PTC_RX_WM_VAL;
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module_param(rx_watermark, uint, 0644);
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MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
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struct ceva_ahci_priv {
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struct platform_device *ahci_pdev;
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/* Port Phy2Cfg Register */
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u32 pp2c[NR_PORTS];
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u32 pp3c[NR_PORTS];
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u32 pp4c[NR_PORTS];
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u32 pp5c[NR_PORTS];
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/* Axi Cache Control Register */
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u32 axicc;
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bool is_cci_enabled;
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int flags;
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};
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static unsigned int ceva_ahci_read_id(struct ata_device *dev,
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struct ata_taskfile *tf, u16 *id)
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{
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u32 err_mask;
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err_mask = ata_do_dev_read_id(dev, tf, id);
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if (err_mask)
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return err_mask;
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/*
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* Since CEVA controller does not support device sleep feature, we
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* need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
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*/
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id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
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return 0;
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}
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static struct ata_port_operations ahci_ceva_ops = {
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.inherits = &ahci_platform_ops,
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.read_id = ceva_ahci_read_id,
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};
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static const struct ata_port_info ahci_ceva_port_info = {
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@ -108,14 +136,6 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
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u32 tmp;
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int i;
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/*
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* AXI Data bus width to 64
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* Set Mem Addr Read, Write ID for data transfers
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* Transfer limit to 72 DWord
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*/
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tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
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writel(tmp, mmio + AHCI_VEND_PAXIC);
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/* Set AHCI Enable */
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tmp = readl(mmio + HOST_CTL);
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tmp |= HOST_AHCI_EN;
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@ -126,32 +146,48 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
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tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
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writel(tmp, mmio + AHCI_VEND_PCFG);
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/*
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* AXI Data bus width to 64
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* Set Mem Addr Read, Write ID for data transfers
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* Set Mem Addr Read ID, Write ID for non-data transfers
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* Transfer limit to 72 DWord
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*/
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tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) |
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PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL;
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writel(tmp, mmio + AHCI_VEND_PAXIC);
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/* Set AXI cache control register if CCi is enabled */
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if (cevapriv->is_cci_enabled) {
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tmp = readl(mmio + AHCI_VEND_AXICC);
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tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL |
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AXICC_ARCH_VAL | AXICC_ARCP_VAL |
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AXICC_AWCFD_VAL | AXICC_AWCD_VAL |
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AXICC_AWCF_VAL;
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writel(tmp, mmio + AHCI_VEND_AXICC);
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}
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/* Port Phy Cfg register enables */
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tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
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writel(tmp, mmio + AHCI_VEND_PPCFG);
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/* Phy Control OOB timing parameters COMINIT */
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tmp = PP2C_CIBGMN | PP2C_CIBGMX | PP2C_CIBGN | PP2C_CINMP;
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writel(tmp, mmio + AHCI_VEND_PP2C);
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writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
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/* Phy Control OOB timing parameters COMWAKE */
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tmp = PP3C_CWBGMN | PP3C_CWBGMX | PP3C_CWBGN | PP3C_CWNMP;
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writel(tmp, mmio + AHCI_VEND_PP3C);
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writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
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/* Phy Control Burst timing setting */
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tmp = PP4C_BMX | PP4C_BNM | PP4C_SFD | PP4C_PTST;
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writel(tmp, mmio + AHCI_VEND_PP4C);
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writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
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/* Rate Change Timer and Retry Interval Timer setting */
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tmp = PP5C_RIT | PP5C_RCT;
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writel(tmp, mmio + AHCI_VEND_PP5C);
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writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
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/* Rx Watermark setting */
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tmp = PTC_RX_WM_VAL | PTC_RSVD;
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tmp = rx_watermark | PTC_RSVD;
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writel(tmp, mmio + AHCI_VEND_PTC);
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/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
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tmp = PORT_SCTL_SPD_GEN2 | PORT_SCTL_IPM;
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/* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
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tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
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if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
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tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
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writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
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@ -168,6 +204,7 @@ static int ceva_ahci_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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struct ceva_ahci_priv *cevapriv;
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enum dev_dma_attr attr;
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int rc;
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|
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cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
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@ -187,6 +224,65 @@ static int ceva_ahci_probe(struct platform_device *pdev)
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if (of_property_read_bool(np, "ceva,broken-gen2"))
|
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cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
|
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|
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/* Read OOB timing value for COMINIT from device-tree */
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if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
|
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(u8 *)&cevapriv->pp2c[0], 4) < 0) {
|
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dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
|
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(u8 *)&cevapriv->pp2c[1], 4) < 0) {
|
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dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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/* Read OOB timing value for COMWAKE from device-tree*/
|
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if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
|
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(u8 *)&cevapriv->pp3c[0], 4) < 0) {
|
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dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
|
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(u8 *)&cevapriv->pp3c[1], 4) < 0) {
|
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dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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/* Read phy BURST timing value from device-tree */
|
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if (of_property_read_u8_array(np, "ceva,p0-burst-params",
|
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(u8 *)&cevapriv->pp4c[0], 4) < 0) {
|
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dev_warn(dev, "ceva,p0-burst-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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if (of_property_read_u8_array(np, "ceva,p1-burst-params",
|
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(u8 *)&cevapriv->pp4c[1], 4) < 0) {
|
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dev_warn(dev, "ceva,p1-burst-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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/* Read phy RETRY interval timing value from device-tree */
|
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if (of_property_read_u16_array(np, "ceva,p0-retry-params",
|
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(u16 *)&cevapriv->pp5c[0], 2) < 0) {
|
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dev_warn(dev, "ceva,p0-retry-params property not defined\n");
|
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return -EINVAL;
|
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}
|
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|
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if (of_property_read_u16_array(np, "ceva,p1-retry-params",
|
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(u16 *)&cevapriv->pp5c[1], 2) < 0) {
|
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dev_warn(dev, "ceva,p1-retry-params property not defined\n");
|
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return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
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* Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
|
||||
* if CCI is enabled, so check for DEV_DMA_COHERENT.
|
||||
*/
|
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attr = device_get_dma_attr(dev);
|
||||
cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);
|
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|
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hpriv->plat_data = cevapriv;
|
||||
|
||||
/* CEVA specific initialization */
|
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@ -206,12 +302,37 @@ disable_resources:
|
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|
||||
static int __maybe_unused ceva_ahci_suspend(struct device *dev)
|
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{
|
||||
return ahci_platform_suspend_host(dev);
|
||||
return ahci_platform_suspend(dev);
|
||||
}
|
||||
|
||||
static int __maybe_unused ceva_ahci_resume(struct device *dev)
|
||||
{
|
||||
return ahci_platform_resume_host(dev);
|
||||
struct ata_host *host = dev_get_drvdata(dev);
|
||||
struct ahci_host_priv *hpriv = host->private_data;
|
||||
int rc;
|
||||
|
||||
rc = ahci_platform_enable_resources(hpriv);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Configure CEVA specific config before resuming HBA */
|
||||
ahci_ceva_setup(hpriv);
|
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|
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rc = ahci_platform_resume_host(dev);
|
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if (rc)
|
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goto disable_resources;
|
||||
|
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/* We resumed so update PM runtime state */
|
||||
pm_runtime_disable(dev);
|
||||
pm_runtime_set_active(dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
disable_resources:
|
||||
ahci_platform_disable_resources(hpriv);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
|
||||
|
||||
@ -230,7 +230,7 @@ static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
|
||||
{
|
||||
u16 adc_out_reg, read_sum;
|
||||
u32 index, read_attempt;
|
||||
const u32 attempt_limit = 100;
|
||||
const u32 attempt_limit = 200;
|
||||
|
||||
imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
|
||||
imx_phy_reg_write(rtune_ctl_reg, mmio);
|
||||
|
||||
@ -295,6 +295,7 @@ static int ahci_platform_get_phy(struct ahci_host_priv *hpriv, u32 port,
|
||||
node->name);
|
||||
break;
|
||||
}
|
||||
/* fall through */
|
||||
case -ENODEV:
|
||||
/* continue normally */
|
||||
hpriv->phys[port] = NULL;
|
||||
|
||||
@ -1879,6 +1879,7 @@ retry:
|
||||
switch (class) {
|
||||
case ATA_DEV_SEMB:
|
||||
class = ATA_DEV_ATA; /* some hard drives report SEMB sig */
|
||||
/* fall through */
|
||||
case ATA_DEV_ATA:
|
||||
case ATA_DEV_ZAC:
|
||||
tf.command = ATA_CMD_ID_ATA;
|
||||
@ -2975,6 +2976,7 @@ int ata_bus_probe(struct ata_port *ap)
|
||||
case -ENODEV:
|
||||
/* give it just one more chance */
|
||||
tries[dev->devno] = min(tries[dev->devno], 1);
|
||||
/* fall through */
|
||||
case -EIO:
|
||||
if (tries[dev->devno] == 1) {
|
||||
/* This is the last chance, better to slow
|
||||
@ -3462,6 +3464,7 @@ int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel)
|
||||
|
||||
case ATA_DNXFER_FORCE_PIO0:
|
||||
pio_mask &= 1;
|
||||
/* fall through */
|
||||
case ATA_DNXFER_FORCE_PIO:
|
||||
mwdma_mask = 0;
|
||||
udma_mask = 0;
|
||||
@ -3964,6 +3967,7 @@ int sata_link_scr_lpm(struct ata_link *link, enum ata_lpm_policy policy,
|
||||
scontrol &= ~(0x1 << 8);
|
||||
scontrol |= (0x6 << 8);
|
||||
break;
|
||||
case ATA_LPM_MED_POWER_WITH_DIPM:
|
||||
case ATA_LPM_MIN_POWER:
|
||||
if (ata_link_nr_enabled(link) > 0)
|
||||
/* no restrictions on LPM transitions */
|
||||
@ -5823,7 +5827,7 @@ void ata_host_resume(struct ata_host *host)
|
||||
}
|
||||
#endif
|
||||
|
||||
struct device_type ata_port_type = {
|
||||
const struct device_type ata_port_type = {
|
||||
.name = "ata_port",
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &ata_port_pm_ops,
|
||||
@ -6903,7 +6907,7 @@ static int __init ata_parse_force_one(char **cur,
|
||||
return -EINVAL;
|
||||
}
|
||||
if (nr_matches > 1) {
|
||||
*reason = "ambigious value";
|
||||
*reason = "ambiguous value";
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
@ -2264,8 +2264,8 @@ static void ata_eh_link_autopsy(struct ata_link *link)
|
||||
if (dev->flags & ATA_DFLAG_DUBIOUS_XFER)
|
||||
eflags |= ATA_EFLAG_DUBIOUS_XFER;
|
||||
ehc->i.action |= ata_eh_speed_down(dev, eflags, all_err_mask);
|
||||
trace_ata_eh_link_autopsy(dev, ehc->i.action, all_err_mask);
|
||||
}
|
||||
trace_ata_eh_link_autopsy(dev, ehc->i.action, all_err_mask);
|
||||
DPRINTK("EXIT\n");
|
||||
}
|
||||
|
||||
@ -3454,9 +3454,9 @@ static int ata_eh_maybe_retry_flush(struct ata_device *dev)
|
||||
* @r_failed_dev: out parameter for failed device
|
||||
*
|
||||
* Enable SATA Interface power management. This will enable
|
||||
* Device Interface Power Management (DIPM) for min_power
|
||||
* policy, and then call driver specific callbacks for
|
||||
* enabling Host Initiated Power management.
|
||||
* Device Interface Power Management (DIPM) for min_power and
|
||||
* medium_power_with_dipm policies, and then call driver specific
|
||||
* callbacks for enabling Host Initiated Power management.
|
||||
*
|
||||
* LOCKING:
|
||||
* EH context.
|
||||
@ -3502,7 +3502,7 @@ static int ata_eh_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
|
||||
hints &= ~ATA_LPM_HIPM;
|
||||
|
||||
/* disable DIPM before changing link config */
|
||||
if (policy != ATA_LPM_MIN_POWER && dipm) {
|
||||
if (policy < ATA_LPM_MED_POWER_WITH_DIPM && dipm) {
|
||||
err_mask = ata_dev_set_feature(dev,
|
||||
SETFEATURES_SATA_DISABLE, SATA_DIPM);
|
||||
if (err_mask && err_mask != AC_ERR_DEV) {
|
||||
@ -3545,7 +3545,7 @@ static int ata_eh_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
|
||||
|
||||
/* host config updated, enable DIPM if transitioning to MIN_POWER */
|
||||
ata_for_each_dev(dev, link, ENABLED) {
|
||||
if (policy == ATA_LPM_MIN_POWER && !no_dipm &&
|
||||
if (policy >= ATA_LPM_MED_POWER_WITH_DIPM && !no_dipm &&
|
||||
ata_id_has_dipm(dev->id)) {
|
||||
err_mask = ata_dev_set_feature(dev,
|
||||
SETFEATURES_SATA_ENABLE, SATA_DIPM);
|
||||
@ -3711,9 +3711,11 @@ static int ata_eh_handle_dev_fail(struct ata_device *dev, int err)
|
||||
case -ENODEV:
|
||||
/* device missing or wrong IDENTIFY data, schedule probing */
|
||||
ehc->i.probe_mask |= (1 << dev->devno);
|
||||
/* fall through */
|
||||
case -EINVAL:
|
||||
/* give it just one more chance */
|
||||
ehc->tries[dev->devno] = min(ehc->tries[dev->devno], 1);
|
||||
/* fall through */
|
||||
case -EIO:
|
||||
if (ehc->tries[dev->devno] == 1) {
|
||||
/* This is the last chance, better to slow
|
||||
|
||||
@ -106,10 +106,11 @@ static const u8 def_control_mpage[CONTROL_MPAGE_LEN] = {
|
||||
};
|
||||
|
||||
static const char *ata_lpm_policy_names[] = {
|
||||
[ATA_LPM_UNKNOWN] = "max_performance",
|
||||
[ATA_LPM_MAX_POWER] = "max_performance",
|
||||
[ATA_LPM_MED_POWER] = "medium_power",
|
||||
[ATA_LPM_MIN_POWER] = "min_power",
|
||||
[ATA_LPM_UNKNOWN] = "max_performance",
|
||||
[ATA_LPM_MAX_POWER] = "max_performance",
|
||||
[ATA_LPM_MED_POWER] = "medium_power",
|
||||
[ATA_LPM_MED_POWER_WITH_DIPM] = "med_power_with_dipm",
|
||||
[ATA_LPM_MIN_POWER] = "min_power",
|
||||
};
|
||||
|
||||
static ssize_t ata_scsi_lpm_store(struct device *device,
|
||||
@ -2145,7 +2146,7 @@ static void ata_scsi_rbuf_fill(struct ata_scsi_args *args,
|
||||
*/
|
||||
static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf)
|
||||
{
|
||||
const u8 versions[] = {
|
||||
static const u8 versions[] = {
|
||||
0x00,
|
||||
0x60, /* SAM-3 (no version claimed) */
|
||||
|
||||
@ -2155,7 +2156,7 @@ static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf)
|
||||
0x03,
|
||||
0x00 /* SPC-3 (no version claimed) */
|
||||
};
|
||||
const u8 versions_zbc[] = {
|
||||
static const u8 versions_zbc[] = {
|
||||
0x00,
|
||||
0xA0, /* SAM-5 (no version claimed) */
|
||||
|
||||
@ -2227,7 +2228,7 @@ static unsigned int ata_scsiop_inq_std(struct ata_scsi_args *args, u8 *rbuf)
|
||||
static unsigned int ata_scsiop_inq_00(struct ata_scsi_args *args, u8 *rbuf)
|
||||
{
|
||||
int num_pages;
|
||||
const u8 pages[] = {
|
||||
static const u8 pages[] = {
|
||||
0x00, /* page 0x00, this page */
|
||||
0x80, /* page 0x80, unit serial no page */
|
||||
0x83, /* page 0x83, device ident page */
|
||||
@ -2258,7 +2259,7 @@ static unsigned int ata_scsiop_inq_00(struct ata_scsi_args *args, u8 *rbuf)
|
||||
*/
|
||||
static unsigned int ata_scsiop_inq_80(struct ata_scsi_args *args, u8 *rbuf)
|
||||
{
|
||||
const u8 hdr[] = {
|
||||
static const u8 hdr[] = {
|
||||
0,
|
||||
0x80, /* this page code */
|
||||
0,
|
||||
@ -2580,7 +2581,7 @@ static unsigned int ata_scsiop_mode_sense(struct ata_scsi_args *args, u8 *rbuf)
|
||||
{
|
||||
struct ata_device *dev = args->dev;
|
||||
u8 *scsicmd = args->cmd->cmnd, *p = rbuf;
|
||||
const u8 sat_blk_desc[] = {
|
||||
static const u8 sat_blk_desc[] = {
|
||||
0, 0, 0, 0, /* number of blocks: sat unspecified */
|
||||
0,
|
||||
0, 0x2, 0x0 /* block length: 512 bytes */
|
||||
|
||||
@ -51,7 +51,7 @@ extern int atapi_passthru16;
|
||||
extern int libata_fua;
|
||||
extern int libata_noacpi;
|
||||
extern int libata_allow_tpm;
|
||||
extern struct device_type ata_port_type;
|
||||
extern const struct device_type ata_port_type;
|
||||
extern struct ata_link *ata_dev_phys_link(struct ata_device *dev);
|
||||
extern void ata_force_cbl(struct ata_port *ap);
|
||||
extern u64 ata_tf_to_lba(const struct ata_taskfile *tf);
|
||||
|
||||
@ -242,7 +242,7 @@ static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
||||
|
||||
static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
|
||||
{
|
||||
unsigned int pio = adev->pio_mode - XFER_PIO_0;
|
||||
unsigned int pio;
|
||||
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
||||
u8 ultra;
|
||||
|
||||
|
||||
@ -171,6 +171,7 @@ static int atp867x_get_active_clocks_shifted(struct ata_port *ap,
|
||||
default:
|
||||
printk(KERN_WARNING "ATP867X: active %dclk is invalid. "
|
||||
"Using 12clk.\n", clk);
|
||||
/* fall through */
|
||||
case 9 ... 12:
|
||||
clocks = 7; /* 12 clk */
|
||||
break;
|
||||
@ -203,6 +204,7 @@ static int atp867x_get_recover_clocks_shifted(unsigned int clk)
|
||||
default:
|
||||
printk(KERN_WARNING "ATP867X: recover %dclk is invalid. "
|
||||
"Using default 12clk.\n", clk);
|
||||
/* fall through */
|
||||
case 12: /* default 12 clk */
|
||||
clocks = 0;
|
||||
break;
|
||||
|
||||
@ -84,7 +84,7 @@ static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed
|
||||
*/
|
||||
static struct pdc2027x_pio_timing {
|
||||
u8 value0, value1, value2;
|
||||
} pdc2027x_pio_timing_tbl [] = {
|
||||
} pdc2027x_pio_timing_tbl[] = {
|
||||
{ 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
|
||||
{ 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
|
||||
{ 0x23, 0x26, 0x64 }, /* PIO mode 2 */
|
||||
@ -94,7 +94,7 @@ static struct pdc2027x_pio_timing {
|
||||
|
||||
static struct pdc2027x_mdma_timing {
|
||||
u8 value0, value1;
|
||||
} pdc2027x_mdma_timing_tbl [] = {
|
||||
} pdc2027x_mdma_timing_tbl[] = {
|
||||
{ 0xdf, 0x5f }, /* MDMA mode 0 */
|
||||
{ 0x6b, 0x27 }, /* MDMA mode 1 */
|
||||
{ 0x69, 0x25 }, /* MDMA mode 2 */
|
||||
@ -102,7 +102,7 @@ static struct pdc2027x_mdma_timing {
|
||||
|
||||
static struct pdc2027x_udma_timing {
|
||||
u8 value0, value1, value2;
|
||||
} pdc2027x_udma_timing_tbl [] = {
|
||||
} pdc2027x_udma_timing_tbl[] = {
|
||||
{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
|
||||
{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
|
||||
{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
|
||||
|
||||
@ -248,6 +248,7 @@ static int sata_dwc_dma_init_old(struct platform_device *pdev,
|
||||
return -ENOMEM;
|
||||
|
||||
hsdev->dma->dev = &pdev->dev;
|
||||
hsdev->dma->id = pdev->id;
|
||||
|
||||
/* Get SATA DMA interrupt number */
|
||||
hsdev->dma->irq = irq_of_parse_and_map(np, 1);
|
||||
|
||||
@ -2387,7 +2387,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
|
||||
": attempting PIO w/multiple DRQ: "
|
||||
"this may fail due to h/w errata\n");
|
||||
}
|
||||
/* drop through */
|
||||
/* fall through */
|
||||
case ATA_PROT_NODATA:
|
||||
case ATAPI_PROT_PIO:
|
||||
case ATAPI_PROT_NODATA:
|
||||
@ -2478,20 +2478,18 @@ static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
|
||||
|
||||
static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
|
||||
{
|
||||
struct ata_eh_info *ehi;
|
||||
unsigned int pmp;
|
||||
|
||||
/*
|
||||
* Initialize EH info for PMPs which saw device errors
|
||||
*/
|
||||
ehi = &ap->link.eh_info;
|
||||
for (pmp = 0; pmp_map != 0; pmp++) {
|
||||
unsigned int this_pmp = (1 << pmp);
|
||||
if (pmp_map & this_pmp) {
|
||||
struct ata_link *link = &ap->pmp_link[pmp];
|
||||
struct ata_eh_info *ehi = &link->eh_info;
|
||||
|
||||
pmp_map &= ~this_pmp;
|
||||
ehi = &link->eh_info;
|
||||
ata_ehi_clear_desc(ehi);
|
||||
ata_ehi_push_desc(ehi, "dev err");
|
||||
ehi->err_mask |= AC_ERR_DEV;
|
||||
@ -3877,7 +3875,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
|
||||
" and avoid the final two gigabytes on"
|
||||
" all RocketRAID BIOS initialized drives.\n");
|
||||
}
|
||||
/* drop through */
|
||||
/* fall through */
|
||||
case chip_6042:
|
||||
hpriv->ops = &mv6xxx_ops;
|
||||
hp_flags |= MV_HP_GEN_IIE;
|
||||
|
||||
@ -872,7 +872,6 @@ MODULE_DEVICE_TABLE(of, sata_rcar_match);
|
||||
|
||||
static int sata_rcar_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *of_id;
|
||||
struct ata_host *host;
|
||||
struct sata_rcar_priv *priv;
|
||||
struct resource *mem;
|
||||
@ -888,11 +887,7 @@ static int sata_rcar_probe(struct platform_device *pdev)
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
of_id = of_match_device(sata_rcar_match, &pdev->dev);
|
||||
if (!of_id)
|
||||
return -ENODEV;
|
||||
|
||||
priv->type = (enum sata_rcar_type)of_id->data;
|
||||
priv->type = (enum sata_rcar_type)of_device_get_match_data(&pdev->dev);
|
||||
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(priv->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get access to sata clock\n");
|
||||
|
||||
@ -522,6 +522,7 @@ enum ata_lpm_policy {
|
||||
ATA_LPM_UNKNOWN,
|
||||
ATA_LPM_MAX_POWER,
|
||||
ATA_LPM_MED_POWER,
|
||||
ATA_LPM_MED_POWER_WITH_DIPM, /* Med power + DIPM as win IRST does */
|
||||
ATA_LPM_MIN_POWER,
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user