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synced 2024-11-17 17:24:17 +08:00
powerpc/qe: Implement QE Pin Multiplexing API
With this API we're able to set a QE pin to the GPIO mode or a dedicated peripheral function. The API relies on the fact that QE gpio controllers are registered. If they aren't, the API won't work (gracefully though). There is one caveat though: if anybody occupied the node->data before us, or overwrote it, then bad things will happen. Luckily this is all in the platform code that we fully control, so this should never happen. I could implement more checks (for example we could create a list of successfully registered QE controllers, and compare the node->data in the qe_pin_request()), but this is unneeded if nobody is going to do silly things behind our back. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov
Kumar Gala
parent
78c7705037
commit
1b9e89046c
@ -17,6 +17,8 @@
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#ifdef __KERNEL__
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <asm/cpm.h>
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#include <asm/immap_qe.h>
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@ -112,6 +114,25 @@ extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
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int assignment, int has_irq);
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extern int par_io_data_set(u8 port, u8 pin, u8 val);
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/*
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* Pin multiplexing functions.
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*/
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struct qe_pin;
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#ifdef CONFIG_QE_GPIO
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extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
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extern void qe_pin_free(struct qe_pin *qe_pin);
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extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
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extern void qe_pin_set_dedicated(struct qe_pin *pin);
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#else
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static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
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{
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return ERR_PTR(-ENOSYS);
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}
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static inline void qe_pin_free(struct qe_pin *qe_pin) {}
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static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
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static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
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#endif /* CONFIG_QE_GPIO */
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/* QE internal API */
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int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
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enum qe_clock qe_clock_source(const char *source);
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@ -14,6 +14,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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@ -24,8 +25,14 @@ struct qe_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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unsigned long pin_flags[QE_PIO_PINS];
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#define QE_PIN_REQUESTED 0
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/* shadowed data register to clear/set bits safely */
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u32 cpdata;
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/* saved_regs used to restore dedicated functions */
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struct qe_pio_regs saved_regs;
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};
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static inline struct qe_gpio_chip *
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@ -40,6 +47,12 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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qe_gc->cpdata = in_be32(®s->cpdata);
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qe_gc->saved_regs.cpdata = qe_gc->cpdata;
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qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
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qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
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qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
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qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
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qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
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}
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static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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@ -103,6 +116,188 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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return 0;
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}
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struct qe_pin {
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/*
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* The qe_gpio_chip name is unfortunate, we should change that to
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* something like qe_pio_controller. Someday.
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*/
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struct qe_gpio_chip *controller;
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int num;
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};
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/**
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* qe_pin_request - Request a QE pin
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* @np: device node to get a pin from
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* @index: index of a pin in the device tree
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* Context: non-atomic
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*
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* This function return qe_pin so that you could use it with the rest of
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* the QE Pin Multiplexing API.
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*/
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struct qe_pin *qe_pin_request(struct device_node *np, int index)
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{
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struct qe_pin *qe_pin;
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struct device_node *gc;
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struct of_gpio_chip *of_gc = NULL;
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struct of_mm_gpio_chip *mm_gc;
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struct qe_gpio_chip *qe_gc;
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int err;
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int size;
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const void *gpio_spec;
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const u32 *gpio_cells;
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unsigned long flags;
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qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
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if (!qe_pin) {
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pr_debug("%s: can't allocate memory\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
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&gc, &gpio_spec);
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if (err) {
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pr_debug("%s: can't parse gpios property\n", __func__);
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goto err0;
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}
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if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
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pr_debug("%s: tried to get a non-qe pin\n", __func__);
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err = -EINVAL;
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goto err1;
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}
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of_gc = gc->data;
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if (!of_gc) {
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pr_debug("%s: gpio controller %s isn't registered\n",
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np->full_name, gc->full_name);
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err = -ENODEV;
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goto err1;
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}
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gpio_cells = of_get_property(gc, "#gpio-cells", &size);
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if (!gpio_cells || size != sizeof(*gpio_cells) ||
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*gpio_cells != of_gc->gpio_cells) {
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pr_debug("%s: wrong #gpio-cells for %s\n",
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np->full_name, gc->full_name);
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err = -EINVAL;
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goto err1;
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}
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err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
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if (err < 0)
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goto err1;
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mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
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qe_gc = to_qe_gpio_chip(mm_gc);
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spin_lock_irqsave(&qe_gc->lock, flags);
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if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
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qe_pin->controller = qe_gc;
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qe_pin->num = err;
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err = 0;
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} else {
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err = -EBUSY;
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}
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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if (!err)
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return qe_pin;
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err1:
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of_node_put(gc);
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err0:
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kfree(qe_pin);
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pr_debug("%s failed with status %d\n", __func__, err);
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return ERR_PTR(err);
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}
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EXPORT_SYMBOL(qe_pin_request);
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/**
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* qe_pin_free - Free a pin
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function frees the qe_pin structure and makes a pin available
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* for further qe_pin_request() calls.
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*/
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void qe_pin_free(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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unsigned long flags;
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const int pin = qe_pin->num;
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spin_lock_irqsave(&qe_gc->lock, flags);
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test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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kfree(qe_pin);
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}
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EXPORT_SYMBOL(qe_pin_free);
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/**
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* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function resets a pin to a dedicated peripheral function that
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* has been set up by the firmware.
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*/
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void qe_pin_set_dedicated(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
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struct qe_pio_regs *sregs = &qe_gc->saved_regs;
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int pin = qe_pin->num;
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u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
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u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
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bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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if (second_reg) {
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clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
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clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
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} else {
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clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
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clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
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}
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if (sregs->cpdata & mask1)
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qe_gc->cpdata |= mask1;
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else
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qe_gc->cpdata &= ~mask1;
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out_be32(®s->cpdata, qe_gc->cpdata);
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clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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EXPORT_SYMBOL(qe_pin_set_dedicated);
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/**
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* qe_pin_set_gpio - Set a pin to the GPIO mode
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function sets a pin to the GPIO mode.
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*/
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void qe_pin_set_gpio(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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/* Let's make it input by default, GPIO API is able to change that. */
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__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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EXPORT_SYMBOL(qe_pin_set_gpio);
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static int __init qe_add_gpiochips(void)
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{
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struct device_node *np;
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