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mfd: asic3: remove SD/SDIO controller register definitions
Only the base addresses remain, as they are needed to set up the IOMEM resources. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Philipp Zabel
Samuel Ortiz
parent
be584bd5a4
commit
1b89040c3a
@ -286,222 +286,9 @@ struct asic3_platform_data {
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* SDIO_CTRL Control registers for SDIO operations
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*
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*****************************************************************************/
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#define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */
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#define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */
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/* [0:8] SD Control Register Base Address */
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#define ASIC3_SD_CONFIG_Addr0 0x20
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/* [9:31] SD Control Register Base Address */
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#define ASIC3_SD_CONFIG_Addr1 0x24
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/* R/O: interrupt assigned to pin */
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#define ASIC3_SD_CONFIG_IntPin 0x78
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/*
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* Set to 0x1f to clock SD controller, 0 otherwise.
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* At 0x82 - Gated Clock Ctrl
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*/
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#define ASIC3_SD_CONFIG_ClkStop 0x80
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/* Control clock of SD controller */
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#define ASIC3_SD_CONFIG_ClockMode 0x84
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#define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
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#define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
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/* auto power up after card inserted */
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#define ASIC3_SD_CONFIG_SDHC_Power2 0x92
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/* auto power down when card removed */
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#define ASIC3_SD_CONFIG_SDHC_Power3 0x94
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#define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
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#define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
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#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
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#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
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/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
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#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
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#define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
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/* Bit 1: double buffer/single buffer */
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#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
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/* Memory access enable (set to 1 to access SD Controller) */
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#define SD_CONFIG_COMMAND_MAE (1<<1)
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#define SD_CONFIG_CLK_ENABLE_ALL 0x1f
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#define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
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#define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
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/* two bits - number of cycles for card detection */
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#define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
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#define ASIC3_SD_CTRL_Base 0x1000
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#define ASIC3_SD_CTRL_Cmd 0x00
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#define ASIC3_SD_CTRL_Arg0 0x08
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#define ASIC3_SD_CTRL_Arg1 0x0C
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#define ASIC3_SD_CTRL_StopInternal 0x10
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#define ASIC3_SD_CTRL_TransferSectorCount 0x14
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#define ASIC3_SD_CTRL_Response0 0x18
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#define ASIC3_SD_CTRL_Response1 0x1C
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#define ASIC3_SD_CTRL_Response2 0x20
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#define ASIC3_SD_CTRL_Response3 0x24
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#define ASIC3_SD_CTRL_Response4 0x28
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#define ASIC3_SD_CTRL_Response5 0x2C
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#define ASIC3_SD_CTRL_Response6 0x30
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#define ASIC3_SD_CTRL_Response7 0x34
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#define ASIC3_SD_CTRL_CardStatus 0x38
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#define ASIC3_SD_CTRL_BufferCtrl 0x3C
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#define ASIC3_SD_CTRL_IntMaskCard 0x40
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#define ASIC3_SD_CTRL_IntMaskBuffer 0x44
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#define ASIC3_SD_CTRL_CardClockCtrl 0x48
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#define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
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#define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
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#define ASIC3_SD_CTRL_ErrorStatus0 0x58
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#define ASIC3_SD_CTRL_ErrorStatus1 0x5C
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#define ASIC3_SD_CTRL_DataPort 0x60
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#define ASIC3_SD_CTRL_TransactionCtrl 0x68
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#define ASIC3_SD_CTRL_SoftwareReset 0x1C0
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#define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
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#define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
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#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
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#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
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#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
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#define MEM_CARD_OPTION_REQUIRED 0x000e
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#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
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#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
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#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
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#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
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#define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
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#define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
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#define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
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#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
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#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
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#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
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#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
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#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
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#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
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#define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
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#define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
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#define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
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#define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
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#define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
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#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
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#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
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#define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
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#define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
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#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
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#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
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#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
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#define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
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#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
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#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
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#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
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#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
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#define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
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#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
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#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
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#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
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#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
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#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
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#define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
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#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
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#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
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#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
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#define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
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#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
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#define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
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#define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
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#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
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#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
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#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
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#define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
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#define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
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#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
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#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
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#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
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#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
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#define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
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#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
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#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
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#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
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#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
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#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
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#define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
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#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
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#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
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#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
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#define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
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#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
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#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
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#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
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#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
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#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
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#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
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#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
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#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
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#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
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#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
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#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
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#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
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#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
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#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
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#define ASIC3_SDIO_CTRL_Base 0x1200
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#define ASIC3_SDIO_CTRL_Cmd 0x00
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#define ASIC3_SDIO_CTRL_CardPortSel 0x04
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#define ASIC3_SDIO_CTRL_Arg0 0x08
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#define ASIC3_SDIO_CTRL_Arg1 0x0C
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#define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
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#define ASIC3_SDIO_CTRL_Response0 0x18
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#define ASIC3_SDIO_CTRL_Response1 0x1C
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#define ASIC3_SDIO_CTRL_Response2 0x20
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#define ASIC3_SDIO_CTRL_Response3 0x24
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#define ASIC3_SDIO_CTRL_Response4 0x28
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#define ASIC3_SDIO_CTRL_Response5 0x2C
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#define ASIC3_SDIO_CTRL_Response6 0x30
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#define ASIC3_SDIO_CTRL_Response7 0x34
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#define ASIC3_SDIO_CTRL_CardStatus 0x38
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#define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
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#define ASIC3_SDIO_CTRL_IntMaskCard 0x40
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#define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
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#define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
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#define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
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#define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
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#define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
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#define ASIC3_SDIO_CTRL_DataPort 0x60
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#define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
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#define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
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#define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
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#define ASIC3_SDIO_CTRL_HostInformation 0x74
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#define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
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#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
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#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
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#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
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#define ASIC3_SD_CTRL_BASE 0x1000
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#define ASIC3_SDIO_CTRL_BASE 0x1200
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#define ASIC3_MAP_SIZE_32BIT 0x2000
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#define ASIC3_MAP_SIZE_16BIT 0x1000
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