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MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_op
The opcodes currently defined in inst.h as cbcond0_op & cbcond1_op are actually defined in the MIPS base instruction set manuals as pop10 & pop30 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -21,11 +21,11 @@
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enum major_op {
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spec_op, bcond_op, j_op, jal_op,
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beq_op, bne_op, blez_op, bgtz_op,
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addi_op, cbcond0_op = addi_op, addiu_op, slti_op, sltiu_op,
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addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
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andi_op, ori_op, xori_op, lui_op,
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cop0_op, cop1_op, cop2_op, cop1x_op,
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beql_op, bnel_op, blezl_op, bgtzl_op,
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daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
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daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
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spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
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lb_op, lh_op, lwl_op, lw_op,
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lbu_op, lhu_op, lwr_op, lwu_op,
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@ -809,8 +809,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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regs->cp0_epc += 8;
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break;
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#endif
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case cbcond0_op:
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case cbcond1_op:
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case pop10_op:
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case pop30_op:
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/* Only valid for MIPS R6 */
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if (!cpu_has_mips_r6) {
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ret = -SIGILL;
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@ -627,8 +627,8 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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case cbcond0_op:
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case cbcond1_op:
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case pop10_op:
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case pop30_op:
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if (!cpu_has_mips_r6)
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break;
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if (insn.i_format.rt && !insn.i_format.rs)
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