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dt-bindings: memory-controller: add STM32 FMC2 EBI controller documentation
This patch adds the documentation of the device tree bindings for the STM32 FMC2 EBI controller. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1591975362-22009-4-git-send-email-christophe.kerello@st.com
This commit is contained in:
Christophe Kerello
Miquel Raynal
parent
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commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
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description: |
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The FMC2 functional block makes the interface with: synchronous and
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asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
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peripherals) and NAND flash memories.
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Its main purposes are:
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- to translate AXI transactions into the appropriate external device
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protocol
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- to meet the access time requirements of the external devices
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All external devices share the addresses, data and control signals with the
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controller. Each external device is accessed by means of a unique Chip
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Select. The FMC2 performs only one access at a time to an external device.
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maintainers:
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- Christophe Kerello <christophe.kerello@st.com>
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properties:
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compatible:
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const: st,stm32mp1-fmc2-ebi
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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"#address-cells":
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const: 2
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"#size-cells":
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const: 1
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ranges:
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description: |
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Reflects the memory layout with four integer values per bank. Format:
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<bank-number> 0 <address of the bank> <size>
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patternProperties:
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"^.*@[0-4],[a-f0-9]+$":
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type: object
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properties:
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reg:
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description: Bank number, base address and size of the device.
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st,fmc2-ebi-cs-transaction-type:
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description: |
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Select one of the transactions type supported
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0: Asynchronous mode 1 SRAM/FRAM.
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1: Asynchronous mode 1 PSRAM.
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2: Asynchronous mode A SRAM/FRAM.
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3: Asynchronous mode A PSRAM.
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4: Asynchronous mode 2 NOR.
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5: Asynchronous mode B NOR.
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6: Asynchronous mode C NOR.
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7: Asynchronous mode D NOR.
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8: Synchronous read synchronous write PSRAM.
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9: Synchronous read asynchronous write PSRAM.
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10: Synchronous read synchronous write NOR.
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11: Synchronous read asynchronous write NOR.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 11
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st,fmc2-ebi-cs-cclk-enable:
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description: Continuous clock enable (first bank must be configured
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in synchronous mode). The FMC_CLK is generated continuously
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during asynchronous and synchronous access. By default, the
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FMC_CLK is only generated during synchronous access.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-mux-enable:
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description: Address/Data multiplexed on databus (valid only with
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NOR and PSRAM transactions type). By default, Address/Data
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are not multiplexed.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-buswidth:
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description: Data bus width
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 8, 16 ]
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default: 16
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st,fmc2-ebi-cs-waitpol-high:
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description: Wait signal polarity (NWAIT signal active high).
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By default, NWAIT is active low.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-waitcfg-enable:
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description: The NWAIT signal indicates wheither the data from the
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device are valid or if a wait state must be inserted when accessing
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the device in synchronous mode. By default, the NWAIT signal is
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active one data cycle before wait state.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-wait-enable:
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description: The NWAIT signal is enabled (its level is taken into
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account after the programmed latency period to insert wait states
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if asserted). By default, the NWAIT signal is disabled.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-asyncwait-enable:
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description: The NWAIT signal is taken into account during asynchronous
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transactions. By default, the NWAIT signal is not taken into account
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during asynchronous transactions.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-cpsize:
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description: CRAM page size. The controller splits the burst access
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when the memory page is reached. By default, no burst split when
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crossing page boundary.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 128, 256, 512, 1024 ]
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default: 0
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st,fmc2-ebi-cs-byte-lane-setup-ns:
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description: This property configures the byte lane setup timing
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defined in nanoseconds from NBLx low to Chip Select NEx low.
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st,fmc2-ebi-cs-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed read/write
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transactions.
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st,fmc2-ebi-cs-data-setup-ns:
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description: This property defines the duration of the data setup phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-bus-turnaround-ns:
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description: This property defines the delay in nanoseconds between the
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end of current read/write transaction and the next transaction.
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st,fmc2-ebi-cs-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-clk-period-ns:
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description: This property defines the FMC_CLK output signal period in
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nanoseconds.
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st,fmc2-ebi-cs-data-latency-ns:
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description: This property defines the data latency before reading or
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writing the first data in nanoseconds.
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st,fmc2_ebi-cs-write-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed write
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transactions.
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st,fmc2-ebi-cs-write-data-setup-ns:
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description: This property defines the duration of the data setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-bus-turnaround-ns:
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description: This property defines the delay between the end of current
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write transaction and the next transaction in nanoseconds.
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st,fmc2-ebi-cs-write-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-max-low-pulse-ns:
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description: This property defines the maximum chip select low pulse
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duration in nanoseconds for synchronous transactions. When this timing
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reaches 0, the controller splits the current access, toggles NE to
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allow device refresh and restarts a new access.
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required:
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- reg
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required:
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- "#address-cells"
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- "#size-cells"
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- compatible
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- reg
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- clocks
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- ranges
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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memory-controller@58002000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "st,stm32mp1-fmc2-ebi";
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reg = <0x58002000 0x1000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
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<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
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<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
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<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
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<4 0 0x80000000 0x10000000>; /* NAND */
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psram@0,0 {
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compatible = "mtd-ram";
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reg = <0 0x00000000 0x100000>;
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bank-width = <2>;
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st,fmc2-ebi-cs-transaction-type = <1>;
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st,fmc2-ebi-cs-address-setup-ns = <60>;
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st,fmc2-ebi-cs-data-setup-ns = <30>;
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st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
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};
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nand-controller@4,0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32mp1-fmc2-nfc";
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reg = <4 0x00000000 0x1000>,
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<4 0x08010000 0x1000>,
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<4 0x08020000 0x1000>,
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<4 0x01000000 0x1000>,
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<4 0x09010000 0x1000>,
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<4 0x09020000 0x1000>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
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<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
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<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
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dma-names = "tx", "rx", "ecc";
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nand@0 {
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reg = <0>;
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nand-on-flash-bbt;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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...
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