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perf vendor events intel: Refresh westmereep-dp events
Update the westmereep-dp events from 3 to 4. Generation was done using https://github.com/intel/perfmon. The most notable change is in corrections to event descriptions. Signed-off-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andrii Nakryiko <andrii@kernel.org> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Eduard Zingerman <eddyz87@gmail.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jing Zhang <renyu.zj@linux.alibaba.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Stephane Eranian <eranian@google.com> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-32-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -28,7 +28,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core
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GenuineIntel-6-55-[01234],v1.29,skylakex,core
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GenuineIntel-6-86,v1.20,snowridgex,core
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GenuineIntel-6-8[CD],v1.10,tigerlake,core
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GenuineIntel-6-2C,v3,westmereep-dp,core
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GenuineIntel-6-2C,v4,westmereep-dp,core
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GenuineIntel-6-25,v3,westmereep-sp,core
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GenuineIntel-6-2F,v3,westmereex,core
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AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
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@ -182,7 +182,7 @@
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"UMask": "0x20"
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},
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{
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"BriefDescription": "L2 lines alloacated",
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"BriefDescription": "L2 lines allocated",
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"EventCode": "0xF1",
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"EventName": "L2_LINES_IN.ANY",
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"SampleAfterValue": "100000",
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@ -56,7 +56,7 @@
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"UMask": "0x80"
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},
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{
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"BriefDescription": "DTLB misses casued by low part of address",
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"BriefDescription": "DTLB misses caused by low part of address",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.PDE_MISS",
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"SampleAfterValue": "200000",
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