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Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next

Browse Source 
John W. Linville says:

====================
Please pull these updates for the 3.14 stream!

For the mac80211 bits, Johannes says:

"Felix adds some helper functions for P2P NoA software tracking, Joe
fixes alignment (but as this apparently never caused issues I didn't
send it to 3.13), Kyeyoon/Jouni add QoS-mapping support (a Hotspot 2.0
feature), Weilong fixed a bunch of checkpatch errors and I get to play
fire-fighter or so and clean up other people's locking issues. I also
added nl80211 vendor-specific events, as we'd discussed at the wireless
summit."

For the iwlwifi bits, Emmanuel says:

"I have here a rework of the interrupt handling to meet RT kernel
requirements - basically we don't take any lock in the primary interrupt
handler. This gave me a good reason to clean things up a bit on the way.
There is also a fix of the QoS mapping along with a few workarounds for
hardware / firmware issues that are hard to hit.
Three fixes suggested by static analyzers, and other various stuff.
Most importantly, I update the Copyright note to include the new year."

For the bluetooth bits, Gustavo says:

"More patches to 3.14. The bulk of changes here is the 6LoWPAN support for
Bluetooth LE Devices. The commits that touches net/ieee802154/ are already
acked by David Miller. Other than that we have some RFCOMM fixes and
improvements plus fixes and clean ups all over the tree."

Beyond that, ath9k, brcmfmac, mwifiex, and wil6210 get their usual
level of attention.  The wl1251 driver gets a number of updates,
and there are a handful of other bits here and there.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2014-01-10 14:53:33 -05:00
commit 1a6c1e5bd2
264 changed files with 5741 additions and 2400 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/bcma/driver_chipcommon_sflash.c
View File

@ -38,7 +38,7 @@ static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
{ "M25P32", 0x15, 0x10000, 64, },
{ "M25P64", 0x16, 0x10000, 128, },
{ "M25FL128", 0x17, 0x10000, 256, },
{ 0 },
{ NULL },
};
static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
@ -56,7 +56,7 @@ static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
{ "SST25VF016", 0x41, 0x1000, 512, },
{ "SST25VF032", 0x4a, 0x1000, 1024, },
{ "SST25VF064", 0x4b, 0x1000, 2048, },
{ 0 },
{ NULL },
};
static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
@ -67,7 +67,7 @@ static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
{ "AT45DB161", 0x2c, 512, 4096, },
{ "AT45DB321", 0x34, 512, 8192, },
{ "AT45DB642", 0x3c, 1024, 8192, },
{ 0 },
{ NULL },
};
static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)

6
drivers/bluetooth/btsdio.c
View File

@ -73,6 +73,7 @@ struct btsdio_data {
#define REG_CL_INTRD 0x13 /* Interrupt Clear */
#define REG_EN_INTRD 0x14 /* Interrupt Enable */
#define REG_MD_STAT 0x20 /* Bluetooth Mode Status */
#define REG_MD_SET 0x20 /* Bluetooth Mode Set */
static int btsdio_tx_packet(struct btsdio_data *data, struct sk_buff *skb)
{
@ -212,7 +213,7 @@ static int btsdio_open(struct hci_dev *hdev)
}
if (data->func->class == SDIO_CLASS_BT_B)
sdio_writeb(data->func, 0x00, REG_MD_STAT, NULL);
sdio_writeb(data->func, 0x00, REG_MD_SET, NULL);
sdio_writeb(data->func, 0x01, REG_EN_INTRD, NULL);
@ -333,6 +334,9 @@ static int btsdio_probe(struct sdio_func *func,
hdev->flush = btsdio_flush;
hdev->send = btsdio_send_frame;
if (func->vendor == 0x0104 && func->device == 0x00c5)
set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks);
err = hci_register_dev(hdev);
if (err < 0) {
hci_free_dev(hdev);

46
drivers/bluetooth/btusb.c
View File

@ -965,6 +965,45 @@ static int btusb_setup_bcm92035(struct hci_dev *hdev)
return 0;
}
static int btusb_setup_csr(struct hci_dev *hdev)
{
struct hci_rp_read_local_version *rp;
struct sk_buff *skb;
int ret;
BT_DBG("%s", hdev->name);
skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL,
HCI_INIT_TIMEOUT);
if (IS_ERR(skb)) {
BT_ERR("Reading local version failed (%ld)", -PTR_ERR(skb));
return -PTR_ERR(skb);
}
rp = (struct hci_rp_read_local_version *) skb->data;
if (!rp->status) {
if (le16_to_cpu(rp->manufacturer) != 10) {
/* Clear the reset quirk since this is not an actual
* early Bluetooth 1.1 device from CSR.
*/
clear_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks);
/* These fake CSR controllers have all a broken
* stored link key handling and so just disable it.
*/
set_bit(HCI_QUIRK_BROKEN_STORED_LINK_KEY,
&hdev->quirks);
}
}
ret = -bt_to_errno(rp->status);
kfree_skb(skb);
return ret;
}
struct intel_version {
u8 status;
u8 hw_platform;
@ -1465,10 +1504,15 @@ static int btusb_probe(struct usb_interface *intf,
if (id->driver_info & BTUSB_CSR) {
struct usb_device *udev = data->udev;
u16 bcdDevice = le16_to_cpu(udev->descriptor.bcdDevice);
/* Old firmware would otherwise execute USB reset */
if (le16_to_cpu(udev->descriptor.bcdDevice) < 0x117)
if (bcdDevice < 0x117)
set_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks);
/* Fake CSR devices with broken commands */
if (bcdDevice <= 0x100)
hdev->setup = btusb_setup_csr;
}
if (id->driver_info & BTUSB_SNIFFER) {

29
drivers/bluetooth/hci_vhci.c
View File

@ -141,22 +141,28 @@ static int vhci_create_device(struct vhci_data *data, __u8 dev_type)
}
static inline ssize_t vhci_get_user(struct vhci_data *data,
const char __user *buf, size_t count)
const struct iovec *iov,
unsigned long count)
{
size_t len = iov_length(iov, count);
struct sk_buff *skb;
__u8 pkt_type, dev_type;
unsigned long i;
int ret;
if (count < 2 || count > HCI_MAX_FRAME_SIZE)
if (len < 2 || len > HCI_MAX_FRAME_SIZE)
return -EINVAL;
skb = bt_skb_alloc(count, GFP_KERNEL);
skb = bt_skb_alloc(len, GFP_KERNEL);
if (!skb)
return -ENOMEM;
if (copy_from_user(skb_put(skb, count), buf, count)) {
kfree_skb(skb);
return -EFAULT;
for (i = 0; i < count; i++) {
if (copy_from_user(skb_put(skb, iov[i].iov_len),
iov[i].iov_base, iov[i].iov_len)) {
kfree_skb(skb);
return -EFAULT;
}
}
pkt_type = *((__u8 *) skb->data);
@ -205,7 +211,7 @@ static inline ssize_t vhci_get_user(struct vhci_data *data,
return -EINVAL;
}
return (ret < 0) ? ret : count;
return (ret < 0) ? ret : len;
}
static inline ssize_t vhci_put_user(struct vhci_data *data,
@ -272,12 +278,13 @@ static ssize_t vhci_read(struct file *file,
return ret;
}
static ssize_t vhci_write(struct file *file,
const char __user *buf, size_t count, loff_t *pos)
static ssize_t vhci_write(struct kiocb *iocb, const struct iovec *iov,
unsigned long count, loff_t pos)
{
struct file *file = iocb->ki_filp;
struct vhci_data *data = file->private_data;
return vhci_get_user(data, buf, count);
return vhci_get_user(data, iov, count);
}
static unsigned int vhci_poll(struct file *file, poll_table *wait)
@ -342,7 +349,7 @@ static int vhci_release(struct inode *inode, struct file *file)
static const struct file_operations vhci_fops = {
.owner = THIS_MODULE,
.read = vhci_read,
.write = vhci_write,
.aio_write = vhci_write,
.poll = vhci_poll,
.open = vhci_open,
.release = vhci_release,

1
drivers/net/wireless/adm8211.c
View File

@ -15,7 +15,6 @@
* more details.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/if.h>
#include <linux/skbuff.h>

1
drivers/net/wireless/airo_cs.c
View File

@ -23,7 +23,6 @@
#ifdef __IN_PCMCIA_PACKAGE__
#include <pcmcia/k_compat.h>
#endif
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ptrace.h>

2
drivers/net/wireless/at76c50x-usb.c
View File

@ -1721,7 +1721,7 @@ static void at76_mac80211_tx(struct ieee80211_hw *hw,
* following workaround is necessary. If the TX frame is an
* authentication frame extract the bssid and send the CMD_JOIN. */
if (mgmt->frame_control & cpu_to_le16(IEEE80211_STYPE_AUTH)) {
if (!ether_addr_equal(priv->bssid, mgmt->bssid)) {
if (!ether_addr_equal_64bits(priv->bssid, mgmt->bssid)) {
memcpy(priv->bssid, mgmt->bssid, ETH_ALEN);
ieee80211_queue_work(hw, &priv->work_join_bssid);
dev_kfree_skb_any(skb);

1
drivers/net/wireless/ath/ar5523/ar5523.c
View File

@ -25,7 +25,6 @@
* that and only has minimal functionality.
*/
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/list.h>

4
drivers/net/wireless/ath/ath5k/base.c
View File

@ -1245,7 +1245,7 @@ ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
if (ieee80211_is_beacon(mgmt->frame_control) &&
le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
ether_addr_equal(mgmt->bssid, common->curbssid)) {
ether_addr_equal_64bits(mgmt->bssid, common->curbssid)) {
/*
* Received an IBSS beacon with the same BSSID. Hardware *must*
* have updated the local TSF. We have to work around various
@ -1309,7 +1309,7 @@ ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
/* only beacons from our BSSID */
if (!ieee80211_is_beacon(mgmt->frame_control) ||
!ether_addr_equal(mgmt->bssid, common->curbssid))
!ether_addr_equal_64bits(mgmt->bssid, common->curbssid))
return;
ewma_add(&ah->ah_beacon_rssi_avg, rssi);

15
drivers/net/wireless/ath/ath9k/ar9002_hw.c
View File

@ -383,6 +383,20 @@ void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
}
}
static void ar9002_hw_init_hang_checks(struct ath_hw *ah)
{
if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
ah->config.hw_hang_checks |= HW_BB_RIFS_HANG;
ah->config.hw_hang_checks |= HW_BB_DFS_HANG;
}
if (AR_SREV_9280(ah))
ah->config.hw_hang_checks |= HW_BB_RX_CLEAR_STUCK_HANG;
if (AR_SREV_5416(ah) || AR_SREV_9100(ah) || AR_SREV_9160(ah))
ah->config.hw_hang_checks |= HW_MAC_HANG;
}
/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
int ar9002_hw_attach_ops(struct ath_hw *ah)
{
@ -395,6 +409,7 @@ int ar9002_hw_attach_ops(struct ath_hw *ah)
return ret;
priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
priv_ops->init_hang_checks = ar9002_hw_init_hang_checks;
ops->config_pci_powersave = ar9002_hw_configpcipowersave;

223
drivers/net/wireless/ath/ath9k/ar9003_calib.c
View File

@ -326,6 +326,224 @@ static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
ah->supp_cals = IQ_MISMATCH_CAL;
}
#define OFF_UPPER_LT 24
#define OFF_LOWER_LT 7
static bool ar9003_hw_dynamic_osdac_selection(struct ath_hw *ah,
bool txiqcal_done)
{
struct ath_common *common = ath9k_hw_common(ah);
int ch0_done, osdac_ch0, dc_off_ch0_i1, dc_off_ch0_q1, dc_off_ch0_i2,
dc_off_ch0_q2, dc_off_ch0_i3, dc_off_ch0_q3;
int ch1_done, osdac_ch1, dc_off_ch1_i1, dc_off_ch1_q1, dc_off_ch1_i2,
dc_off_ch1_q2, dc_off_ch1_i3, dc_off_ch1_q3;
int ch2_done, osdac_ch2, dc_off_ch2_i1, dc_off_ch2_q1, dc_off_ch2_i2,
dc_off_ch2_q2, dc_off_ch2_i3, dc_off_ch2_q3;
bool status;
u32 temp, val;
/*
* Clear offset and IQ calibration, run AGC cal.
*/
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_OFFSET_CAL);
REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_CAL,
0, AH_WAIT_TIMEOUT);
if (!status) {
ath_dbg(common, CALIBRATE,
"AGC cal without offset cal failed to complete in 1ms");
return false;
}
/*
* Allow only offset calibration and disable the others
* (Carrier Leak calibration, TX Filter calibration and
* Peak Detector offset calibration).
*/
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_OFFSET_CAL);
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
AR_PHY_CL_CAL_ENABLE);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_FLTR_CAL);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_PKDET_CAL);
ch0_done = 0;
ch1_done = 0;
ch2_done = 0;
while ((ch0_done == 0) || (ch1_done == 0) || (ch2_done == 0)) {
osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3;
osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3;
osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3;
REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_CAL,
0, AH_WAIT_TIMEOUT);
if (!status) {
ath_dbg(common, CALIBRATE,
"DC offset cal failed to complete in 1ms");
return false;
}
REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
/*
* High gain.
*/
REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8)));
REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8)));
REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8)));
temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
dc_off_ch0_i1 = (temp >> 26) & 0x1f;
dc_off_ch0_q1 = (temp >> 21) & 0x1f;
temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
dc_off_ch1_i1 = (temp >> 26) & 0x1f;
dc_off_ch1_q1 = (temp >> 21) & 0x1f;
temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
dc_off_ch2_i1 = (temp >> 26) & 0x1f;
dc_off_ch2_q1 = (temp >> 21) & 0x1f;
/*
* Low gain.
*/
REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8)));
REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8)));
REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8)));
temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
dc_off_ch0_i2 = (temp >> 26) & 0x1f;
dc_off_ch0_q2 = (temp >> 21) & 0x1f;
temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
dc_off_ch1_i2 = (temp >> 26) & 0x1f;
dc_off_ch1_q2 = (temp >> 21) & 0x1f;
temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
dc_off_ch2_i2 = (temp >> 26) & 0x1f;
dc_off_ch2_q2 = (temp >> 21) & 0x1f;
/*
* Loopback.
*/
REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8)));
REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8)));
REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8)));
temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
dc_off_ch0_i3 = (temp >> 26) & 0x1f;
dc_off_ch0_q3 = (temp >> 21) & 0x1f;
temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
dc_off_ch1_i3 = (temp >> 26) & 0x1f;
dc_off_ch1_q3 = (temp >> 21) & 0x1f;
temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
dc_off_ch2_i3 = (temp >> 26) & 0x1f;
dc_off_ch2_q3 = (temp >> 21) & 0x1f;
if ((dc_off_ch0_i1 > OFF_UPPER_LT) || (dc_off_ch0_i1 < OFF_LOWER_LT) ||
(dc_off_ch0_i2 > OFF_UPPER_LT) || (dc_off_ch0_i2 < OFF_LOWER_LT) ||
(dc_off_ch0_i3 > OFF_UPPER_LT) || (dc_off_ch0_i3 < OFF_LOWER_LT) ||
(dc_off_ch0_q1 > OFF_UPPER_LT) || (dc_off_ch0_q1 < OFF_LOWER_LT) ||
(dc_off_ch0_q2 > OFF_UPPER_LT) || (dc_off_ch0_q2 < OFF_LOWER_LT) ||
(dc_off_ch0_q3 > OFF_UPPER_LT) || (dc_off_ch0_q3 < OFF_LOWER_LT)) {
if (osdac_ch0 == 3) {
ch0_done = 1;
} else {
osdac_ch0++;
val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff;
val |= (osdac_ch0 << 30);
REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val);
ch0_done = 0;
}
} else {
ch0_done = 1;
}
if ((dc_off_ch1_i1 > OFF_UPPER_LT) || (dc_off_ch1_i1 < OFF_LOWER_LT) ||
(dc_off_ch1_i2 > OFF_UPPER_LT) || (dc_off_ch1_i2 < OFF_LOWER_LT) ||
(dc_off_ch1_i3 > OFF_UPPER_LT) || (dc_off_ch1_i3 < OFF_LOWER_LT) ||
(dc_off_ch1_q1 > OFF_UPPER_LT) || (dc_off_ch1_q1 < OFF_LOWER_LT) ||
(dc_off_ch1_q2 > OFF_UPPER_LT) || (dc_off_ch1_q2 < OFF_LOWER_LT) ||
(dc_off_ch1_q3 > OFF_UPPER_LT) || (dc_off_ch1_q3 < OFF_LOWER_LT)) {
if (osdac_ch1 == 3) {
ch1_done = 1;
} else {
osdac_ch1++;
val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff;
val |= (osdac_ch1 << 30);
REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val);
ch1_done = 0;
}
} else {
ch1_done = 1;
}
if ((dc_off_ch2_i1 > OFF_UPPER_LT) || (dc_off_ch2_i1 < OFF_LOWER_LT) ||
(dc_off_ch2_i2 > OFF_UPPER_LT) || (dc_off_ch2_i2 < OFF_LOWER_LT) ||
(dc_off_ch2_i3 > OFF_UPPER_LT) || (dc_off_ch2_i3 < OFF_LOWER_LT) ||
(dc_off_ch2_q1 > OFF_UPPER_LT) || (dc_off_ch2_q1 < OFF_LOWER_LT) ||
(dc_off_ch2_q2 > OFF_UPPER_LT) || (dc_off_ch2_q2 < OFF_LOWER_LT) ||
(dc_off_ch2_q3 > OFF_UPPER_LT) || (dc_off_ch2_q3 < OFF_LOWER_LT)) {
if (osdac_ch2 == 3) {
ch2_done = 1;
} else {
osdac_ch2++;
val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff;
val |= (osdac_ch2 << 30);
REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val);
ch2_done = 0;
}
} else {
ch2_done = 1;
}
}
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_OFFSET_CAL);
REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
/*
* We don't need to check txiqcal_done here since it is always
* set for AR9550.
*/
REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
return true;
}
/*
* solve 4x4 linear equation used in loopback iq cal.
*/
@ -1271,6 +1489,11 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
}
if (AR_SREV_9550(ah) && IS_CHAN_2GHZ(chan)) {
if (!ar9003_hw_dynamic_osdac_selection(ah, txiqcal_done))
return false;
}
skip_tx_iqcal:
if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
if (AR_SREV_9330_11(ah))

13
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
View File

@ -3598,7 +3598,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
AR_SWITCH_TABLE_COM_AR9462_ALL, value);
} else if (AR_SREV_9550(ah)) {
} else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
AR_SWITCH_TABLE_COM_AR9550_ALL, value);
} else
@ -3975,7 +3975,7 @@ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
if (AR_SREV_9340(ah))
if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
return;
if (eep->baseEepHeader.featureEnable & 0x40) {
@ -4030,7 +4030,10 @@ static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
if (!(eep->baseEepHeader.featureEnable & 0x80))
return;
if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
if (!AR_SREV_9300(ah) &&
!AR_SREV_9340(ah) &&
!AR_SREV_9580(ah) &&
!AR_SREV_9531(ah))
return;
xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
@ -4163,7 +4166,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
ar9003_hw_atten_apply(ah, chan);
ar9003_hw_quick_drop_apply(ah, chan->channel);
if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah))
ar9003_hw_internal_regulator_apply(ah);
ar9003_hw_apply_tuning_caps(ah);
ar9003_hw_apply_minccapwr_thresh(ah, chan);
@ -4788,7 +4791,7 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah,
}
tempslope:
if (AR_SREV_9550(ah)) {
if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
/*
* AR955x has tempSlope register for each chain.
* Check whether temp_compensation feature is enabled or not.

161
drivers/net/wireless/ath/ath9k/ar9003_hw.c
View File

@ -28,6 +28,7 @@
#include "ar9462_2p1_initvals.h"
#include "ar9565_1p0_initvals.h"
#include "ar9565_1p1_initvals.h"
#include "ar953x_initvals.h"
/* General hardware code for the AR9003 hadware family */
@ -308,6 +309,31 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
/* Fast clock modal settings */
INIT_INI_ARRAY(&ah->iniModesFastClock,
ar955x_1p0_modes_fast_clock);
} else if (AR_SREV_9531(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
qca953x_1p0_mac_core);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
qca953x_1p0_mac_postamble);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
qca953x_1p0_baseband_core);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
qca953x_1p0_baseband_postamble);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
qca953x_1p0_radio_core);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
qca953x_1p0_radio_postamble);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
qca953x_1p0_soc_preamble);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
qca953x_1p0_soc_postamble);
INIT_INI_ARRAY(&ah->iniModesRxGain,
qca953x_1p0_common_wo_xlna_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca953x_1p0_common_wo_xlna_rx_gain_bounds);
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca953x_1p0_modes_no_xpa_tx_gain_table);
INIT_INI_ARRAY(&ah->iniModesFastClock,
qca953x_1p0_modes_fast_clock);
} else if (AR_SREV_9580(ah)) {
/* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@ -485,6 +511,9 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
else if (AR_SREV_9550(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar955x_1p0_modes_xpa_tx_gain_table);
else if (AR_SREV_9531(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca953x_1p0_modes_xpa_tx_gain_table);
else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9580_1p0_lowest_ob_db_tx_gain_table);
@ -525,7 +554,14 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
else if (AR_SREV_9550(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar955x_1p0_modes_no_xpa_tx_gain_table);
else if (AR_SREV_9462_21(ah))
else if (AR_SREV_9531(ah)) {
if (AR_SREV_9531_11(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca953x_1p1_modes_no_xpa_tx_gain_table);
else
INIT_INI_ARRAY(&ah->iniModesTxGain,
qca953x_1p0_modes_no_xpa_tx_gain_table);
} else if (AR_SREV_9462_21(ah))
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9462_2p1_modes_high_ob_db_tx_gain);
else if (AR_SREV_9462_20(ah))
@ -699,6 +735,11 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
ar955x_1p0_common_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
ar955x_1p0_common_rx_gain_bounds);
} else if (AR_SREV_9531(ah)) {
INIT_INI_ARRAY(&ah->iniModesRxGain,
qca953x_1p0_common_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca953x_1p0_common_rx_gain_bounds);
} else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9580_1p0_rx_gain_table);
@ -744,6 +785,11 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
ar955x_1p0_common_wo_xlna_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
ar955x_1p0_common_wo_xlna_rx_gain_bounds);
} else if (AR_SREV_9531(ah)) {
INIT_INI_ARRAY(&ah->iniModesRxGain,
qca953x_1p0_common_wo_xlna_rx_gain_table);
INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
qca953x_1p0_common_wo_xlna_rx_gain_bounds);
} else if (AR_SREV_9580(ah))
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9580_1p0_wo_xlna_rx_gain_table);
@ -872,6 +918,117 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
}
}
static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
{
/*
* All chips support detection of BB/MAC hangs.
*/
ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
ah->config.hw_hang_checks |= HW_MAC_HANG;
/*
* This is not required for AR9580 1.0
*/
if (AR_SREV_9300_22(ah))
ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
if (AR_SREV_9330(ah))
ah->bb_watchdog_timeout_ms = 85;
else
ah->bb_watchdog_timeout_ms = 25;
}
/*
* MAC HW hang check
* =================
*
* Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
*
* The state of each DCU chain (mapped to TX queues) is available from these
* DMA debug registers:
*
* Chain 0 state : Bits 4:0 of AR_DMADBG_4
* Chain 1 state : Bits 9:5 of AR_DMADBG_4
* Chain 2 state : Bits 14:10 of AR_DMADBG_4
* Chain 3 state : Bits 19:15 of AR_DMADBG_4
* Chain 4 state : Bits 24:20 of AR_DMADBG_4
* Chain 5 state : Bits 29:25 of AR_DMADBG_4
* Chain 6 state : Bits 4:0 of AR_DMADBG_5
* Chain 7 state : Bits 9:5 of AR_DMADBG_5
* Chain 8 state : Bits 14:10 of AR_DMADBG_5
* Chain 9 state : Bits 19:15 of AR_DMADBG_5
*
* The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
*/
#define NUM_STATUS_READS 50
static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
{
u32 dma_dbg_chain, dma_dbg_complete;
u8 dcu_chain_state, dcu_complete_state;
int i;
for (i = 0; i < NUM_STATUS_READS; i++) {
if (queue < 6)
dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
else
dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
dcu_complete_state = dma_dbg_complete & 0x3;
if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
return false;
}
ath_dbg(ath9k_hw_common(ah), RESET,
"MAC Hang signature found for queue: %d\n", queue);
return true;
}
static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
{
u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
u8 dcu_chain_state, dcu_complete_state;
bool dcu_wait_frdone = false;
unsigned long chk_dcu = 0;
unsigned int i = 0;
dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
dcu_complete_state = dma_dbg_6 & 0x3;
if (dcu_complete_state != 0x1)
goto exit;
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
if (i < 6)
chk_dbg = dma_dbg_4;
else
chk_dbg = dma_dbg_5;
dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
if (dcu_chain_state == 0x6) {
dcu_wait_frdone = true;
chk_dcu |= BIT(i);
}
}
if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
if (ath9k_hw_verify_hang(ah, i))
return true;
}
}
exit:
return false;
}
/* Sets up the AR9003 hardware familiy callbacks */
void ar9003_hw_attach_ops(struct ath_hw *ah)
{
@ -880,6 +1037,8 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
ar9003_hw_init_mode_regs(ah);
priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
ops->config_pci_powersave = ar9003_hw_configpcipowersave;

91
drivers/net/wireless/ath/ath9k/ar9003_phy.c
View File

@ -103,7 +103,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
} else {
channelSel = CHANSEL_2G(freq) >> 1;
}
} else if (AR_SREV_9550(ah)) {
} else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
if (ah->is_clk_25mhz)
div = 75;
else
@ -118,7 +118,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
/* Set to 2G mode */
bMode = 1;
} else {
if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) &&
ah->is_clk_25mhz) {
channelSel = freq / 75;
chan_frac = ((freq % 75) * 0x20000) / 75;
@ -810,10 +810,12 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
/*
* TXGAIN initvals.
*/
if (AR_SREV_9550(ah)) {
int modes_txgain_index;
if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
int modes_txgain_index = 1;
if (AR_SREV_9550(ah))
modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
if (modes_txgain_index < 0)
return -EINVAL;
@ -1814,6 +1816,68 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
}
/*
* Baseband Watchdog signatures:
*
* 0x04000539: BB hang when operating in HT40 DFS Channel.
* Full chip reset is not required, but a recovery
* mechanism is needed.
*
* 0x1300000a: Related to CAC deafness.
* Chip reset is not required.
*
* 0x0400000a: Related to CAC deafness.
* Full chip reset is required.
*
* 0x04000b09: RX state machine gets into an illegal state
* when a packet with unsupported rate is received.
* Full chip reset is required and PHY_RESTART has
* to be disabled.
*
* 0x04000409: Packet stuck on receive.
* Full chip reset is required for all chips except AR9340.
*/
/*
* ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
*/
bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
{
u32 val;
switch(ah->bb_watchdog_last_status) {
case 0x04000539:
val = REG_READ(ah, AR_PHY_RADAR_0);
val &= (~AR_PHY_RADAR_0_FIRPWR);
val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
REG_WRITE(ah, AR_PHY_RADAR_0, val);
udelay(1);
val = REG_READ(ah, AR_PHY_RADAR_0);
val &= ~AR_PHY_RADAR_0_FIRPWR;
val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
REG_WRITE(ah, AR_PHY_RADAR_0, val);
return false;
case 0x1300000a:
return false;
case 0x0400000a:
case 0x04000b09:
return true;
case 0x04000409:
if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
return false;
else
return true;
default:
/*
* For any other unknown signatures, do a
* full chip reset.
*/
return true;
}
}
EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
@ -1930,6 +1994,7 @@ EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
{
u8 result;
u32 val;
/* While receiving unsupported rate frame rx state machine
@ -1937,15 +2002,13 @@ void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
* state, BB would go hang. If RXSM is in 0xb state after
* first bb panic, ensure to disable the phy_restart.
*/
if (!((MS(ah->bb_watchdog_last_status,
AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
ah->bb_hang_rx_ofdm))
return;
result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
ah->bb_hang_rx_ofdm = true;
val = REG_READ(ah, AR_PHY_RESTART);
val &= ~AR_PHY_RESTART_ENA;
REG_WRITE(ah, AR_PHY_RESTART, val);
if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
ah->bb_hang_rx_ofdm = true;
val = REG_READ(ah, AR_PHY_RESTART);
val &= ~AR_PHY_RESTART_ENA;
REG_WRITE(ah, AR_PHY_RESTART, val);
}
}
EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);

17
drivers/net/wireless/ath/ath9k/ar9003_phy.h
View File

@ -338,9 +338,8 @@
#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -60
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -60
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
@ -670,6 +669,16 @@
#define AR_PHY_65NM_CH1_RXTX4 0x1650c
#define AR_PHY_65NM_CH2_RXTX4 0x1690c
#define AR_PHY_65NM_CH0_BB1 0x16140
#define AR_PHY_65NM_CH0_BB2 0x16144
#define AR_PHY_65NM_CH0_BB3 0x16148
#define AR_PHY_65NM_CH1_BB1 0x16540
#define AR_PHY_65NM_CH1_BB2 0x16544
#define AR_PHY_65NM_CH1_BB3 0x16548
#define AR_PHY_65NM_CH2_BB1 0x16940
#define AR_PHY_65NM_CH2_BB2 0x16944
#define AR_PHY_65NM_CH2_BB3 0x16948
#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19
#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
@ -1334,4 +1343,6 @@
#define AR_PHY_65NM_RXRF_AGC_AGC_OUT 0x00000004
#define AR_PHY_65NM_RXRF_AGC_AGC_OUT_S 2
#define AR9300_DFS_FIRPWR -28
#endif /* AR9003_PHY_H */

718
drivers/net/wireless/ath/ath9k/ar953x_initvals.h Normal file
View File

@ -0,0 +1,718 @@
/*
* Copyright (c) 2010-2011 Atheros Communications Inc.
* Copyright (c) 2011-2012 Qualcomm Atheros Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef INITVALS_953X_H
#define INITVALS_953X_H
#define qca953x_1p0_mac_postamble ar9300_2p2_mac_postamble
#define qca953x_1p0_soc_postamble ar9300_2p2_soc_postamble
#define qca953x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
#define qca953x_1p0_common_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
#define qca953x_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
static const u32 qca953x_1p0_mac_core[][2] = {
/* Addr allmodes */
{0x00000008, 0x00000000},
{0x00000030, 0x00020085},
{0x00000034, 0x00000005},
{0x00000040, 0x00000000},
{0x00000044, 0x00000000},
{0x00000048, 0x00000008},
{0x0000004c, 0x00000010},
{0x00000050, 0x00000000},
{0x00001040, 0x002ffc0f},
{0x00001044, 0x002ffc0f},
{0x00001048, 0x002ffc0f},
{0x0000104c, 0x002ffc0f},
{0x00001050, 0x002ffc0f},
{0x00001054, 0x002ffc0f},
{0x00001058, 0x002ffc0f},
{0x0000105c, 0x002ffc0f},
{0x00001060, 0x002ffc0f},
{0x00001064, 0x002ffc0f},
{0x000010f0, 0x00000100},
{0x00001270, 0x00000000},
{0x000012b0, 0x00000000},
{0x000012f0, 0x00000000},
{0x0000143c, 0x00000000},
{0x0000147c, 0x00000000},
{0x00008000, 0x00000000},
{0x00008004, 0x00000000},
{0x00008008, 0x00000000},
{0x0000800c, 0x00000000},
{0x00008018, 0x00000000},
{0x00008020, 0x00000000},
{0x00008038, 0x00000000},
{0x0000803c, 0x00000000},
{0x00008040, 0x00000000},
{0x00008044, 0x00000000},
{0x00008048, 0x00000000},
{0x0000804c, 0xffffffff},
{0x00008054, 0x00000000},
{0x00008058, 0x00000000},
{0x0000805c, 0x000fc78f},
{0x00008060, 0x0000000f},
{0x00008064, 0x00000000},
{0x00008070, 0x00000310},
{0x00008074, 0x00000020},
{0x00008078, 0x00000000},
{0x0000809c, 0x0000000f},
{0x000080a0, 0x00000000},
{0x000080a4, 0x02ff0000},
{0x000080a8, 0x0e070605},
{0x000080ac, 0x0000000d},
{0x000080b0, 0x00000000},
{0x000080b4, 0x00000000},
{0x000080b8, 0x00000000},
{0x000080bc, 0x00000000},
{0x000080c0, 0x2a800000},
{0x000080c4, 0x06900168},
{0x000080c8, 0x13881c22},
{0x000080cc, 0x01f40000},
{0x000080d0, 0x00252500},
{0x000080d4, 0x00a00000},
{0x000080d8, 0x00400000},
{0x000080dc, 0x00000000},
{0x000080e0, 0xffffffff},
{0x000080e4, 0x0000ffff},
{0x000080e8, 0x3f3f3f3f},
{0x000080ec, 0x00000000},
{0x000080f0, 0x00000000},
{0x000080f4, 0x00000000},
{0x000080fc, 0x00020000},
{0x00008100, 0x00000000},
{0x00008108, 0x00000052},
{0x0000810c, 0x00000000},
{0x00008110, 0x00000000},
{0x00008114, 0x000007ff},
{0x00008118, 0x000000aa},
{0x0000811c, 0x00003210},
{0x00008124, 0x00000000},
{0x00008128, 0x00000000},
{0x0000812c, 0x00000000},
{0x00008130, 0x00000000},
{0x00008134, 0x00000000},
{0x00008138, 0x00000000},
{0x0000813c, 0x0000ffff},
{0x00008140, 0x000000fe},
{0x00008144, 0xffffffff},
{0x00008168, 0x00000000},
{0x0000816c, 0x00000000},
{0x000081c0, 0x00000000},
{0x000081c4, 0x33332210},
{0x000081ec, 0x00000000},
{0x000081f0, 0x00000000},
{0x000081f4, 0x00000000},
{0x000081f8, 0x00000000},
{0x000081fc, 0x00000000},
{0x00008240, 0x00100000},
{0x00008244, 0x0010f3d7},
{0x00008248, 0x00000852},
{0x0000824c, 0x0001e7ae},
{0x00008250, 0x00000000},
{0x00008254, 0x00000000},
{0x00008258, 0x00000000},
{0x0000825c, 0x40000000},
{0x00008260, 0x00080922},
{0x00008264, 0x9d400010},
{0x00008268, 0xffffffff},
{0x0000826c, 0x0000ffff},
{0x00008270, 0x00000000},
{0x00008274, 0x40000000},
{0x00008278, 0x003e4180},
{0x0000827c, 0x00000004},
{0x00008284, 0x0000002c},
{0x00008288, 0x0000002c},
{0x0000828c, 0x000000ff},
{0x00008294, 0x00000000},
{0x00008298, 0x00000000},
{0x0000829c, 0x00000000},
{0x00008300, 0x00001d40},
{0x00008314, 0x00000000},
{0x0000831c, 0x0000010d},
{0x00008328, 0x00000000},
{0x0000832c, 0x0000001f},
{0x00008330, 0x00000302},
{0x00008334, 0x00000700},
{0x00008338, 0xffff0000},
{0x0000833c, 0x02400000},
{0x00008340, 0x000107ff},
{0x00008344, 0xaa48107b},
{0x00008348, 0x008f0000},
{0x0000835c, 0x00000000},
{0x00008360, 0xffffffff},
{0x00008364, 0xffffffff},
{0x00008368, 0x00000000},
{0x00008370, 0x00000000},
{0x00008374, 0x000000ff},
{0x00008378, 0x00000000},
{0x0000837c, 0x00000000},
{0x00008380, 0xffffffff},
{0x00008384, 0xffffffff},
{0x00008390, 0xffffffff},
{0x00008394, 0xffffffff},
{0x00008398, 0x00000000},
{0x0000839c, 0x00000000},
{0x000083a0, 0x00000000},
{0x000083a4, 0x0000fa14},
{0x000083a8, 0x000f0c00},
{0x000083ac, 0x33332210},
{0x000083b0, 0x33332210},
{0x000083b4, 0x33332210},
{0x000083b8, 0x33332210},
{0x000083bc, 0x00000000},
{0x000083c0, 0x00000000},
{0x000083c4, 0x00000000},
{0x000083c8, 0x00000000},
{0x000083cc, 0x00000200},
{0x000083d0, 0x8c7901ff},
};
static const u32 qca953x_1p0_baseband_core[][2] = {
/* Addr allmodes */
{0x00009800, 0xafe68e30},
{0x00009804, 0xfd14e000},
{0x00009808, 0x9c0a9f6b},
{0x0000980c, 0x04900000},
{0x00009814, 0x0280c00a},
{0x00009818, 0x00000000},
{0x0000981c, 0x00020028},
{0x00009834, 0x6400a190},
{0x00009838, 0x0108ecff},
{0x0000983c, 0x14000600},
{0x00009880, 0x201fff00},
{0x00009884, 0x00001042},
{0x000098a4, 0x00200400},
{0x000098b0, 0x32840bbe},
{0x000098bc, 0x00000002},
{0x000098d0, 0x004b6a8e},
{0x000098d4, 0x00000820},
{0x000098dc, 0x00000000},
{0x000098f0, 0x00000000},
{0x000098f4, 0x00000000},
{0x00009c04, 0xff55ff55},
{0x00009c08, 0x0320ff55},
{0x00009c0c, 0x00000000},
{0x00009c10, 0x00000000},
{0x00009c14, 0x00046384},
{0x00009c18, 0x05b6b440},
{0x00009c1c, 0x00b6b440},
{0x00009d00, 0xc080a333},
{0x00009d04, 0x40206c10},
{0x00009d08, 0x009c4060},
{0x00009d0c, 0x9883800a},
{0x00009d10, 0x01884061},
{0x00009d14, 0x00c0040b},
{0x00009d18, 0x00000000},
{0x00009e08, 0x0038230c},
{0x00009e24, 0x990bb515},
{0x00009e28, 0x0c6f0000},
{0x00009e30, 0x06336f77},
{0x00009e34, 0x6af6532f},
{0x00009e38, 0x0cc80c00},
{0x00009e40, 0x0d261820},
{0x00009e4c, 0x00001004},
{0x00009e50, 0x00ff03f1},
{0x00009fc0, 0x813e4788},
{0x00009fc4, 0x0001efb5},
{0x00009fcc, 0x40000014},
{0x00009fd0, 0x01193b91},
{0x0000a20c, 0x00000000},
{0x0000a220, 0x00000000},
{0x0000a224, 0x00000000},
{0x0000a228, 0x10002310},
{0x0000a23c, 0x00000000},
{0x0000a244, 0x0c000000},
{0x0000a248, 0x00000140},
{0x0000a2a0, 0x00000007},
{0x0000a2c0, 0x00000007},
{0x0000a2c8, 0x00000000},
{0x0000a2d4, 0x00000000},
{0x0000a2ec, 0x00000000},
{0x0000a2f0, 0x00000000},
{0x0000a2f4, 0x00000000},
{0x0000a2f8, 0x00000000},
{0x0000a344, 0x00000000},
{0x0000a34c, 0x00000000},
{0x0000a350, 0x0000a000},
{0x0000a364, 0x00000000},
{0x0000a370, 0x00000000},
{0x0000a390, 0x00000001},
{0x0000a394, 0x00000444},
{0x0000a398, 0x1f020503},
{0x0000a39c, 0x29180c03},
{0x0000a3a0, 0x9a8b6844},
{0x0000a3a4, 0x000000ff},
{0x0000a3a8, 0x6a6a6a6a},
{0x0000a3ac, 0x6a6a6a6a},
{0x0000a3b0, 0x00c8641a},
{0x0000a3b4, 0x0000001a},
{0x0000a3b8, 0x0088642a},
{0x0000a3bc, 0x000001fa},
{0x0000a3c0, 0x20202020},
{0x0000a3c4, 0x22222220},
{0x0000a3c8, 0x20200020},
{0x0000a3cc, 0x20202020},
{0x0000a3d0, 0x20202020},
{0x0000a3d4, 0x20202020},
{0x0000a3d8, 0x20202020},
{0x0000a3dc, 0x20202020},
{0x0000a3e0, 0x20202020},
{0x0000a3e4, 0x20202020},
{0x0000a3e8, 0x20202020},
{0x0000a3ec, 0x20202020},
{0x0000a3f0, 0x00000000},
{0x0000a3f4, 0x00000000},
{0x0000a3f8, 0x0c9bd380},
{0x0000a3fc, 0x000f0f01},
{0x0000a400, 0x8fa91f01},
{0x0000a404, 0x00000000},
{0x0000a408, 0x0e79e5c6},
{0x0000a40c, 0x00820820},
{0x0000a414, 0x1ce42108},
{0x0000a418, 0x2d001dce},
{0x0000a41c, 0x1ce73908},
{0x0000a420, 0x000001ce},
{0x0000a424, 0x1ce738e7},
{0x0000a428, 0x000001ce},
{0x0000a42c, 0x1ce739ce},
{0x0000a430, 0x1ce739ce},
{0x0000a434, 0x00000000},
{0x0000a438, 0x00001801},
{0x0000a43c, 0x00100000},
{0x0000a444, 0x00000000},
{0x0000a448, 0x05000080},
{0x0000a44c, 0x00000001},
{0x0000a450, 0x00010000},
{0x0000a458, 0x00000000},
{0x0000a644, 0xbfad9d74},
{0x0000a648, 0x0048060a},
{0x0000a64c, 0x00003c37},
{0x0000a670, 0x03020100},
{0x0000a674, 0x09080504},
{0x0000a678, 0x0d0c0b0a},
{0x0000a67c, 0x13121110},
{0x0000a680, 0x31301514},
{0x0000a684, 0x35343332},
{0x0000a688, 0x00000036},
{0x0000a690, 0x08000838},
{0x0000a7cc, 0x00000000},
{0x0000a7d0, 0x00000000},
{0x0000a7d4, 0x00000004},
{0x0000a7dc, 0x00000000},
{0x0000a8d0, 0x004b6a8e},
{0x0000a8d4, 0x00000820},
{0x0000a8dc, 0x00000000},
{0x0000a8f0, 0x00000000},
{0x0000a8f4, 0x00000000},
{0x0000b2d0, 0x00000080},
{0x0000b2d4, 0x00000000},
{0x0000b2ec, 0x00000000},
{0x0000b2f0, 0x00000000},
{0x0000b2f4, 0x00000000},
{0x0000b2f8, 0x00000000},
{0x0000b408, 0x0e79e5c0},
{0x0000b40c, 0x00820820},
{0x0000b420, 0x00000000},
};
static const u32 qca953x_1p0_baseband_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
{0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
{0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
{0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
{0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
{0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
{0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
{0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
{0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
{0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
{0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
{0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
{0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
{0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10822, 0xcfa10822},
{0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
{0x0000a204, 0x005c0ec0, 0x005c0ec4, 0x005c0ec4, 0x005c0ec0},
{0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
{0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
{0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
{0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
{0x0000a238, 0xffb01018, 0xffb01018, 0xffb01018, 0xffb01018},
{0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
{0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
{0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
{0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01010e0e, 0x01010e0e},
{0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
{0x0000a264, 0x00000e0e, 0x00000e0e, 0x01000e0e, 0x01000e0e},
{0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
{0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
{0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
{0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
{0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
{0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
{0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
{0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
{0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
{0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
{0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
{0x0000b284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
};
static const u32 qca953x_1p0_radio_core[][2] = {
/* Addr allmodes */
{0x00016000, 0x36db6db6},
{0x00016004, 0x6db6db40},
{0x00016008, 0x73f00000},
{0x0001600c, 0x00000000},
{0x00016040, 0x3f80fff8},
{0x0001604c, 0x000f0278},
{0x00016050, 0x8036db6c},
{0x00016054, 0x6db60000},
{0x00016080, 0x00080000},
{0x00016084, 0x0e48048c},
{0x00016088, 0x14214514},
{0x0001608c, 0x119f080a},
{0x00016090, 0x24926490},
{0x00016094, 0x00000000},
{0x000160a0, 0xc2108ffe},
{0x000160a4, 0x812fc370},
{0x000160a8, 0x423c8000},
{0x000160b4, 0x92480080},
{0x000160c0, 0x006db6d8},
{0x000160c4, 0x24b6db6c},
{0x000160c8, 0x6db6db6c},
{0x000160cc, 0x6db6fb7c},
{0x000160d0, 0x6db6da44},
{0x00016100, 0x07ff8001},
{0x00016108, 0x00080010},
{0x00016144, 0x01884080},
{0x00016148, 0x000080d8},
{0x00016280, 0x01000901},
{0x00016284, 0x15d30000},
{0x00016288, 0x00318000},
{0x0001628c, 0x50000000},
{0x00016380, 0x00000000},
{0x00016384, 0x00000000},
{0x00016388, 0x00800700},
{0x0001638c, 0x00800700},
{0x00016390, 0x00800700},
{0x00016394, 0x00000000},
{0x00016398, 0x00000000},
{0x0001639c, 0x00000000},
{0x000163a0, 0x00000001},
{0x000163a4, 0x00000001},
{0x000163a8, 0x00000000},
{0x000163ac, 0x00000000},
{0x000163b0, 0x00000000},
{0x000163b4, 0x00000000},
{0x000163b8, 0x00000000},
{0x000163bc, 0x00000000},
{0x000163c0, 0x000000a0},
{0x000163c4, 0x000c0000},
{0x000163c8, 0x14021402},
{0x000163cc, 0x00001402},
{0x000163d0, 0x00000000},
{0x000163d4, 0x00000000},
{0x00016400, 0x36db6db6},
{0x00016404, 0x6db6db40},
{0x00016408, 0x73f00000},
{0x0001640c, 0x00000000},
{0x00016440, 0x3f80fff8},
{0x0001644c, 0x000f0278},
{0x00016450, 0x8036db6c},
{0x00016454, 0x6db60000},
{0x00016500, 0x07ff8001},
{0x00016508, 0x00080010},
{0x00016544, 0x01884080},
{0x00016548, 0x000080d8},
{0x00016780, 0x00000000},
{0x00016784, 0x00000000},
{0x00016788, 0x00800700},
{0x0001678c, 0x00800700},
{0x00016790, 0x00800700},
{0x00016794, 0x00000000},
{0x00016798, 0x00000000},
{0x0001679c, 0x00000000},
{0x000167a0, 0x00000001},
{0x000167a4, 0x00000001},
{0x000167a8, 0x00000000},
{0x000167ac, 0x00000000},
{0x000167b0, 0x00000000},
{0x000167b4, 0x00000000},
{0x000167b8, 0x00000000},
{0x000167bc, 0x00000000},
{0x000167c0, 0x000000a0},
{0x000167c4, 0x000c0000},
{0x000167c8, 0x14021402},
{0x000167cc, 0x00001402},
{0x000167d0, 0x00000000},
{0x000167d4, 0x00000000},
};
static const u32 qca953x_1p0_radio_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00016098, 0xd2dd5554, 0xd2dd5554, 0xc4128f5c, 0xc4128f5c},
{0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x0fd08f25, 0x0fd08f25},
{0x000160ac, 0xa4647c00, 0xa4647c00, 0x24646800, 0x24646800},
{0x000160b0, 0x01885f52, 0x01885f52, 0x00fe7f46, 0x00fe7f46},
{0x00016104, 0xb7a00001, 0xb7a00001, 0xfff80005, 0xfff80005},
{0x0001610c, 0xc0000000, 0xc0000000, 0x00000000, 0x00000000},
{0x00016140, 0x10804008, 0x10804008, 0x50804000, 0x50804000},
{0x00016504, 0xb7a00001, 0xb7a00001, 0xfff80001, 0xfff80001},
{0x0001650c, 0xc0000000, 0xc0000000, 0x00000000, 0x00000000},
{0x00016540, 0x10804008, 0x10804008, 0x50804000, 0x50804000},
};
static const u32 qca953x_1p0_soc_preamble[][2] = {
/* Addr allmodes */
{0x00007000, 0x00000000},
{0x00007004, 0x00000000},
{0x00007008, 0x00000000},
{0x0000700c, 0x00000000},
{0x0000701c, 0x00000000},
{0x00007020, 0x00000000},
{0x00007024, 0x00000000},
{0x00007028, 0x00000000},
{0x0000702c, 0x00000000},
{0x00007030, 0x00000000},
{0x00007034, 0x00000002},
{0x00007038, 0x000004c2},
{0x00007048, 0x00000000},
};
static const u32 qca953x_1p0_common_rx_gain_bounds[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302018, 0x50302018},
};
static const u32 qca953x_1p0_common_wo_xlna_rx_gain_bounds[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
};
static const u32 qca953x_1p0_modes_xpa_tx_gain_table[][2] = {
/* Addr allmodes */
{0x0000a2dc, 0xfffd5aaa},
{0x0000a2e0, 0xfffe9ccc},
{0x0000a2e4, 0xffffe0f0},
{0x0000a2e8, 0xfffcff00},
{0x0000a410, 0x000050da},
{0x0000a500, 0x00000000},
{0x0000a504, 0x04000002},
{0x0000a508, 0x08000004},
{0x0000a50c, 0x0c000006},
{0x0000a510, 0x0f00000a},
{0x0000a514, 0x1300000c},
{0x0000a518, 0x1700000e},
{0x0000a51c, 0x1b000064},
{0x0000a520, 0x1f000242},
{0x0000a524, 0x23000229},
{0x0000a528, 0x270002a2},
{0x0000a52c, 0x2c001203},
{0x0000a530, 0x30001803},
{0x0000a534, 0x33000881},
{0x0000a538, 0x38001809},
{0x0000a53c, 0x3a000814},
{0x0000a540, 0x3f001a0c},
{0x0000a544, 0x43001a0e},
{0x0000a548, 0x46001812},
{0x0000a54c, 0x49001884},
{0x0000a550, 0x4d001e84},
{0x0000a554, 0x50001e69},
{0x0000a558, 0x550006f4},
{0x0000a55c, 0x59000ad3},
{0x0000a560, 0x5e000ad5},
{0x0000a564, 0x61001ced},
{0x0000a568, 0x660018d4},
{0x0000a56c, 0x660018d4},
{0x0000a570, 0x660018d4},
{0x0000a574, 0x660018d4},
{0x0000a578, 0x660018d4},
{0x0000a57c, 0x660018d4},
{0x0000a600, 0x00000000},
{0x0000a604, 0x00000000},
{0x0000a608, 0x00000000},
{0x0000a60c, 0x03804000},
{0x0000a610, 0x0300ca02},
{0x0000a614, 0x00000e04},
{0x0000a618, 0x03014000},
{0x0000a61c, 0x00000000},
{0x0000a620, 0x00000000},
{0x0000a624, 0x03014000},
{0x0000a628, 0x03804c05},
{0x0000a62c, 0x0701de06},
{0x0000a630, 0x07819c07},
{0x0000a634, 0x0701dc07},
{0x0000a638, 0x0701dc07},
{0x0000a63c, 0x0701dc07},
{0x0000b2dc, 0xfffd5aaa},
{0x0000b2e0, 0xfffe9ccc},
{0x0000b2e4, 0xffffe0f0},
{0x0000b2e8, 0xfffcff00},
{0x00016044, 0x010002d4},
{0x00016048, 0x66482400},
{0x00016280, 0x01000015},
{0x00016444, 0x010002d4},
{0x00016448, 0x66482400},
};
static const u32 qca953x_1p0_modes_no_xpa_tx_gain_table[][2] = {
/* Addr allmodes */
{0x0000a2dc, 0xffd5f552},
{0x0000a2e0, 0xffe60664},
{0x0000a2e4, 0xfff80780},
{0x0000a2e8, 0xfffff800},
{0x0000a410, 0x000050d6},
{0x0000a500, 0x00060020},
{0x0000a504, 0x04060060},
{0x0000a508, 0x080600a0},
{0x0000a50c, 0x0c068020},
{0x0000a510, 0x10068060},
{0x0000a514, 0x140680a0},
{0x0000a518, 0x18090040},
{0x0000a51c, 0x1b090080},
{0x0000a520, 0x1f0900c0},
{0x0000a524, 0x240c0041},
{0x0000a528, 0x280d0021},
{0x0000a52c, 0x2d0f0061},
{0x0000a530, 0x310f00a1},
{0x0000a534, 0x350e00a2},
{0x0000a538, 0x360e80a2},
{0x0000a53c, 0x380f00a2},
{0x0000a540, 0x3b0e00a3},
{0x0000a544, 0x3d110083},
{0x0000a548, 0x3e1100a3},
{0x0000a54c, 0x401100e3},
{0x0000a550, 0x421380e3},
{0x0000a554, 0x431780e3},
{0x0000a558, 0x461f80e3},
{0x0000a55c, 0x461f80e3},
{0x0000a560, 0x461f80e3},
{0x0000a564, 0x461f80e3},
{0x0000a568, 0x461f80e3},
{0x0000a56c, 0x461f80e3},
{0x0000a570, 0x461f80e3},
{0x0000a574, 0x461f80e3},
{0x0000a578, 0x461f80e3},
{0x0000a57c, 0x461f80e3},
{0x0000a600, 0x00000000},
{0x0000a604, 0x00000000},
{0x0000a608, 0x00000000},
{0x0000a60c, 0x00804201},
{0x0000a610, 0x01008201},
{0x0000a614, 0x0180c402},
{0x0000a618, 0x0180c603},
{0x0000a61c, 0x0180c603},
{0x0000a620, 0x01c10603},
{0x0000a624, 0x01c10704},
{0x0000a628, 0x02c18b05},
{0x0000a62c, 0x0301cc07},
{0x0000a630, 0x0301cc07},
{0x0000a634, 0x0301cc07},
{0x0000a638, 0x0301cc07},
{0x0000a63c, 0x0301cc07},
{0x0000b2dc, 0xffd5f552},
{0x0000b2e0, 0xffe60664},
{0x0000b2e4, 0xfff80780},
{0x0000b2e8, 0xfffff800},
{0x00016044, 0x049242db},
{0x00016048, 0x6c927a70},
{0x00016444, 0x049242db},
{0x00016448, 0x6c927a70},
};
static const u32 qca953x_1p1_modes_no_xpa_tx_gain_table[][2] = {
/* Addr allmodes */
{0x0000a2dc, 0xffd5f552},
{0x0000a2e0, 0xffe60664},
{0x0000a2e4, 0xfff80780},
{0x0000a2e8, 0xfffff800},
{0x0000a410, 0x000050de},
{0x0000a500, 0x00000061},
{0x0000a504, 0x04000063},
{0x0000a508, 0x08000065},
{0x0000a50c, 0x0c000261},
{0x0000a510, 0x10000263},
{0x0000a514, 0x14000265},
{0x0000a518, 0x18000482},
{0x0000a51c, 0x1b000484},
{0x0000a520, 0x1f000486},
{0x0000a524, 0x240008c2},
{0x0000a528, 0x28000cc1},
{0x0000a52c, 0x2d000ce3},
{0x0000a530, 0x31000ce5},
{0x0000a534, 0x350010e5},
{0x0000a538, 0x360012e5},
{0x0000a53c, 0x380014e5},
{0x0000a540, 0x3b0018e5},
{0x0000a544, 0x3d001d04},
{0x0000a548, 0x3e001d05},
{0x0000a54c, 0x40001d07},
{0x0000a550, 0x42001f27},
{0x0000a554, 0x43001f67},
{0x0000a558, 0x46001fe7},
{0x0000a55c, 0x47001f2b},
{0x0000a560, 0x49001f0d},
{0x0000a564, 0x4b001ed2},
{0x0000a568, 0x4c001ed4},
{0x0000a56c, 0x4e001f15},
{0x0000a570, 0x4f001ff6},
{0x0000a574, 0x4f001ff6},
{0x0000a578, 0x4f001ff6},
{0x0000a57c, 0x4f001ff6},
{0x0000a600, 0x00000000},
{0x0000a604, 0x00000000},
{0x0000a608, 0x00000000},
{0x0000a60c, 0x00804201},
{0x0000a610, 0x01008201},
{0x0000a614, 0x0180c402},
{0x0000a618, 0x0180c603},
{0x0000a61c, 0x0180c603},
{0x0000a620, 0x01c10603},
{0x0000a624, 0x01c10704},
{0x0000a628, 0x02c18b05},
{0x0000a62c, 0x02c14c07},
{0x0000a630, 0x01008704},
{0x0000a634, 0x01c10402},
{0x0000a638, 0x0301cc07},
{0x0000a63c, 0x0301cc07},
{0x0000b2dc, 0xffd5f552},
{0x0000b2e0, 0xffe60664},
{0x0000b2e4, 0xfff80780},
{0x0000b2e8, 0xfffff800},
{0x00016044, 0x049242db},
{0x00016048, 0x6c927a70},
{0x00016444, 0x049242db},
{0x00016448, 0x6c927a70},
};
#endif /* INITVALS_953X_H */

7
drivers/net/wireless/ath/ath9k/ath9k.h
View File

@ -455,10 +455,8 @@ bool ath9k_csa_is_finished(struct ath_softc *sc);
void ath_tx_complete_poll_work(struct work_struct *work);
void ath_reset_work(struct work_struct *work);
void ath_hw_check(struct work_struct *work);
bool ath_hw_check(struct ath_softc *sc);
void ath_hw_pll_work(struct work_struct *work);
void ath_rx_poll(unsigned long data);
void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
void ath_paprd_calibrate(struct work_struct *work);
void ath_ani_calibrate(unsigned long data);
void ath_start_ani(struct ath_softc *sc);
@ -722,12 +720,10 @@ struct ath_softc {
spinlock_t sc_pcu_lock;
struct mutex mutex;
struct work_struct paprd_work;
struct work_struct hw_check_work;
struct work_struct hw_reset_work;
struct completion paprd_complete;
wait_queue_head_t tx_wait;
unsigned int hw_busy_count;
unsigned long sc_flags;
unsigned long driver_data;
@ -761,7 +757,6 @@ struct ath_softc {
struct ath_beacon_config cur_beacon_conf;
struct delayed_work tx_complete_work;
struct delayed_work hw_pll_work;
struct timer_list rx_poll_timer;
struct timer_list sleep_timer;
#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT

10
drivers/net/wireless/ath/ath9k/beacon.c
View File

@ -337,8 +337,14 @@ void ath9k_beacon_tasklet(unsigned long data)
ath9k_hw_check_nav(ah);
if (!ath9k_hw_check_alive(ah))
ieee80211_queue_work(sc->hw, &sc->hw_check_work);
/*
* If the previous beacon has not been transmitted
* and a MAC/BB hang has been identified, return
* here because a chip reset would have been
* initiated.
*/
if (!ath_hw_check(sc))
return;
if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) {
ath_dbg(common, BSTUCK,

2
drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
View File

@ -1077,7 +1077,7 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
if (ieee80211_is_beacon(hdr->frame_control) &&
!is_zero_ether_addr(common->curbssid) &&
ether_addr_equal(hdr->addr3, common->curbssid)) {
ether_addr_equal_64bits(hdr->addr3, common->curbssid)) {
s8 rssi = rxbuf->rxstatus.rs_rssi;
if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))

42
drivers/net/wireless/ath/ath9k/hw-ops.h
View File

@ -107,6 +107,21 @@ static inline void ath9k_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
/* Private hardware call ops */
static inline void ath9k_hw_init_hang_checks(struct ath_hw *ah)
{
ath9k_hw_private_ops(ah)->init_hang_checks(ah);
}
static inline bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
{
return ath9k_hw_private_ops(ah)->detect_mac_hang(ah);
}
static inline bool ath9k_hw_detect_bb_hang(struct ath_hw *ah)
{
return ath9k_hw_private_ops(ah)->detect_bb_hang(ah);
}
/* PHY ops */
static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
@ -232,4 +247,31 @@ static inline void ath9k_hw_set_radar_params(struct ath_hw *ah)
ath9k_hw_private_ops(ah)->set_radar_params(ah, &ah->radar_conf);
}
static inline void ath9k_hw_init_cal_settings(struct ath_hw *ah)
{
ath9k_hw_private_ops(ah)->init_cal_settings(ah);
}
static inline u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
struct ath9k_channel *chan)
{
return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
}
static inline void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
return;
ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
}
static inline void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
{
if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
return;
ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
}
#endif /* ATH9K_HW_OPS_H */

323
drivers/net/wireless/ath/ath9k/hw.c
View File

@ -37,57 +37,6 @@ MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");
static int __init ath9k_init(void)
{
return 0;
}
module_init(ath9k_init);
static void __exit ath9k_exit(void)
{
return;
}
module_exit(ath9k_exit);
/* Private hardware callbacks */
static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
{
ath9k_hw_private_ops(ah)->init_cal_settings(ah);
}
static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
struct ath9k_channel *chan)
{
return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
}
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
return;
ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
}
static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
{
/* You will not have this callback if using the old ANI */
if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
return;
ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
}
/********************/
/* Helper Functions */
/********************/
#ifdef CONFIG_ATH9K_DEBUGFS
#endif
static void ath9k_hw_set_clockrate(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
@ -296,6 +245,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
case AR9300_DEVID_QCA955X:
ah->hw_version.macVersion = AR_SREV_VERSION_9550;
return;
case AR9300_DEVID_AR953X:
ah->hw_version.macVersion = AR_SREV_VERSION_9531;
return;
}
val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
@ -397,9 +349,10 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
static void ath9k_hw_init_config(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
ah->config.dma_beacon_response_time = 1;
ah->config.sw_beacon_response_time = 6;
ah->config.ack_6mb = 0x0;
ah->config.cwm_ignore_extcca = 0;
ah->config.analog_shiftreg = 1;
@ -423,6 +376,24 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
*/
if (num_possible_cpus() > 1)
ah->config.serialize_regmode = SER_REG_MODE_AUTO;
if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
!ah->is_pciexpress)) {
ah->config.serialize_regmode = SER_REG_MODE_ON;
} else {
ah->config.serialize_regmode = SER_REG_MODE_OFF;
}
}
ath_dbg(common, RESET, "serialize_regmode is %d\n",
ah->config.serialize_regmode);
if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
else
ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
}
static void ath9k_hw_init_defaults(struct ath_hw *ah)
@ -435,15 +406,24 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
ah->hw_version.magic = AR5416_MAGIC;
ah->hw_version.subvendorid = 0;
ah->sta_id1_defaults =
AR_STA_ID1_CRPT_MIC_ENABLE |
AR_STA_ID1_MCAST_KSRCH;
ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
AR_STA_ID1_MCAST_KSRCH;
if (AR_SREV_9100(ah))
ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
ah->slottime = ATH9K_SLOT_TIME_9;
ah->globaltxtimeout = (u32) -1;
ah->power_mode = ATH9K_PM_UNDEFINED;
ah->htc_reset_init = true;
ah->ani_function = ATH9K_ANI_ALL;
if (!AR_SREV_9300_20_OR_LATER(ah))
ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
else
ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
}
static int ath9k_hw_init_macaddr(struct ath_hw *ah)
@ -525,6 +505,31 @@ static int __ath9k_hw_init(struct ath_hw *ah)
ath9k_hw_read_revisions(ah);
switch (ah->hw_version.macVersion) {
case AR_SREV_VERSION_5416_PCI:
case AR_SREV_VERSION_5416_PCIE:
case AR_SREV_VERSION_9160:
case AR_SREV_VERSION_9100:
case AR_SREV_VERSION_9280:
case AR_SREV_VERSION_9285:
case AR_SREV_VERSION_9287:
case AR_SREV_VERSION_9271:
case AR_SREV_VERSION_9300:
case AR_SREV_VERSION_9330:
case AR_SREV_VERSION_9485:
case AR_SREV_VERSION_9340:
case AR_SREV_VERSION_9462:
case AR_SREV_VERSION_9550:
case AR_SREV_VERSION_9565:
case AR_SREV_VERSION_9531:
break;
default:
ath_err(common,
"Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
ah->hw_version.macVersion, ah->hw_version.macRev);
return -EOPNOTSUPP;
}
/*
* Read back AR_WA into a permanent copy and set bits 14 and 17.
* We need to do this to avoid RMW of this register. We cannot
@ -558,50 +563,6 @@ static int __ath9k_hw_init(struct ath_hw *ah)
return -EIO;
}
if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
!ah->is_pciexpress)) {
ah->config.serialize_regmode =
SER_REG_MODE_ON;
} else {
ah->config.serialize_regmode =
SER_REG_MODE_OFF;
}
}
ath_dbg(common, RESET, "serialize_regmode is %d\n",
ah->config.serialize_regmode);
if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
else
ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
switch (ah->hw_version.macVersion) {
case AR_SREV_VERSION_5416_PCI:
case AR_SREV_VERSION_5416_PCIE:
case AR_SREV_VERSION_9160:
case AR_SREV_VERSION_9100:
case AR_SREV_VERSION_9280:
case AR_SREV_VERSION_9285:
case AR_SREV_VERSION_9287:
case AR_SREV_VERSION_9271:
case AR_SREV_VERSION_9300:
case AR_SREV_VERSION_9330:
case AR_SREV_VERSION_9485:
case AR_SREV_VERSION_9340:
case AR_SREV_VERSION_9462:
case AR_SREV_VERSION_9550:
case AR_SREV_VERSION_9565:
break;
default:
ath_err(common,
"Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
ah->hw_version.macVersion, ah->hw_version.macRev);
return -EOPNOTSUPP;
}
if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
AR_SREV_9330(ah) || AR_SREV_9550(ah))
ah->is_pciexpress = false;
@ -609,10 +570,6 @@ static int __ath9k_hw_init(struct ath_hw *ah)
ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
ath9k_hw_init_cal_settings(ah);
ah->ani_function = ATH9K_ANI_ALL;
if (!AR_SREV_9300_20_OR_LATER(ah))
ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
if (!ah->is_pciexpress)
ath9k_hw_disablepcie(ah);
@ -631,15 +588,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
return r;
}
if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
else
ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
if (AR_SREV_9330(ah))
ah->bb_watchdog_timeout_ms = 85;
else
ah->bb_watchdog_timeout_ms = 25;
ath9k_hw_init_hang_checks(ah);
common->state = ATH_HW_INITIALIZED;
@ -672,6 +621,7 @@ int ath9k_hw_init(struct ath_hw *ah)
case AR9300_DEVID_AR9462:
case AR9485_DEVID_AR1111:
case AR9300_DEVID_AR9565:
case AR9300_DEVID_AR953X:
break;
default:
if (common->bus_ops->ath_bus_type == ATH_USB)
@ -807,7 +757,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
/* program BB PLL phase_shift */
REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
} else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
} else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
u32 regval, pll2_divint, pll2_divfrac, refdiv;
REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
@ -817,9 +767,15 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
udelay(100);
if (ah->is_clk_25mhz) {
pll2_divint = 0x54;
pll2_divfrac = 0x1eb85;
refdiv = 3;
if (AR_SREV_9531(ah)) {
pll2_divint = 0x1c;
pll2_divfrac = 0xa3d2;
refdiv = 1;
} else {
pll2_divint = 0x54;
pll2_divfrac = 0x1eb85;
refdiv = 3;
}
} else {
if (AR_SREV_9340(ah)) {
pll2_divint = 88;
@ -833,7 +789,10 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
}
regval = REG_READ(ah, AR_PHY_PLL_MODE);
regval |= (0x1 << 16);
if (AR_SREV_9531(ah))
regval |= (0x1 << 22);
else
regval |= (0x1 << 16);
REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
udelay(100);
@ -843,14 +802,33 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
regval = REG_READ(ah, AR_PHY_PLL_MODE);
if (AR_SREV_9340(ah))
regval = (regval & 0x80071fff) | (0x1 << 30) |
(0x1 << 13) | (0x4 << 26) | (0x18 << 19);
regval = (regval & 0x80071fff) |
(0x1 << 30) |
(0x1 << 13) |
(0x4 << 26) |
(0x18 << 19);
else if (AR_SREV_9531(ah))
regval = (regval & 0x01c00fff) |
(0x1 << 31) |
(0x2 << 29) |
(0xa << 25) |
(0x1 << 19) |
(0x6 << 12);
else
regval = (regval & 0x80071fff) | (0x3 << 30) |
(0x1 << 13) | (0x4 << 26) | (0x60 << 19);
regval = (regval & 0x80071fff) |
(0x3 << 30) |
(0x1 << 13) |
(0x4 << 26) |
(0x60 << 19);
REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
REG_WRITE(ah, AR_PHY_PLL_MODE,
REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
if (AR_SREV_9531(ah))
REG_WRITE(ah, AR_PHY_PLL_MODE,
REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
else
REG_WRITE(ah, AR_PHY_PLL_MODE,
REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
udelay(1000);
}
@ -1532,76 +1510,6 @@ static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
}
}
static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
int *hang_state, int *hang_pos)
{
static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
u32 chain_state, dcs_pos, i;
for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
for (i = 0; i < 3; i++) {
if (chain_state == dcu_chain_state[i]) {
*hang_state = chain_state;
*hang_pos = dcs_pos;
return true;
}
}
}
return false;
}
#define DCU_COMPLETE_STATE 1
#define DCU_COMPLETE_STATE_MASK 0x3
#define NUM_STATUS_READS 50
static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
{
u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
u32 i, hang_pos, hang_state, num_state = 6;
comp_state = REG_READ(ah, AR_DMADBG_6);
if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
ath_dbg(ath9k_hw_common(ah), RESET,
"MAC Hang signature not found at DCU complete\n");
return false;
}
chain_state = REG_READ(ah, dcs_reg);
if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
goto hang_check_iter;
dcs_reg = AR_DMADBG_5;
num_state = 4;
chain_state = REG_READ(ah, dcs_reg);
if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
goto hang_check_iter;
ath_dbg(ath9k_hw_common(ah), RESET,
"MAC Hang signature 1 not found\n");
return false;
hang_check_iter:
ath_dbg(ath9k_hw_common(ah), RESET,
"DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
chain_state, comp_state, hang_state, hang_pos);
for (i = 0; i < NUM_STATUS_READS; i++) {
chain_state = REG_READ(ah, dcs_reg);
chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
comp_state = REG_READ(ah, AR_DMADBG_6);
if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
DCU_COMPLETE_STATE) ||
(chain_state != hang_state))
return false;
}
ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
return true;
}
void ath9k_hw_check_nav(struct ath_hw *ah)
{
struct ath_common *common = ath9k_hw_common(ah);
@ -1676,7 +1584,6 @@ static void ath9k_hw_reset_opmode(struct ath_hw *ah,
REG_RMW(ah, AR_STA_ID1, macStaId1
| AR_STA_ID1_RTS_USE_DEF
| (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
| ah->sta_id1_defaults,
~AR_STA_ID1_SADH_MASK);
ath_hw_setbssidmask(common);
@ -1735,7 +1642,7 @@ static void ath9k_hw_init_desc(struct ath_hw *ah)
}
#ifdef __BIG_ENDIAN
else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
AR_SREV_9550(ah))
AR_SREV_9550(ah) || AR_SREV_9531(ah))
REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
else
REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
@ -1865,7 +1772,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
/* Save TSF before chip reset, a cold reset clears it */
tsf = ath9k_hw_gettsf64(ah);
getrawmonotonic(&ts);
usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
saveLedState = REG_READ(ah, AR_CFG_LED) &
(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
@ -1899,7 +1806,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
/* Restore TSF */
getrawmonotonic(&ts);
usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
ath9k_hw_settsf64(ah, tsf + usec);
if (AR_SREV_9280_20_OR_LATER(ah))
@ -2008,10 +1915,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ath9k_hw_loadnf(ah, chan);
ath9k_hw_start_nfcal(ah, true);
if (AR_SREV_9300_20_OR_LATER(ah)) {
if (AR_SREV_9300_20_OR_LATER(ah))
ar9003_hw_bb_watchdog_config(ah);
if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
ar9003_hw_disable_phy_restart(ah);
}
ath9k_hw_apply_gpio_override(ah);
@ -2135,7 +2043,11 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
AR_RTC_FORCE_WAKE_EN);
udelay(50);
if (AR_SREV_9100(ah))
udelay(10000);
else
udelay(50);
for (i = POWER_UP_TIME / 50; i > 0; i--) {
val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
@ -2564,13 +2476,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
/*
* Fast channel change across bands is available
* only for AR9462 and AR9565.
*/
if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
return 0;
}
@ -3084,14 +2989,14 @@ void ath_gen_timer_isr(struct ath_hw *ah)
trigger_mask &= timer_table->timer_mask;
thresh_mask &= timer_table->timer_mask;
trigger_mask &= ~thresh_mask;
for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
timer = timer_table->timers[index];
if (!timer)
continue;
if (!timer->overflow)
continue;
trigger_mask &= ~BIT(index);
timer->overflow(timer->arg);
}

28
drivers/net/wireless/ath/ath9k/hw.h
View File

@ -52,6 +52,7 @@
#define AR9300_DEVID_QCA955X 0x0038
#define AR9485_DEVID_AR1111 0x0037
#define AR9300_DEVID_AR9565 0x0036
#define AR9300_DEVID_AR953X 0x003d
#define AR5416_AR9100_DEVID 0x000b
@ -277,10 +278,24 @@ struct ath9k_hw_capabilities {
u8 txs_len;
};
#define AR_NO_SPUR 0x8000
#define AR_BASE_FREQ_2GHZ 2300
#define AR_BASE_FREQ_5GHZ 4900
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
enum ath9k_hw_hang_checks {
HW_BB_WATCHDOG = BIT(0),
HW_PHYRESTART_CLC_WAR = BIT(1),
HW_BB_RIFS_HANG = BIT(2),
HW_BB_DFS_HANG = BIT(3),
HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
HW_MAC_HANG = BIT(5),
};
struct ath9k_ops_config {
int dma_beacon_response_time;
int sw_beacon_response_time;
int ack_6mb;
u32 cwm_ignore_extcca;
u32 pcie_waen;
u8 analog_shiftreg;
@ -292,13 +307,9 @@ struct ath9k_ops_config {
int serialize_regmode;
bool rx_intr_mitigation;
bool tx_intr_mitigation;
#define AR_NO_SPUR 0x8000
#define AR_BASE_FREQ_2GHZ 2300
#define AR_BASE_FREQ_5GHZ 4900
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
u8 max_txtrig_level;
u16 ani_poll_interval; /* ANI poll interval in ms */
u16 hw_hang_checks;
/* Platform specific config */
u32 aspm_l1_fix;
@ -573,6 +584,10 @@ struct ath_hw_radar_conf {
* register settings through the register initialization.
*/
struct ath_hw_private_ops {
void (*init_hang_checks)(struct ath_hw *ah);
bool (*detect_mac_hang)(struct ath_hw *ah);
bool (*detect_bb_hang)(struct ath_hw *ah);
/* Calibration ops */
void (*init_cal_settings)(struct ath_hw *ah);
bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
@ -1029,6 +1044,7 @@ void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
* Code specific to AR9003, we stuff these here to avoid callbacks
* for older families
*/
bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);

2
drivers/net/wireless/ath/ath9k/init.c
View File

@ -763,10 +763,8 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
INIT_WORK(&sc->hw_reset_work, ath_reset_work);
INIT_WORK(&sc->hw_check_work, ath_hw_check);
INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
/*
* Cache line size is used to size and align various

67
drivers/net/wireless/ath/ath9k/link.c
View File

@ -65,50 +65,26 @@ void ath_tx_complete_poll_work(struct work_struct *work)
/*
* Checks if the BB/MAC is hung.
*/
void ath_hw_check(struct work_struct *work)
bool ath_hw_check(struct ath_softc *sc)
{
struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
unsigned long flags;
int busy;
u8 is_alive, nbeacon = 1;
enum ath_reset_type type;
bool is_alive;
ath9k_ps_wakeup(sc);
is_alive = ath9k_hw_check_alive(sc->sc_ah);
if ((is_alive && !AR_SREV_9300(sc->sc_ah)) || sc->tx99_state)
goto out;
else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
if (!is_alive) {
ath_dbg(common, RESET,
"DCU stuck is detected. Schedule chip reset\n");
"HW hang detected, schedule chip reset\n");
type = RESET_TYPE_MAC_HANG;
goto sched_reset;
ath9k_queue_reset(sc, type);
}
spin_lock_irqsave(&common->cc_lock, flags);
busy = ath_update_survey_stats(sc);
spin_unlock_irqrestore(&common->cc_lock, flags);
ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
busy, sc->hw_busy_count + 1);
if (busy >= 99) {
if (++sc->hw_busy_count >= 3) {
type = RESET_TYPE_BB_HANG;
goto sched_reset;
}
} else if (busy >= 0) {
sc->hw_busy_count = 0;
nbeacon = 3;
}
ath_start_rx_poll(sc, nbeacon);
goto out;
sched_reset:
ath9k_queue_reset(sc, type);
out:
ath9k_ps_restore(sc);
return is_alive;
}
/*
@ -161,29 +137,6 @@ void ath_hw_pll_work(struct work_struct *work)
msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
}
/*
* RX Polling - monitors baseband hangs.
*/
void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
{
if (!AR_SREV_9300(sc->sc_ah))
return;
if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
return;
mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
(nbeacon * sc->cur_beacon_conf.beacon_interval));
}
void ath_rx_poll(unsigned long data)
{
struct ath_softc *sc = (struct ath_softc *)data;
if (!test_bit(SC_OP_INVALID, &sc->sc_flags))
ieee80211_queue_work(sc->hw, &sc->hw_check_work);
}
/*
* PA Pre-distortion.
*/
@ -409,10 +362,10 @@ void ath_ani_calibrate(unsigned long data)
/* Call ANI routine if necessary */
if (aniflag) {
spin_lock_irqsave(&common->cc_lock, flags);
spin_lock(&common->cc_lock);
ath9k_hw_ani_monitor(ah, ah->curchan);
ath_update_survey_stats(sc);
spin_unlock_irqrestore(&common->cc_lock, flags);
spin_unlock(&common->cc_lock);
}
/* Perform calibration if necessary */

24
drivers/net/wireless/ath/ath9k/mac.c
View File

@ -922,11 +922,29 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah)
mask2 |= AR_IMR_S2_CST;
}
if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
if (ints & ATH9K_INT_BB_WATCHDOG) {
mask |= AR_IMR_BCNMISC;
mask2 |= AR_IMR_S2_BB_WATCHDOG;
}
}
ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
REG_WRITE(ah, AR_IMR, mask);
ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
ah->imrs2_reg &= ~(AR_IMR_S2_TIM |
AR_IMR_S2_DTIM |
AR_IMR_S2_DTIMSYNC |
AR_IMR_S2_CABEND |
AR_IMR_S2_CABTO |
AR_IMR_S2_TSFOOR |
AR_IMR_S2_GTT |
AR_IMR_S2_CST);
if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
if (ints & ATH9K_INT_BB_WATCHDOG)
ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG;
}
ah->imrs2_reg |= mask2;
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);

76
drivers/net/wireless/ath/ath9k/main.c
View File

@ -170,7 +170,6 @@ void ath9k_ps_restore(struct ath_softc *sc)
static void __ath_cancel_work(struct ath_softc *sc)
{
cancel_work_sync(&sc->paprd_work);
cancel_work_sync(&sc->hw_check_work);
cancel_delayed_work_sync(&sc->tx_complete_work);
cancel_delayed_work_sync(&sc->hw_pll_work);
@ -194,7 +193,6 @@ void ath_restart_work(struct ath_softc *sc)
ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
ath_start_rx_poll(sc, 3);
ath_start_ani(sc);
}
@ -204,11 +202,7 @@ static bool ath_prepare_reset(struct ath_softc *sc)
bool ret = true;
ieee80211_stop_queues(sc->hw);
sc->hw_busy_count = 0;
ath_stop_ani(sc);
del_timer_sync(&sc->rx_poll_timer);
ath9k_hw_disable_interrupts(ah);
if (!ath_drain_all_txq(sc))
@ -336,7 +330,6 @@ static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chand
struct ieee80211_hw *hw = sc->hw;
struct ath9k_channel *hchan;
struct ieee80211_channel *chan = chandef->chan;
unsigned long flags;
bool offchannel;
int pos = chan->hw_value;
int old_pos = -1;
@ -354,9 +347,9 @@ static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chand
chan->center_freq, chandef->width);
/* update survey stats for the old channel before switching */
spin_lock_irqsave(&common->cc_lock, flags);
spin_lock_bh(&common->cc_lock);
ath_update_survey_stats(sc);
spin_unlock_irqrestore(&common->cc_lock, flags);
spin_unlock_bh(&common->cc_lock);
ath9k_cmn_get_channel(hw, ah, chandef);
@ -427,12 +420,6 @@ static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
an->vif = vif;
ath_tx_node_init(sc, an);
if (sta->ht_cap.ht_supported) {
an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
sta->ht_cap.ampdu_factor);
an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
}
}
static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
@ -454,14 +441,8 @@ void ath9k_tasklet(unsigned long data)
ath9k_ps_wakeup(sc);
spin_lock(&sc->sc_pcu_lock);
if ((status & ATH9K_INT_FATAL) ||
(status & ATH9K_INT_BB_WATCHDOG)) {
if (status & ATH9K_INT_FATAL)
type = RESET_TYPE_FATAL_INT;
else
type = RESET_TYPE_BB_WATCHDOG;
if (status & ATH9K_INT_FATAL) {
type = RESET_TYPE_FATAL_INT;
ath9k_queue_reset(sc, type);
/*
@ -473,6 +454,28 @@ void ath9k_tasklet(unsigned long data)
goto out;
}
if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
(status & ATH9K_INT_BB_WATCHDOG)) {
spin_lock(&common->cc_lock);
ath_hw_cycle_counters_update(common);
ar9003_hw_bb_watchdog_dbg_info(ah);
spin_unlock(&common->cc_lock);
if (ar9003_hw_bb_watchdog_check(ah)) {
type = RESET_TYPE_BB_WATCHDOG;
ath9k_queue_reset(sc, type);
/*
* Increment the ref. counter here so that
* interrupts are enabled in the reset routine.
*/
atomic_inc(&ah->intr_ref_cnt);
ath_dbg(common, ANY,
"BB_WATCHDOG: Skipping interrupts\n");
goto out;
}
}
spin_lock_irqsave(&sc->sc_pm_lock, flags);
if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
/*
@ -541,7 +544,7 @@ irqreturn_t ath_isr(int irq, void *dev)
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
enum ath9k_int status;
u32 sync_cause;
u32 sync_cause = 0;
bool sched = false;
/*
@ -593,16 +596,9 @@ irqreturn_t ath_isr(int irq, void *dev)
!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
goto chip_reset;
if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
(status & ATH9K_INT_BB_WATCHDOG)) {
spin_lock(&common->cc_lock);
ath_hw_cycle_counters_update(common);
ar9003_hw_bb_watchdog_dbg_info(ah);
spin_unlock(&common->cc_lock);
if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
(status & ATH9K_INT_BB_WATCHDOG))
goto chip_reset;
}
#ifdef CONFIG_ATH9K_WOW
if (status & ATH9K_INT_BMISS) {
@ -732,11 +728,13 @@ static int ath9k_start(struct ieee80211_hw *hw)
if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
ah->imask |= ATH9K_INT_RXHP |
ATH9K_INT_RXLP |
ATH9K_INT_BB_WATCHDOG;
ATH9K_INT_RXLP;
else
ah->imask |= ATH9K_INT_RX;
if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
ah->imask |= ATH9K_INT_BB_WATCHDOG;
ah->imask |= ATH9K_INT_GTT;
if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
@ -860,7 +858,6 @@ static void ath9k_stop(struct ieee80211_hw *hw)
mutex_lock(&sc->mutex);
ath_cancel_work(sc);
del_timer_sync(&sc->rx_poll_timer);
if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
ath_dbg(common, ANY, "Device not present\n");
@ -1791,13 +1788,12 @@ static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ieee80211_supported_band *sband;
struct ieee80211_channel *chan;
unsigned long flags;
int pos;
if (config_enabled(CONFIG_ATH9K_TX99))
return -EOPNOTSUPP;
spin_lock_irqsave(&common->cc_lock, flags);
spin_lock_bh(&common->cc_lock);
if (idx == 0)
ath_update_survey_stats(sc);
@ -1811,7 +1807,7 @@ static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
if (!sband || idx >= sband->n_channels) {
spin_unlock_irqrestore(&common->cc_lock, flags);
spin_unlock_bh(&common->cc_lock);
return -ENOENT;
}
@ -1819,7 +1815,7 @@ static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
pos = chan->hw_value;
memcpy(survey, &sc->survey[pos], sizeof(*survey));
survey->channel = chan;
spin_unlock_irqrestore(&common->cc_lock, flags);
spin_unlock_bh(&common->cc_lock);
return 0;
}

101
drivers/net/wireless/ath/ath9k/pci.c
View File

@ -409,6 +409,16 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
0x11AD, /* LITEON */
0x0632),
.driver_data = ATH9K_PCI_AR9565_1ANT },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
0x06B2),
.driver_data = ATH9K_PCI_AR9565_1ANT },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
0x0842),
.driver_data = ATH9K_PCI_AR9565_1ANT },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
@ -424,6 +434,16 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
0x1B9A, /* XAVI */
0x2812),
.driver_data = ATH9K_PCI_AR9565_1ANT },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x1B9A, /* XAVI */
0x28A1),
.driver_data = ATH9K_PCI_AR9565_1ANT },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_AZWAVE,
0x218A),
.driver_data = ATH9K_PCI_AR9565_1ANT },
/* WB335 1-ANT / Antenna Diversity */
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
@ -466,6 +486,11 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
0x11AD, /* LITEON */
0x0662),
.driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
0x06A2),
.driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
@ -476,16 +501,6 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
PCI_VENDOR_ID_AZWAVE,
0x213A),
.driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_LENOVO,
0x3026),
.driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_LENOVO,
0x4026),
.driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_HP,
@ -504,37 +519,35 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_DELL,
0x020E),
0x020C),
.driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
/* WB335 2-ANT */
/* WB335 2-ANT / Antenna-Diversity */
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_SAMSUNG,
0x411A),
.driver_data = ATH9K_PCI_AR9565_2ANT },
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_SAMSUNG,
0x411B),
.driver_data = ATH9K_PCI_AR9565_2ANT },
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_SAMSUNG,
0x411C),
.driver_data = ATH9K_PCI_AR9565_2ANT },
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_SAMSUNG,
0x411D),
.driver_data = ATH9K_PCI_AR9565_2ANT },
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_SAMSUNG,
0x411E),
.driver_data = ATH9K_PCI_AR9565_2ANT },
/* WB335 2-ANT / Antenna-Diversity */
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_ATHEROS,
@ -560,11 +573,31 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
0x11AD, /* LITEON */
0x0612),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
0x0832),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x11AD, /* LITEON */
0x0692),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_AZWAVE,
0x2130),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_AZWAVE,
0x213B),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_AZWAVE,
0x2182),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x144F, /* ASKEY */
@ -575,6 +608,11 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
0x1B9A, /* XAVI */
0x2810),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x1B9A, /* XAVI */
0x28A2),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
0x185F, /* WNC */
@ -590,6 +628,31 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
PCI_VENDOR_ID_FOXCONN,
0xE07F),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_FOXCONN,
0xE081),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_LENOVO,
0x3026),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_LENOVO,
0x4026),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_ASUSTEK,
0x85F2),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0036,
PCI_VENDOR_ID_DELL,
0x020E),
.driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
/* PCI-E AR9565 (WB335) */
{ PCI_VDEVICE(ATHEROS, 0x0036),

31
drivers/net/wireless/ath/ath9k/recv.c
View File

@ -419,7 +419,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
}
if (AR_SREV_9550(sc->sc_ah))
if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah))
rfilt |= ATH9K_RX_FILTER_4ADDRESS;
return rfilt;
@ -850,20 +850,15 @@ static int ath9k_process_rate(struct ath_common *common,
enum ieee80211_band band;
unsigned int i = 0;
struct ath_softc __maybe_unused *sc = common->priv;
struct ath_hw *ah = sc->sc_ah;
band = hw->conf.chandef.chan->band;
band = ah->curchan->chan->band;
sband = hw->wiphy->bands[band];
switch (hw->conf.chandef.width) {
case NL80211_CHAN_WIDTH_5:
if (IS_CHAN_QUARTER_RATE(ah->curchan))
rxs->flag |= RX_FLAG_5MHZ;
break;
case NL80211_CHAN_WIDTH_10:
else if (IS_CHAN_HALF_RATE(ah->curchan))
rxs->flag |= RX_FLAG_10MHZ;
break;
default:
break;
}
if (rx_stats->rs_rate & 0x80) {
/* HT rate */
@ -982,7 +977,7 @@ static bool ath9k_is_mybeacon(struct ath_softc *sc, struct ieee80211_hdr *hdr)
if (ieee80211_is_beacon(hdr->frame_control)) {
RX_STAT_INC(rx_beacons);
if (!is_zero_ether_addr(common->curbssid) &&
ether_addr_equal(hdr->addr3, common->curbssid))
ether_addr_equal_64bits(hdr->addr3, common->curbssid))
return true;
}
@ -1077,9 +1072,13 @@ static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
}
rx_stats->is_mybeacon = ath9k_is_mybeacon(sc, hdr);
if (rx_stats->is_mybeacon) {
sc->hw_busy_count = 0;
ath_start_rx_poll(sc, 3);
/*
* This shouldn't happen, but have a safety check anyway.
*/
if (WARN_ON(!ah->curchan)) {
ret = -EINVAL;
goto exit;
}
if (ath9k_process_rate(common, hw, rx_stats, rx_status)) {
@ -1089,8 +1088,8 @@ static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
ath9k_process_rssi(common, hw, rx_stats, rx_status);
rx_status->band = hw->conf.chandef.chan->band;
rx_status->freq = hw->conf.chandef.chan->center_freq;
rx_status->band = ah->curchan->chan->band;
rx_status->freq = ah->curchan->chan->center_freq;
rx_status->antenna = rx_stats->rs_antenna;
rx_status->flag |= RX_FLAG_MACTIME_END;

14
drivers/net/wireless/ath/ath9k/reg.h
View File

@ -304,6 +304,7 @@
#define AR_IMR_S2 0x00ac
#define AR_IMR_S2_QCU_TXURN 0x000003FF
#define AR_IMR_S2_QCU_TXURN_S 0
#define AR_IMR_S2_BB_WATCHDOG 0x00010000
#define AR_IMR_S2_CST 0x00400000
#define AR_IMR_S2_GTT 0x00800000
#define AR_IMR_S2_TIM 0x01000000
@ -812,6 +813,9 @@
#define AR_SREV_REVISION_9565_101 1
#define AR_SREV_REVISION_9565_11 2
#define AR_SREV_VERSION_9550 0x400
#define AR_SREV_VERSION_9531 0x500
#define AR_SREV_REVISION_9531_10 0
#define AR_SREV_REVISION_9531_11 1
#define AR_SREV_5416(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@ -945,11 +949,19 @@
#define AR_SREV_9580(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))
#define AR_SREV_9580_10(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9580_10))
#define AR_SREV_9531(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531))
#define AR_SREV_9531_10(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_10))
#define AR_SREV_9531_11(_ah) \
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \
((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_11))
/* NOTE: When adding chips newer than Peacock, add chip check here */
#define AR_SREV_9580_10_OR_LATER(_ah) \
(AR_SREV_9580(_ah))

2
drivers/net/wireless/ath/ath9k/spectral.c
View File

@ -497,7 +497,7 @@ static int remove_buf_file_handler(struct dentry *dentry)
return 0;
}
struct rchan_callbacks rfs_spec_scan_cb = {
static struct rchan_callbacks rfs_spec_scan_cb = {
.create_buf_file = create_buf_file_handler,
.remove_buf_file = remove_buf_file_handler,
};

1
drivers/net/wireless/ath/ath9k/wow.c
View File

@ -197,7 +197,6 @@ int ath9k_suspend(struct ieee80211_hw *hw,
ath_cancel_work(sc);
ath_stop_ani(sc);
del_timer_sync(&sc->rx_poll_timer);
if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
ath_dbg(common, ANY, "Device not present\n");

9
drivers/net/wireless/ath/ath9k/xmit.c
View File

@ -774,11 +774,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
if (bt_aggr_limit)
aggr_limit = bt_aggr_limit;
/*
* h/w can accept aggregates up to 16 bit lengths (65535).
* The IE, however can hold up to 65536, which shows up here
* as zero. Ignore 65536 since we are constrained by hw.
*/
if (tid->an->maxampdu)
aggr_limit = min(aggr_limit, tid->an->maxampdu);
@ -1403,8 +1398,8 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
* has already been added.
*/
if (sta->ht_cap.ht_supported) {
an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
sta->ht_cap.ampdu_factor);
an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
sta->ht_cap.ampdu_factor)) - 1;
density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
an->mpdudensity = density;
}

1
drivers/net/wireless/ath/carl9170/debug.c
View File

@ -37,7 +37,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/seq_file.h>

1
drivers/net/wireless/ath/carl9170/main.c
View File

@ -37,7 +37,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/etherdevice.h>

7
drivers/net/wireless/ath/carl9170/rx.c
View File

@ -37,7 +37,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/etherdevice.h>
@ -536,7 +535,7 @@ static void carl9170_ps_beacon(struct ar9170 *ar, void *data, unsigned int len)
return;
/* and only beacons from the associated BSSID, please */
if (!ether_addr_equal(hdr->addr3, ar->common.curbssid) ||
if (!ether_addr_equal_64bits(hdr->addr3, ar->common.curbssid) ||
!ar->common.curaid)
return;
@ -602,8 +601,8 @@ static void carl9170_ba_check(struct ar9170 *ar, void *data, unsigned int len)
if (bar->start_seq_num == entry_bar->start_seq_num &&
TID_CHECK(bar->control, entry_bar->control) &&
ether_addr_equal(bar->ra, entry_bar->ta) &&
ether_addr_equal(bar->ta, entry_bar->ra)) {
ether_addr_equal_64bits(bar->ra, entry_bar->ta) &&
ether_addr_equal_64bits(bar->ta, entry_bar->ra)) {
struct ieee80211_tx_info *tx_info;
tx_info = IEEE80211_SKB_CB(entry_skb);

1
drivers/net/wireless/ath/carl9170/tx.c
View File

@ -37,7 +37,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/etherdevice.h>

13
drivers/net/wireless/ath/wil6210/interrupt.c
View File

@ -156,6 +156,19 @@ void wil6210_enable_irq(struct wil6210_priv *wil)
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
offsetof(struct RGF_ICR, ICC));
/* interrupt moderation parameters */
if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
/* disable interrupt moderation for monitor
* to get better timestamp precision
*/
iowrite32(0, wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
} else {
iowrite32(WIL6210_ITR_TRSH,
wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
iowrite32(BIT_DMA_ITR_CNT_CRL_EN,
wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
}
wil6210_unmask_irq_pseudo(wil);
wil6210_unmask_irq_tx(wil);
wil6210_unmask_irq_rx(wil);

8
drivers/net/wireless/ath/wil6210/txrx.c
View File

@ -21,6 +21,7 @@
#include <linux/ip.h>
#include <linux/ipv6.h>
#include <net/ipv6.h>
#include <asm/processor.h>
#include "wil6210.h"
#include "wmi.h"
@ -377,6 +378,8 @@ static struct sk_buff *wil_vring_reap_rx(struct wil6210_priv *wil,
}
skb_trim(skb, dmalen);
prefetch(skb->data);
wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
skb->data, skb_headlen(skb), false);
@ -673,9 +676,12 @@ static int wil_tx_desc_offload_cksum_set(struct wil6210_priv *wil,
if (skb->ip_summed != CHECKSUM_PARTIAL)
return 0;
d->dma.b11 = ETH_HLEN; /* MAC header length */
switch (skb->protocol) {
case cpu_to_be16(ETH_P_IP):
protocol = ip_hdr(skb)->protocol;
d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS);
break;
case cpu_to_be16(ETH_P_IPV6):
protocol = ipv6_hdr(skb)->nexthdr;
@ -701,8 +707,6 @@ static int wil_tx_desc_offload_cksum_set(struct wil6210_priv *wil,
}
d->dma.ip_length = skb_network_header_len(skb);
d->dma.b11 = ETH_HLEN; /* MAC header length */
d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS);
/* Enable TCP/UDP checksum */
d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS);
/* Calculate pseudo-header */

1
drivers/net/wireless/ath/wil6210/wil6210.h
View File

@ -39,6 +39,7 @@ static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
#define WIL6210_MAX_TX_RINGS (24) /* HW limit */
#define WIL6210_MAX_CID (8) /* HW limit */
#define WIL6210_NAPI_BUDGET (16) /* arbitrary */
#define WIL6210_ITR_TRSH (10000) /* arbitrary - about 15 IRQs/msec */
/* Hardware definitions begin */

1
drivers/net/wireless/atmel.c
View File

@ -39,7 +39,6 @@
******************************************************************************/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>

1
drivers/net/wireless/atmel_cs.c
View File

@ -32,7 +32,6 @@
#ifdef __IN_PCMCIA_PACKAGE__
#include <pcmcia/k_compat.h>
#endif
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ptrace.h>

1
drivers/net/wireless/atmel_pci.c
View File

@ -22,7 +22,6 @@
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include "atmel.h"

10
drivers/net/wireless/brcm80211/brcmfmac/bcdc.c
View File

@ -41,9 +41,6 @@ struct brcmf_proto_bcdc_dcmd {
__le32 status; /* status code returned from the device */
};
/* Max valid buffer size that can be sent to the dongle */
#define BCDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
/* BCDC flag definitions */
#define BCDC_DCMD_ERROR 0x01 /* 1=cmd failed */
#define BCDC_DCMD_SET 0x02 /* 0=get, 1=set cmd */
@ -133,9 +130,12 @@ brcmf_proto_bcdc_msg(struct brcmf_pub *drvr, int ifidx, uint cmd, void *buf,
if (buf)
memcpy(bcdc->buf, buf, len);
len += sizeof(*msg);
if (len > BRCMF_TX_IOCTL_MAX_MSG_SIZE)
len = BRCMF_TX_IOCTL_MAX_MSG_SIZE;
/* Send request */
return brcmf_bus_txctl(drvr->bus_if, (unsigned char *)&bcdc->msg,
len + sizeof(struct brcmf_proto_bcdc_dcmd));
return brcmf_bus_txctl(drvr->bus_if, (unsigned char *)&bcdc->msg, len);
}
static int brcmf_proto_bcdc_cmplt(struct brcmf_pub *drvr, u32 id, u32 len)

252
drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
View File

@ -47,8 +47,6 @@
#define SDIOH_API_ACCESS_RETRY_LIMIT 2
#define SDIO_VENDOR_ID_BROADCOM 0x02d0
#define DMA_ALIGN_MASK 0x03
#define SDIO_FUNC1_BLOCKSIZE 64
@ -216,94 +214,104 @@ static inline int brcmf_sdiod_f0_writeb(struct sdio_func *func,
return err_ret;
}
static int brcmf_sdiod_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw,
uint func, uint regaddr, u8 *byte)
static int brcmf_sdiod_request_data(struct brcmf_sdio_dev *sdiodev, u8 fn,
u32 addr, u8 regsz, void *data, bool write)
{
int err_ret;
brcmf_dbg(SDIO, "rw=%d, func=%d, addr=0x%05x\n", rw, func, regaddr);
brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_byte_wait);
if (brcmf_sdiod_pm_resume_error(sdiodev))
return -EIO;
if (rw && func == 0) {
/* handle F0 separately */
err_ret = brcmf_sdiod_f0_writeb(sdiodev->func[func],
regaddr, *byte);
} else {
if (rw) /* CMD52 Write */
sdio_writeb(sdiodev->func[func], *byte, regaddr,
&err_ret);
else if (func == 0) {
*byte = sdio_f0_readb(sdiodev->func[func], regaddr,
&err_ret);
} else {
*byte = sdio_readb(sdiodev->func[func], regaddr,
&err_ret);
}
}
if (err_ret) {
/*
* SleepCSR register access can fail when
* waking up the device so reduce this noise
* in the logs.
*/
if (regaddr != SBSDIO_FUNC1_SLEEPCSR)
brcmf_err("Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
rw ? "write" : "read", func, regaddr, *byte,
err_ret);
else
brcmf_dbg(SDIO, "Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
rw ? "write" : "read", func, regaddr, *byte,
err_ret);
}
return err_ret;
}
static int brcmf_sdiod_request_word(struct brcmf_sdio_dev *sdiodev, uint rw,
uint func, uint addr, u32 *word,
uint nbytes)
{
int err_ret = -EIO;
if (func == 0) {
brcmf_err("Only CMD52 allowed to F0\n");
return -EINVAL;
}
struct sdio_func *func;
int ret;
brcmf_dbg(SDIO, "rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
rw, func, addr, nbytes);
write, fn, addr, regsz);
brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_word_wait);
if (brcmf_sdiod_pm_resume_error(sdiodev))
return -EIO;
if (rw) { /* CMD52 Write */
if (nbytes == 4)
sdio_writel(sdiodev->func[func], *word, addr,
&err_ret);
else if (nbytes == 2)
sdio_writew(sdiodev->func[func], (*word & 0xFFFF),
addr, &err_ret);
/* only allow byte access on F0 */
if (WARN_ON(regsz > 1 && !fn))
return -EINVAL;
func = sdiodev->func[fn];
switch (regsz) {
case sizeof(u8):
if (write) {
if (fn)
sdio_writeb(func, *(u8 *)data, addr, &ret);
else
ret = brcmf_sdiod_f0_writeb(func, addr,
*(u8 *)data);
} else {
if (fn)
*(u8 *)data = sdio_readb(func, addr, &ret);
else
*(u8 *)data = sdio_f0_readb(func, addr, &ret);
}
break;
case sizeof(u16):
if (write)
sdio_writew(func, *(u16 *)data, addr, &ret);
else
brcmf_err("Invalid nbytes: %d\n", nbytes);
} else { /* CMD52 Read */
if (nbytes == 4)
*word = sdio_readl(sdiodev->func[func], addr, &err_ret);
else if (nbytes == 2)
*word = sdio_readw(sdiodev->func[func], addr,
&err_ret) & 0xFFFF;
*(u16 *)data = sdio_readw(func, addr, &ret);
break;
case sizeof(u32):
if (write)
sdio_writel(func, *(u32 *)data, addr, &ret);
else
brcmf_err("Invalid nbytes: %d\n", nbytes);
*(u32 *)data = sdio_readl(func, addr, &ret);
break;
default:
brcmf_err("invalid size: %d\n", regsz);
break;
}
if (err_ret)
brcmf_err("Failed to %s word, Err: 0x%08x\n",
rw ? "write" : "read", err_ret);
if (ret) {
/*
* SleepCSR register access can fail when
* waking up the device so reduce this noise
* in the logs.
*/
if (addr != SBSDIO_FUNC1_SLEEPCSR)
brcmf_err("failed to %s data F%d@0x%05x, err: %d\n",
write ? "write" : "read", fn, addr, ret);
else
brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, err: %d\n",
write ? "write" : "read", fn, addr, ret);
}
return ret;
}
return err_ret;
static int brcmf_sdiod_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
u8 regsz, void *data, bool write)
{
u8 func_num;
s32 retry = 0;
int ret;
/*
* figure out how to read the register based on address range
* 0x00 ~ 0x7FF: function 0 CCCR and FBR
* 0x10000 ~ 0x1FFFF: function 1 miscellaneous registers
* The rest: function 1 silicon backplane core registers
*/
if ((addr & ~REG_F0_REG_MASK) == 0)
func_num = SDIO_FUNC_0;
else
func_num = SDIO_FUNC_1;
do {
if (!write)
memset(data, 0, regsz);
/* for retry wait for 1 ms till bus get settled down */
if (retry)
usleep_range(1000, 2000);
ret = brcmf_sdiod_request_data(sdiodev, func_num, addr, regsz,
data, write);
} while (ret != 0 && retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
if (ret != 0)
brcmf_err("failed with %d\n", ret);
return ret;
}
static int
@ -311,24 +319,17 @@ brcmf_sdiod_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev, u32 address)
{
int err = 0, i;
u8 addr[3];
s32 retry;
addr[0] = (address >> 8) & SBSDIO_SBADDRLOW_MASK;
addr[1] = (address >> 16) & SBSDIO_SBADDRMID_MASK;
addr[2] = (address >> 24) & SBSDIO_SBADDRHIGH_MASK;
for (i = 0; i < 3; i++) {
retry = 0;
do {
if (retry)
usleep_range(1000, 2000);
err = brcmf_sdiod_request_byte(sdiodev, SDIOH_WRITE,
SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW + i,
&addr[i]);
} while (err != 0 && retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
err = brcmf_sdiod_regrw_helper(sdiodev,
SBSDIO_FUNC1_SBADDRLOW + i,
sizeof(u8), &addr[i], true);
if (err) {
brcmf_err("failed at addr:0x%0x\n",
brcmf_err("failed at addr: 0x%0x\n",
SBSDIO_FUNC1_SBADDRLOW + i);
break;
}
@ -359,61 +360,14 @@ brcmf_sdiod_addrprep(struct brcmf_sdio_dev *sdiodev, uint width, u32 *addr)
return 0;
}
static int brcmf_sdiod_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
void *data, bool write)
{
u8 func_num, reg_size;
s32 retry = 0;
int ret;
/*
* figure out how to read the register based on address range
* 0x00 ~ 0x7FF: function 0 CCCR and FBR
* 0x10000 ~ 0x1FFFF: function 1 miscellaneous registers
* The rest: function 1 silicon backplane core registers
*/
if ((addr & ~REG_F0_REG_MASK) == 0) {
func_num = SDIO_FUNC_0;
reg_size = 1;
} else if ((addr & ~REG_F1_MISC_MASK) == 0) {
func_num = SDIO_FUNC_1;
reg_size = 1;
} else {
func_num = SDIO_FUNC_1;
reg_size = 4;
ret = brcmf_sdiod_addrprep(sdiodev, reg_size, &addr);
if (ret)
goto done;
}
do {
if (!write)
memset(data, 0, reg_size);
if (retry) /* wait for 1 ms till bus get settled down */
usleep_range(1000, 2000);
if (reg_size == 1)
ret = brcmf_sdiod_request_byte(sdiodev, write,
func_num, addr, data);
else
ret = brcmf_sdiod_request_word(sdiodev, write,
func_num, addr, data, 4);
} while (ret != 0 && retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
done:
if (ret != 0)
brcmf_err("failed with %d\n", ret);
return ret;
}
u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
{
u8 data;
int retval;
brcmf_dbg(SDIO, "addr:0x%08x\n", addr);
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, &data, false);
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
false);
brcmf_dbg(SDIO, "data:0x%02x\n", data);
if (ret)
@ -428,9 +382,14 @@ u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
int retval;
brcmf_dbg(SDIO, "addr:0x%08x\n", addr);
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, &data, false);
retval = brcmf_sdiod_addrprep(sdiodev, sizeof(data), &addr);
if (retval)
goto done;
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
false);
brcmf_dbg(SDIO, "data:0x%08x\n", data);
done:
if (ret)
*ret = retval;
@ -443,8 +402,8 @@ void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
int retval;
brcmf_dbg(SDIO, "addr:0x%08x, data:0x%02x\n", addr, data);
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, &data, true);
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
true);
if (ret)
*ret = retval;
}
@ -455,8 +414,13 @@ void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
int retval;
brcmf_dbg(SDIO, "addr:0x%08x, data:0x%08x\n", addr, data);
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, &data, true);
retval = brcmf_sdiod_addrprep(sdiodev, sizeof(data), &addr);
if (retval)
goto done;
retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
true);
done:
if (ret)
*ret = retval;
}
@ -879,8 +843,8 @@ int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn)
brcmf_dbg(SDIO, "Enter\n");
/* issue abort cmd52 command through F0 */
brcmf_sdiod_request_byte(sdiodev, SDIOH_WRITE, SDIO_FUNC_0,
SDIO_CCCR_ABORT, &t_func);
brcmf_sdiod_request_data(sdiodev, SDIO_FUNC_0, SDIO_CCCR_ABORT,
sizeof(t_func), &t_func, true);
brcmf_dbg(SDIO, "Exit\n");
return 0;
@ -981,6 +945,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
{SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
{SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)},
{SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334)},
{SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43362)},
{SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM,
SDIO_DEVICE_ID_BROADCOM_4335_4339)},
{ /* end: all zeroes */ },
@ -1037,7 +1002,6 @@ static int brcmf_ops_sdio_probe(struct sdio_func *func,
sdiodev->pdata = brcmfmac_sdio_pdata;
atomic_set(&sdiodev->suspend, false);
init_waitqueue_head(&sdiodev->request_byte_wait);
init_waitqueue_head(&sdiodev->request_word_wait);
init_waitqueue_head(&sdiodev->request_buffer_wait);

7
drivers/net/wireless/brcm80211/brcmfmac/dhd.h
View File

@ -21,8 +21,6 @@
#ifndef _BRCMF_H_
#define _BRCMF_H_
#define BRCMF_VERSION_STR "4.218.248.5"
#include "fweh.h"
#define TOE_TX_CSUM_OL 0x00000001
@ -39,6 +37,11 @@
#define BRCMF_DCMD_MEDLEN 1536
#define BRCMF_DCMD_MAXLEN 8192
/* IOCTL from host to device are limited in lenght. A device can only handle
* ethernet frame size. This limitation is to be applied by protocol layer.
*/
#define BRCMF_TX_IOCTL_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
#define BRCMF_AMPDU_RX_REORDER_MAXFLOWS 256
/* Length of firmware version string stored for

9
drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
View File

@ -32,15 +32,6 @@
#define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
#define BRCMF_DEFAULT_PACKET_FILTER "100 0 0 0 0x01 0x00"
#ifdef DEBUG
static const char brcmf_version[] =
"Dongle Host Driver, version " BRCMF_VERSION_STR "\nCompiled on "
__DATE__ " at " __TIME__;
#else
static const char brcmf_version[] =
"Dongle Host Driver, version " BRCMF_VERSION_STR;
#endif
bool brcmf_c_prec_enq(struct device *dev, struct pktq *q,
struct sk_buff *pkt, int prec)

9
drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
View File

@ -702,7 +702,7 @@ int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
ndev->destructor = free_netdev;
ndev->destructor = brcmf_cfg80211_free_netdev;
return 0;
fail:
@ -859,8 +859,6 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
}
/* unregister will take care of freeing it */
unregister_netdev(ifp->ndev);
if (bssidx == 0)
brcmf_cfg80211_detach(drvr->config);
} else {
kfree(ifp);
}
@ -963,8 +961,7 @@ int brcmf_bus_start(struct device *dev)
fail:
if (ret < 0) {
brcmf_err("failed: %d\n", ret);
if (drvr->config)
brcmf_cfg80211_detach(drvr->config);
brcmf_cfg80211_detach(drvr->config);
if (drvr->fws) {
brcmf_fws_del_interface(ifp);
brcmf_fws_deinit(drvr);
@ -1039,6 +1036,8 @@ void brcmf_detach(struct device *dev)
brcmf_del_if(drvr, i);
}
brcmf_cfg80211_detach(drvr->config);
brcmf_bus_detach(drvr);
brcmf_proto_detach(drvr);

167
drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
View File

@ -509,6 +509,8 @@ enum brcmf_sdio_frmtype {
#define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
#define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
#define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
#define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
#define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
#define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
#define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
@ -526,6 +528,8 @@ MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
@ -552,6 +556,7 @@ static const struct brcmf_firmware_names brcmf_fwname_data[] = {
{ BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
{ BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
{ BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
{ BCM43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
{ BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }
};
@ -3384,7 +3389,8 @@ err:
static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus)
{
u32 addr, reg;
u32 addr, reg, pmu_cc3_mask = ~0;
int err;
brcmf_dbg(TRACE, "Enter\n");
@ -3392,13 +3398,27 @@ static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus)
if (bus->ci->pmurev < 17)
return false;
/* read PMU chipcontrol register 3*/
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL);
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
switch (bus->ci->chip) {
case BCM43241_CHIP_ID:
case BCM4335_CHIP_ID:
case BCM4339_CHIP_ID:
/* read PMU chipcontrol register 3 */
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL);
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
return (reg & pmu_cc3_mask) != 0;
default:
addr = CORE_CC_REG(bus->ci->c_inf[0].base, pmucapabilities_ext);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, &err);
if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
return false;
return (bool)reg;
addr = CORE_CC_REG(bus->ci->c_inf[0].base, retention_ctl);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
}
}
static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
@ -3615,7 +3635,7 @@ static int brcmf_sdio_bus_init(struct device *dev)
}
/* If we didn't come up, turn off backplane clock */
if (bus_if->state != BRCMF_BUS_DATA)
if (ret != 0)
brcmf_sdio_clkctl(bus, CLK_NONE, false);
exit:
@ -3750,31 +3770,6 @@ static void brcmf_sdio_dataworker(struct work_struct *work)
}
}
static void brcmf_sdio_release_malloc(struct brcmf_sdio *bus)
{
brcmf_dbg(TRACE, "Enter\n");
kfree(bus->rxbuf);
bus->rxctl = bus->rxbuf = NULL;
bus->rxlen = 0;
}
static bool brcmf_sdio_probe_malloc(struct brcmf_sdio *bus)
{
brcmf_dbg(TRACE, "Enter\n");
if (bus->sdiodev->bus_if->maxctl) {
bus->rxblen =
roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
ALIGNMENT) + bus->head_align;
bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
if (!(bus->rxbuf))
return false;
}
return true;
}
static bool
brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
{
@ -3888,39 +3883,6 @@ fail:
return false;
}
static bool brcmf_sdio_probe_init(struct brcmf_sdio *bus)
{
brcmf_dbg(TRACE, "Enter\n");
sdio_claim_host(bus->sdiodev->func[1]);
/* Disable F2 to clear any intermediate frame state on the dongle */
sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
bus->rxflow = false;
/* Done with backplane-dependent accesses, can drop clock... */
brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
sdio_release_host(bus->sdiodev->func[1]);
/* ...and initialize clock/power states */
bus->clkstate = CLK_SDONLY;
bus->idletime = BRCMF_IDLE_INTERVAL;
bus->idleclock = BRCMF_IDLE_ACTIVE;
/* Query the F2 block size, set roundup accordingly */
bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
bus->roundup = min(max_roundup, bus->blocksize);
/* SR state */
bus->sleeping = false;
bus->sr_enabled = false;
return true;
}
static int
brcmf_sdio_watchdog_thread(void *data)
{
@ -3955,24 +3917,6 @@ brcmf_sdio_watchdog(unsigned long data)
}
}
static void brcmf_sdio_release_dongle(struct brcmf_sdio *bus)
{
brcmf_dbg(TRACE, "Enter\n");
if (bus->ci) {
sdio_claim_host(bus->sdiodev->func[1]);
brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
brcmf_sdio_clkctl(bus, CLK_NONE, false);
sdio_release_host(bus->sdiodev->func[1]);
brcmf_sdio_chip_detach(&bus->ci);
if (bus->vars && bus->varsz)
kfree(bus->vars);
bus->vars = NULL;
}
brcmf_dbg(TRACE, "Disconnected\n");
}
static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
.stop = brcmf_sdio_bus_stop,
.preinit = brcmf_sdio_bus_preinit,
@ -4066,15 +4010,42 @@ struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
}
/* Allocate buffers */
if (!(brcmf_sdio_probe_malloc(bus))) {
brcmf_err("brcmf_sdio_probe_malloc failed\n");
goto fail;
if (bus->sdiodev->bus_if->maxctl) {
bus->rxblen =
roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
ALIGNMENT) + bus->head_align;
bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
if (!(bus->rxbuf)) {
brcmf_err("rxbuf allocation failed\n");
goto fail;
}
}
if (!(brcmf_sdio_probe_init(bus))) {
brcmf_err("brcmf_sdio_probe_init failed\n");
goto fail;
}
sdio_claim_host(bus->sdiodev->func[1]);
/* Disable F2 to clear any intermediate frame state on the dongle */
sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
bus->rxflow = false;
/* Done with backplane-dependent accesses, can drop clock... */
brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
sdio_release_host(bus->sdiodev->func[1]);
/* ...and initialize clock/power states */
bus->clkstate = CLK_SDONLY;
bus->idletime = BRCMF_IDLE_INTERVAL;
bus->idleclock = BRCMF_IDLE_ACTIVE;
/* Query the F2 block size, set roundup accordingly */
bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
bus->roundup = min(max_roundup, bus->blocksize);
/* SR state */
bus->sleeping = false;
bus->sr_enabled = false;
brcmf_sdio_debugfs_create(bus);
brcmf_dbg(INFO, "completed!!\n");
@ -4108,12 +4079,20 @@ void brcmf_sdio_remove(struct brcmf_sdio *bus)
if (bus->sdiodev->bus_if->drvr) {
brcmf_detach(bus->sdiodev->dev);
brcmf_sdio_release_dongle(bus);
}
if (bus->ci) {
sdio_claim_host(bus->sdiodev->func[1]);
brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
brcmf_sdio_clkctl(bus, CLK_NONE, false);
sdio_release_host(bus->sdiodev->func[1]);
brcmf_sdio_chip_detach(&bus->ci);
}
brcmu_pkt_buf_free_skb(bus->txglom_sgpad);
brcmf_sdio_release_malloc(bus);
kfree(bus->rxbuf);
kfree(bus->hdrbuf);
kfree(bus->vars);
kfree(bus);
}
@ -4131,7 +4110,7 @@ void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
}
/* don't start the wd until fw is loaded */
if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN)
if (bus->sdiodev->bus_if->state != BRCMF_BUS_DATA)
return;
if (wdtick) {

2
drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c
View File

@ -1873,7 +1873,7 @@ int brcmf_fws_process_skb(struct brcmf_if *ifp, struct sk_buff *skb)
brcmf_dbg(DATA, "tx proto=0x%X\n", ntohs(eh->h_proto));
/* determine the priority */
if (!skb->priority)
skb->priority = cfg80211_classify8021d(skb);
skb->priority = cfg80211_classify8021d(skb, NULL);
drvr->tx_multicast += !!multicast;
if (pae)

43
drivers/net/wireless/brcm80211/brcmfmac/p2p.c
View File

@ -1955,21 +1955,21 @@ s32 brcmf_p2p_attach(struct brcmf_cfg80211_info *cfg)
err = brcmf_fil_iovar_int_set(pri_ifp, "p2p_disc", 1);
if (err < 0) {
brcmf_err("set p2p_disc error\n");
brcmf_free_vif(cfg, p2p_vif);
brcmf_free_vif(p2p_vif);
goto exit;
}
/* obtain bsscfg index for P2P discovery */
err = brcmf_fil_iovar_int_get(pri_ifp, "p2p_dev", &bssidx);
if (err < 0) {
brcmf_err("retrieving discover bsscfg index failed\n");
brcmf_free_vif(cfg, p2p_vif);
brcmf_free_vif(p2p_vif);
goto exit;
}
/* Verify that firmware uses same bssidx as driver !! */
if (p2p_ifp->bssidx != bssidx) {
brcmf_err("Incorrect bssidx=%d, compared to p2p_ifp->bssidx=%d\n",
bssidx, p2p_ifp->bssidx);
brcmf_free_vif(cfg, p2p_vif);
brcmf_free_vif(p2p_vif);
goto exit;
}
@ -1997,7 +1997,7 @@ void brcmf_p2p_detach(struct brcmf_p2p_info *p2p)
brcmf_p2p_cancel_remain_on_channel(vif->ifp);
brcmf_p2p_deinit_discovery(p2p);
/* remove discovery interface */
brcmf_free_vif(p2p->cfg, vif);
brcmf_free_vif(vif);
p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
}
/* just set it all to zero */
@ -2222,7 +2222,7 @@ static struct wireless_dev *brcmf_p2p_create_p2pdev(struct brcmf_p2p_info *p2p,
return &p2p_vif->wdev;
fail:
brcmf_free_vif(p2p->cfg, p2p_vif);
brcmf_free_vif(p2p_vif);
return ERR_PTR(err);
}
@ -2231,31 +2231,12 @@ fail:
*
* @vif: virtual interface object to delete.
*/
static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_info *cfg,
static void brcmf_p2p_delete_p2pdev(struct brcmf_p2p_info *p2p,
struct brcmf_cfg80211_vif *vif)
{
cfg80211_unregister_wdev(&vif->wdev);
cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
brcmf_free_vif(cfg, vif);
}
/**
* brcmf_p2p_free_p2p_if() - free up net device related data.
*
* @ndev: net device that needs to be freed.
*/
static void brcmf_p2p_free_p2p_if(struct net_device *ndev)
{
struct brcmf_cfg80211_info *cfg;
struct brcmf_cfg80211_vif *vif;
struct brcmf_if *ifp;
ifp = netdev_priv(ndev);
cfg = ifp->drvr->config;
vif = ifp->vif;
brcmf_free_vif(cfg, vif);
free_netdev(ifp->ndev);
p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
brcmf_free_vif(vif);
}
/**
@ -2335,8 +2316,6 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
brcmf_err("Registering netdevice failed\n");
goto fail;
}
/* override destructor */
ifp->ndev->destructor = brcmf_p2p_free_p2p_if;
cfg->p2p.bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = vif;
/* Disable firmware roaming for P2P interface */
@ -2349,7 +2328,7 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
return &ifp->vif->wdev;
fail:
brcmf_free_vif(cfg, vif);
brcmf_free_vif(vif);
return ERR_PTR(err);
}
@ -2358,8 +2337,6 @@ fail:
*
* @wiphy: wiphy device of interface.
* @wdev: wireless device of interface.
*
* TODO: not yet supported.
*/
int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
{
@ -2385,7 +2362,7 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
break;
case NL80211_IFTYPE_P2P_DEVICE:
brcmf_p2p_delete_p2pdev(cfg, vif);
brcmf_p2p_delete_p2pdev(p2p, vif);
return 0;
default:
return -ENOTSUPP;

46
drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
View File

@ -19,6 +19,7 @@
#include <linux/netdevice.h>
#include <linux/mmc/card.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/ssb/ssb_regs.h>
#include <linux/bcma/bcma.h>
@ -83,6 +84,24 @@ static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
{0, 0x1}
};
/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
{6, 0x7},
{5, 0x6},
{4, 0x5},
{3, 0x4},
{2, 0x2},
{1, 0x1},
{0, 0x0}
};
/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
{3, 0x3},
{2, 0x2},
{1, 0x1},
{0, 0x0} };
/* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
{16, 0x7},
@ -569,6 +588,23 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
ci->ramsize = 0xc0000;
ci->rambase = 0x180000;
break;
case BCM43362_CHIP_ID:
ci->c_inf[0].wrapbase = 0x18100000;
ci->c_inf[0].cib = 0x27004211;
ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
ci->c_inf[1].base = 0x18002000;
ci->c_inf[1].wrapbase = 0x18102000;
ci->c_inf[1].cib = 0x0a004211;
ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
ci->c_inf[2].base = 0x18004000;
ci->c_inf[2].wrapbase = 0x18104000;
ci->c_inf[2].cib = 0x08080401;
ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
ci->c_inf[3].base = 0x18003000;
ci->c_inf[3].wrapbase = 0x18103000;
ci->c_inf[3].cib = 0x03004211;
ci->ramsize = 0x3C000;
break;
default:
brcmf_err("chipid 0x%x is not supported\n", ci->chip);
return -ENODEV;
@ -757,6 +793,11 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
str_mask = 0x00003800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
str_tab = sdiod_drvstr_tab6_1v8;
str_mask = 0x00001800;
str_shift = 11;
break;
case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
/* note: 43143 does not support tristate */
i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
@ -769,6 +810,11 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
brcmf_sdio_chip_name(ci->chip, chn, 8),
drivestrength);
break;
case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
str_tab = sdiod_drive_strength_tab5_1v8;
str_mask = 0x00003800;
str_shift = 11;
break;
default:
brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
brcmf_sdio_chip_name(ci->chip, chn, 8),

8
drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
View File

@ -54,14 +54,6 @@
#define BRCMF_MAX_CORENUM 6
/* SDIO device ID */
#define SDIO_DEVICE_ID_BROADCOM_43143 43143
#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
#define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
struct chip_core_info {
u16 id;
u16 rev;

1
drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h
View File

@ -167,7 +167,6 @@ struct brcmf_sdio_dev {
u32 sbwad; /* Save backplane window address */
struct brcmf_sdio *bus;
atomic_t suspend; /* suspend flag */
wait_queue_head_t request_byte_wait;
wait_queue_head_t request_word_wait;
wait_queue_head_t request_buffer_wait;
struct device *dev;

164
drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
View File

@ -1095,10 +1095,10 @@ static void brcmf_link_down(struct brcmf_cfg80211_vif *vif)
BRCMF_C_DISASSOC, NULL, 0);
if (err) {
brcmf_err("WLC_DISASSOC failed (%d)\n", err);
cfg80211_disconnected(vif->wdev.netdev, 0,
NULL, 0, GFP_KERNEL);
}
clear_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state);
cfg80211_disconnected(vif->wdev.netdev, 0, NULL, 0, GFP_KERNEL);
}
clear_bit(BRCMF_VIF_STATUS_CONNECTING, &vif->sme_state);
clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
@ -1758,6 +1758,7 @@ brcmf_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *ndev,
return -EIO;
clear_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state);
cfg80211_disconnected(ndev, reason_code, NULL, 0, GFP_KERNEL);
memcpy(&scbval.ea, &profile->bssid, ETH_ALEN);
scbval.val = cpu_to_le32(reason_code);
@ -4359,9 +4360,6 @@ struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
{
struct brcmf_cfg80211_vif *vif;
if (cfg->vif_cnt == BRCMF_IFACE_MAX_CNT)
return ERR_PTR(-ENOSPC);
brcmf_dbg(TRACE, "allocating virtual interface (size=%zu)\n",
sizeof(*vif));
vif = kzalloc(sizeof(*vif), GFP_KERNEL);
@ -4378,21 +4376,25 @@ struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
brcmf_init_prof(&vif->profile);
list_add_tail(&vif->list, &cfg->vif_list);
cfg->vif_cnt++;
return vif;
}
void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
struct brcmf_cfg80211_vif *vif)
void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
{
list_del(&vif->list);
cfg->vif_cnt--;
kfree(vif);
if (!cfg->vif_cnt) {
wiphy_unregister(cfg->wiphy);
wiphy_free(cfg->wiphy);
}
}
void brcmf_cfg80211_free_netdev(struct net_device *ndev)
{
struct brcmf_cfg80211_vif *vif;
struct brcmf_if *ifp;
ifp = netdev_priv(ndev);
vif = ifp->vif;
brcmf_free_vif(vif);
free_netdev(ndev);
}
static bool brcmf_is_linkup(const struct brcmf_event_msg *e)
@ -4979,20 +4981,20 @@ cfg80211_p2p_attach_out:
wl_deinit_priv(cfg);
cfg80211_attach_out:
brcmf_free_vif(cfg, vif);
brcmf_free_vif(vif);
return NULL;
}
void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
{
struct brcmf_cfg80211_vif *vif;
struct brcmf_cfg80211_vif *tmp;
if (!cfg)
return;
wl_deinit_priv(cfg);
WARN_ON(!list_empty(&cfg->vif_list));
wiphy_unregister(cfg->wiphy);
brcmf_btcoex_detach(cfg);
list_for_each_entry_safe(vif, tmp, &cfg->vif_list, list) {
brcmf_free_vif(cfg, vif);
}
wl_deinit_priv(cfg);
wiphy_free(cfg->wiphy);
}
static s32
@ -5087,7 +5089,8 @@ dongle_scantime_out:
}
static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg, u32 bw_cap)
static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg,
u32 bw_cap[])
{
struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
struct ieee80211_channel *band_chan_arr;
@ -5100,7 +5103,6 @@ static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg, u32 bw_cap)
enum ieee80211_band band;
u32 channel;
u32 *n_cnt;
bool ht40_allowed;
u32 index;
u32 ht40_flag;
bool update;
@ -5133,18 +5135,17 @@ static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg, u32 bw_cap)
array_size = ARRAY_SIZE(__wl_2ghz_channels);
n_cnt = &__wl_band_2ghz.n_channels;
band = IEEE80211_BAND_2GHZ;
ht40_allowed = (bw_cap == WLC_N_BW_40ALL);
} else if (ch.band == BRCMU_CHAN_BAND_5G) {
band_chan_arr = __wl_5ghz_a_channels;
array_size = ARRAY_SIZE(__wl_5ghz_a_channels);
n_cnt = &__wl_band_5ghz_a.n_channels;
band = IEEE80211_BAND_5GHZ;
ht40_allowed = !(bw_cap == WLC_N_BW_20ALL);
} else {
brcmf_err("Invalid channel Sepc. 0x%x.\n", ch.chspec);
brcmf_err("Invalid channel Spec. 0x%x.\n", ch.chspec);
continue;
}
if (!ht40_allowed && ch.bw == BRCMU_CHAN_BW_40)
if (!(bw_cap[band] & WLC_BW_40MHZ_BIT) &&
ch.bw == BRCMU_CHAN_BW_40)
continue;
update = false;
for (j = 0; (j < *n_cnt && (*n_cnt < array_size)); j++) {
@ -5162,7 +5163,10 @@ static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg, u32 bw_cap)
ieee80211_channel_to_frequency(ch.chnum, band);
band_chan_arr[index].hw_value = ch.chnum;
if (ch.bw == BRCMU_CHAN_BW_40 && ht40_allowed) {
brcmf_err("channel %d: f=%d bw=%d sb=%d\n",
ch.chnum, band_chan_arr[index].center_freq,
ch.bw, ch.sb);
if (ch.bw == BRCMU_CHAN_BW_40) {
/* assuming the order is HT20, HT40 Upper,
* HT40 lower from chanspecs
*/
@ -5213,6 +5217,46 @@ exit:
return err;
}
static void brcmf_get_bwcap(struct brcmf_if *ifp, u32 bw_cap[])
{
u32 band, mimo_bwcap;
int err;
band = WLC_BAND_2G;
err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
if (!err) {
bw_cap[IEEE80211_BAND_2GHZ] = band;
band = WLC_BAND_5G;
err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
if (!err) {
bw_cap[IEEE80211_BAND_5GHZ] = band;
return;
}
WARN_ON(1);
return;
}
brcmf_dbg(INFO, "fallback to mimo_bw_cap info\n");
mimo_bwcap = 0;
err = brcmf_fil_iovar_int_get(ifp, "mimo_bw_cap", &mimo_bwcap);
if (err)
/* assume 20MHz if firmware does not give a clue */
mimo_bwcap = WLC_N_BW_20ALL;
switch (mimo_bwcap) {
case WLC_N_BW_40ALL:
bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_40MHZ_BIT;
/* fall-thru */
case WLC_N_BW_20IN2G_40IN5G:
bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_40MHZ_BIT;
/* fall-thru */
case WLC_N_BW_20ALL:
bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_20MHZ_BIT;
bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_20MHZ_BIT;
break;
default:
brcmf_err("invalid mimo_bw_cap value\n");
}
}
static s32 brcmf_update_wiphybands(struct brcmf_cfg80211_info *cfg)
{
@ -5221,13 +5265,13 @@ static s32 brcmf_update_wiphybands(struct brcmf_cfg80211_info *cfg)
s32 phy_list;
u32 band_list[3];
u32 nmode;
u32 bw_cap = 0;
u32 bw_cap[2] = { 0, 0 };
s8 phy;
s32 err;
u32 nband;
s32 i;
struct ieee80211_supported_band *bands[IEEE80211_NUM_BANDS];
s32 index;
struct ieee80211_supported_band *bands[2] = { NULL, NULL };
struct ieee80211_supported_band *band;
err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_PHYLIST,
&phy_list, sizeof(phy_list));
@ -5253,11 +5297,10 @@ static s32 brcmf_update_wiphybands(struct brcmf_cfg80211_info *cfg)
if (err) {
brcmf_err("nmode error (%d)\n", err);
} else {
err = brcmf_fil_iovar_int_get(ifp, "mimo_bw_cap", &bw_cap);
if (err)
brcmf_err("mimo_bw_cap error (%d)\n", err);
brcmf_get_bwcap(ifp, bw_cap);
}
brcmf_dbg(INFO, "nmode=%d, mimo_bw_cap=%d\n", nmode, bw_cap);
brcmf_dbg(INFO, "nmode=%d, bw_cap=(%d, %d)\n", nmode,
bw_cap[IEEE80211_BAND_2GHZ], bw_cap[IEEE80211_BAND_5GHZ]);
err = brcmf_construct_reginfo(cfg, bw_cap);
if (err) {
@ -5266,40 +5309,33 @@ static s32 brcmf_update_wiphybands(struct brcmf_cfg80211_info *cfg)
}
nband = band_list[0];
memset(bands, 0, sizeof(bands));
for (i = 1; i <= nband && i < ARRAY_SIZE(band_list); i++) {
index = -1;
band = NULL;
if ((band_list[i] == WLC_BAND_5G) &&
(__wl_band_5ghz_a.n_channels > 0)) {
index = IEEE80211_BAND_5GHZ;
bands[index] = &__wl_band_5ghz_a;
if ((bw_cap == WLC_N_BW_40ALL) ||
(bw_cap == WLC_N_BW_20IN2G_40IN5G))
bands[index]->ht_cap.cap |=
IEEE80211_HT_CAP_SGI_40;
} else if ((band_list[i] == WLC_BAND_2G) &&
(__wl_band_2ghz.n_channels > 0)) {
index = IEEE80211_BAND_2GHZ;
bands[index] = &__wl_band_2ghz;
if (bw_cap == WLC_N_BW_40ALL)
bands[index]->ht_cap.cap |=
IEEE80211_HT_CAP_SGI_40;
}
(__wl_band_5ghz_a.n_channels > 0))
band = &__wl_band_5ghz_a;
else if ((band_list[i] == WLC_BAND_2G) &&
(__wl_band_2ghz.n_channels > 0))
band = &__wl_band_2ghz;
else
continue;
if ((index >= 0) && nmode) {
bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40;
bands[index]->ht_cap.ht_supported = true;
bands[index]->ht_cap.ampdu_factor =
IEEE80211_HT_MAX_AMPDU_64K;
bands[index]->ht_cap.ampdu_density =
IEEE80211_HT_MPDU_DENSITY_16;
/* An HT shall support all EQM rates for one spatial
* stream
*/
bands[index]->ht_cap.mcs.rx_mask[0] = 0xff;
if (bw_cap[band->band] & WLC_BW_40MHZ_BIT) {
band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
}
band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
band->ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40;
band->ht_cap.ht_supported = true;
band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
/* An HT shall support all EQM rates for one spatial
* stream
*/
band->ht_cap.mcs.rx_mask[0] = 0xff;
band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
bands[band->band] = band;
}
wiphy = cfg_to_wiphy(cfg);

5
drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
View File

@ -412,7 +412,6 @@ struct brcmf_cfg80211_info {
struct work_struct escan_timeout_work;
u8 *escan_ioctl_buf;
struct list_head vif_list;
u8 vif_cnt;
struct brcmf_cfg80211_vif_event vif_event;
struct completion vif_disabled;
struct brcmu_d11inf d11inf;
@ -487,8 +486,7 @@ enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp);
struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
enum nl80211_iftype type,
bool pm_block);
void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
struct brcmf_cfg80211_vif *vif);
void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
const u8 *vndr_ie_buf, u32 vndr_ie_len);
@ -507,5 +505,6 @@ s32 brcmf_notify_escan_complete(struct brcmf_cfg80211_info *cfg,
bool fw_abort);
void brcmf_set_mpc(struct brcmf_if *ndev, int mpc);
void brcmf_abort_scanning(struct brcmf_cfg80211_info *cfg);
void brcmf_cfg80211_free_netdev(struct net_device *ndev);
#endif /* _wl_cfg80211_h_ */

1
drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
View File

@ -41,6 +41,7 @@
#define BCM4331_CHIP_ID 0x4331
#define BCM4334_CHIP_ID 0x4334
#define BCM4335_CHIP_ID 0x4335
#define BCM43362_CHIP_ID 43362
#define BCM4339_CHIP_ID 0x4339
#endif /* _BRCM_HW_IDS_H_ */

14
drivers/net/wireless/brcm80211/include/brcmu_wifi.h
View File

@ -82,6 +82,20 @@
#define WLC_N_BW_40ALL 1
#define WLC_N_BW_20IN2G_40IN5G 2
#define WLC_BW_20MHZ_BIT BIT(0)
#define WLC_BW_40MHZ_BIT BIT(1)
#define WLC_BW_80MHZ_BIT BIT(2)
#define WLC_BW_160MHZ_BIT BIT(3)
/* Bandwidth capabilities */
#define WLC_BW_CAP_20MHZ (WLC_BW_20MHZ_BIT)
#define WLC_BW_CAP_40MHZ (WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
#define WLC_BW_CAP_80MHZ (WLC_BW_80MHZ_BIT|WLC_BW_40MHZ_BIT| \
WLC_BW_20MHZ_BIT)
#define WLC_BW_CAP_160MHZ (WLC_BW_160MHZ_BIT|WLC_BW_80MHZ_BIT| \
WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
#define WLC_BW_CAP_UNRESTRICTED 0xFF
/* band types */
#define WLC_BAND_AUTO 0 /* auto-select */
#define WLC_BAND_5G 1 /* 5 Ghz */

1
drivers/net/wireless/cw1200/fwio.c
View File

@ -14,7 +14,6 @@
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/sched.h>
#include <linux/firmware.h>

1
drivers/net/wireless/cw1200/main.c
View File

@ -21,7 +21,6 @@
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/firmware.h>
#include <linux/etherdevice.h>
#include <linux/vmalloc.h>

11
drivers/net/wireless/cw1200/pm.c
View File

@ -225,7 +225,7 @@ int cw1200_wow_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
cw1200_set_pm(priv, &priv->powersave_mode);
if (wait_event_interruptible_timeout(priv->ps_mode_switch_done,
!priv->ps_mode_switch_in_progress, 1*HZ) <= 0) {
goto revert3;
goto revert4;
}
}
@ -254,11 +254,11 @@ int cw1200_wow_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
/* Stop serving thread */
if (cw1200_bh_suspend(priv))
goto revert4;
goto revert5;
ret = timer_pending(&priv->mcast_timeout);
if (ret)
goto revert5;
goto revert6;
/* Store suspend state */
pm_state->suspend_state = state;
@ -280,9 +280,9 @@ int cw1200_wow_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan)
return 0;
revert5:
revert6:
WARN_ON(cw1200_bh_resume(priv));
revert4:
revert5:
cw1200_resume_work(priv, &priv->bss_loss_work,
state->bss_loss_tmo);
cw1200_resume_work(priv, &priv->join_timeout,
@ -291,6 +291,7 @@ revert4:
state->direct_probe);
cw1200_resume_work(priv, &priv->link_id_gc_work,
state->link_id_gc);
revert4:
kfree(state);
revert3:
wsm_set_udp_port_filter(priv, &cw1200_udp_port_filter_off);

1
drivers/net/wireless/hostap/hostap_cs.c
View File

@ -1,7 +1,6 @@
#define PRISM2_PCCARD
#include <linux/module.h>
#include <linux/init.h>
#include <linux/if.h>
#include <linux/slab.h>
#include <linux/wait.h>

2
drivers/net/wireless/hostap/hostap_ioctl.c
View File

@ -2567,7 +2567,7 @@ static int prism2_ioctl_priv_prism2_param(struct net_device *dev,
local->passive_scan_interval = value;
if (timer_pending(&local->passive_scan_timer))
del_timer(&local->passive_scan_timer);
if (value > 0) {
if (value > 0 && value < INT_MAX / HZ) {
local->passive_scan_timer.expires = jiffies +
local->passive_scan_interval * HZ;
add_timer(&local->passive_scan_timer);

1
drivers/net/wireless/hostap/hostap_pci.c
View File

@ -5,7 +5,6 @@
* Andy Warner <andyw@pobox.com> */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/if.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>

1
drivers/net/wireless/hostap/hostap_plx.c
View File

@ -8,7 +8,6 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/if.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>

1
drivers/net/wireless/ipw2x00/ipw2200.h
View File

@ -29,7 +29,6 @@
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>

2
drivers/net/wireless/ipw2x00/libipw_rx.c
View File

@ -1468,7 +1468,7 @@ static inline int is_same_network(struct libipw_network *src,
* as one network */
return ((src->ssid_len == dst->ssid_len) &&
(src->channel == dst->channel) &&
ether_addr_equal(src->bssid, dst->bssid) &&
ether_addr_equal_64bits(src->bssid, dst->bssid) &&
!memcmp(src->ssid, dst->ssid, src->ssid_len));
}

1
drivers/net/wireless/iwlegacy/3945-rs.c
View File

@ -25,7 +25,6 @@
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <net/mac80211.h>

5
drivers/net/wireless/iwlegacy/3945.c
View File

@ -26,7 +26,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
@ -466,10 +465,10 @@ il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
switch (il->iw_mode) {
case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
/* packets to our IBSS update information */
return ether_addr_equal(header->addr3, il->bssid);
return ether_addr_equal_64bits(header->addr3, il->bssid);
case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
/* packets to our IBSS update information */
return ether_addr_equal(header->addr2, il->bssid);
return ether_addr_equal_64bits(header->addr2, il->bssid);
default:
return 1;
}

1
drivers/net/wireless/iwlegacy/4965-rs.c
View File

@ -24,7 +24,6 @@
*
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <net/mac80211.h>

1
drivers/net/wireless/iwlegacy/4965.c
View File

@ -26,7 +26,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>

9
drivers/net/wireless/iwlegacy/common.c
View File

@ -33,7 +33,6 @@
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/lockdep.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
@ -3746,10 +3745,10 @@ il_full_rxon_required(struct il_priv *il)
/* These items are only settable from the full RXON command */
CHK(!il_is_associated(il));
CHK(!ether_addr_equal(staging->bssid_addr, active->bssid_addr));
CHK(!ether_addr_equal(staging->node_addr, active->node_addr));
CHK(!ether_addr_equal(staging->wlap_bssid_addr,
active->wlap_bssid_addr));
CHK(!ether_addr_equal_64bits(staging->bssid_addr, active->bssid_addr));
CHK(!ether_addr_equal_64bits(staging->node_addr, active->node_addr));
CHK(!ether_addr_equal_64bits(staging->wlap_bssid_addr,
active->wlap_bssid_addr));
CHK_NEQ(staging->dev_type, active->dev_type);
CHK_NEQ(staging->channel, active->channel);
CHK_NEQ(staging->air_propagation, active->air_propagation);

4
drivers/net/wireless/iwlwifi/dvm/agn.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
drivers/net/wireless/iwlwifi/dvm/calib.c
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
drivers/net/wireless/iwlwifi/dvm/calib.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

4
drivers/net/wireless/iwlwifi/dvm/commands.h
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
drivers/net/wireless/iwlwifi/dvm/debugfs.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/dvm/dev.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/dvm/devices.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

3
drivers/net/wireless/iwlwifi/dvm/led.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -27,7 +27,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>

2
drivers/net/wireless/iwlwifi/dvm/led.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

3
drivers/net/wireless/iwlwifi/dvm/lib.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -29,7 +29,6 @@
#include <linux/etherdevice.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <net/mac80211.h>

3
drivers/net/wireless/iwlwifi/dvm/mac80211.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -28,7 +28,6 @@
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>

2
drivers/net/wireless/iwlwifi/dvm/main.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

3
drivers/net/wireless/iwlwifi/dvm/power.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -30,7 +30,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <net/mac80211.h>
#include "iwl-io.h"
#include "iwl-debug.h"

2
drivers/net/wireless/iwlwifi/dvm/power.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

3
drivers/net/wireless/iwlwifi/dvm/rs.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@ -24,7 +24,6 @@
*
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <net/mac80211.h>

2
drivers/net/wireless/iwlwifi/dvm/rs.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/dvm/rx.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portionhelp of the ieee80211 subsystem header files.

2
drivers/net/wireless/iwlwifi/dvm/rxon.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/dvm/scan.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/dvm/sta.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

3
drivers/net/wireless/iwlwifi/dvm/tt.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
@ -30,7 +30,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <net/mac80211.h>
#include "iwl-io.h"
#include "iwl-modparams.h"

2
drivers/net/wireless/iwlwifi/dvm/tt.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.

3
drivers/net/wireless/iwlwifi/dvm/tx.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -29,7 +29,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ieee80211.h>
#include "iwl-io.h"

3
drivers/net/wireless/iwlwifi/dvm/ucode.c
View File

@ -2,7 +2,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -28,7 +28,6 @@
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include "iwl-io.h"
#include "iwl-agn-hw.h"

2
drivers/net/wireless/iwlwifi/iwl-1000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-2000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-5000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
drivers/net/wireless/iwlwifi/iwl-6000.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

4
drivers/net/wireless/iwlwifi/iwl-7000.c
View File

@ -5,7 +5,7 @@
*
* GPL LICENSE SUMMARY
*
* Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -30,7 +30,7 @@
*
* BSD LICENSE
*
* Copyright(c) 2012 - 2013 Intel Corporation. All rights reserved.
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

Some files were not shown because too many files have changed in this diff Show More