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cpufreq: qcom-hw: Fix reading "reg" with address/size-cells != 2
Commit054a3ef683
("cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe") assumed that every reg variable is 4*u32 wide (as most new qcom SoCs set #address- and #size-cells to <2>. That is not the case for all of them though. Check the cells values dynamically to ensure the proper region of the DTB is being read. Fixes:054a3ef683
("cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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@ -649,9 +649,10 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device *dev = &pdev->dev;
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struct device_node *soc_node;
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struct device *cpu_dev;
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struct clk *clk;
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int ret, i, num_domains;
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int ret, i, num_domains, reg_sz;
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clk = clk_get(dev, "xo");
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if (IS_ERR(clk))
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@ -679,7 +680,21 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
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return ret;
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/* Allocate qcom_cpufreq_data based on the available frequency domains in DT */
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num_domains = of_property_count_elems_of_size(dev->of_node, "reg", sizeof(u32) * 4);
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soc_node = of_get_parent(dev->of_node);
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if (!soc_node)
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return -EINVAL;
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ret = of_property_read_u32(soc_node, "#address-cells", ®_sz);
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if (ret)
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goto of_exit;
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ret = of_property_read_u32(soc_node, "#size-cells", &i);
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if (ret)
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goto of_exit;
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reg_sz += i;
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num_domains = of_property_count_elems_of_size(dev->of_node, "reg", sizeof(u32) * reg_sz);
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if (num_domains <= 0)
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return num_domains;
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@ -743,6 +758,9 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
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else
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dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n");
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of_exit:
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of_node_put(soc_node);
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return ret;
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}
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