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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
Jeff Kirsher says: ==================== Intel Wired LAN Driver Updates This series contains updates to i40e only. Christopher Pau provides a patch to set pf_id based on device and function numbers since NICs with ARI enabled can have function numbers larger than 8. Anjali provides 3 i40e patches to update hardware defines to keep in sync with hardware updates. Shannon provides the majority of i40e patches, with 7. First patch clears the admin queue head and tail registers during admin queue shutdown. Then simplifies the admin queue head-tail-len setups to use more virtual registers. Provides several patches to cleanup and fix driver load and reset procedures to make more robust. Lastly, provides an ethtool test for interrupts using the software interrupt. Mitch provides some i40e patches which fixes up VF code in the PF driver, specifically the number of vectors per VF are reported by the hardware does not include vector 0, so we need to account for this when checking. In addition, cleans up debugging messages. Kamil provides an i40e patch to fix the diagnostics test by restricting the diagnostic test length. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
19e1190afb
@ -81,11 +81,14 @@
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#define I40E_DEFAULT_MSG_ENABLE 4
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#define I40E_NVM_VERSION_LO_SHIFT 0
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#define I40E_NVM_VERSION_LO_MASK (0xf << I40E_NVM_VERSION_LO_SHIFT)
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#define I40E_NVM_VERSION_MID_SHIFT 4
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#define I40E_NVM_VERSION_MID_MASK (0xff << I40E_NVM_VERSION_MID_SHIFT)
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#define I40E_NVM_VERSION_HI_SHIFT 12
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#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
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#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
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#define I40E_NVM_VERSION_HI_SHIFT 8
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#define I40E_NVM_VERSION_HI_MASK (0xff << I40E_NVM_VERSION_HI_SHIFT)
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/* The values in here are decimal coded as hex as is the case in the NVM map*/
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#define I40E_CURRENT_NVM_VERSION_HI 0x2
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#define I40E_CURRENT_NVM_VERSION_LO 0x1
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/* magic for getting defines into strings */
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#define STRINGIFY(foo) #foo
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@ -127,6 +130,7 @@ enum i40e_state_t {
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__I40E_PF_RESET_REQUESTED,
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__I40E_CORE_RESET_REQUESTED,
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__I40E_GLOBAL_RESET_REQUESTED,
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__I40E_EMP_RESET_REQUESTED,
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__I40E_FILTER_OVERFLOW_PROMISC,
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};
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@ -247,6 +251,7 @@ struct i40e_pf {
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u16 globr_count; /* Global reset count */
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u16 empr_count; /* EMP reset count */
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u16 pfr_count; /* PF reset count */
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u16 sw_int_count; /* SW interrupt count */
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struct mutex switch_mutex;
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u16 lan_vsi; /* our default LAN VSI */
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@ -441,13 +446,11 @@ static inline char *i40e_fw_version_str(struct i40e_hw *hw)
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static char buf[32];
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snprintf(buf, sizeof(buf),
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"f%d.%d a%d.%d n%02d.%02d.%02d e%08x",
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"f%d.%d a%d.%d n%02x.%02x e%08x",
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hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
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hw->aq.api_maj_ver, hw->aq.api_min_ver,
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(hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
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>> I40E_NVM_VERSION_HI_SHIFT,
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(hw->nvm.version & I40E_NVM_VERSION_MID_MASK)
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>> I40E_NVM_VERSION_MID_SHIFT,
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(hw->nvm.version & I40E_NVM_VERSION_LO_MASK)
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>> I40E_NVM_VERSION_LO_SHIFT,
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hw->nvm.eetrack);
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@ -43,13 +43,17 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
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if (hw->mac.type == I40E_MAC_VF) {
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hw->aq.asq.tail = I40E_VF_ATQT1;
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hw->aq.asq.head = I40E_VF_ATQH1;
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hw->aq.asq.len = I40E_VF_ATQLEN1;
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hw->aq.arq.tail = I40E_VF_ARQT1;
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hw->aq.arq.head = I40E_VF_ARQH1;
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hw->aq.arq.len = I40E_VF_ARQLEN1;
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} else {
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hw->aq.asq.tail = I40E_PF_ATQT;
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hw->aq.asq.head = I40E_PF_ATQH;
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hw->aq.asq.len = I40E_PF_ATQLEN;
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hw->aq.arq.tail = I40E_PF_ARQT;
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hw->aq.arq.head = I40E_PF_ARQH;
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hw->aq.arq.len = I40E_PF_ARQLEN;
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}
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}
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@ -466,10 +470,9 @@ static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
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return I40E_ERR_NOT_READY;
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/* Stop firmware AdminQ processing */
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if (hw->mac.type == I40E_MAC_VF)
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wr32(hw, I40E_VF_ATQLEN1, 0);
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else
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wr32(hw, I40E_PF_ATQLEN, 0);
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wr32(hw, hw->aq.asq.head, 0);
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wr32(hw, hw->aq.asq.tail, 0);
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wr32(hw, hw->aq.asq.len, 0);
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/* make sure lock is available */
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mutex_lock(&hw->aq.asq_mutex);
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@ -500,10 +503,9 @@ static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
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return I40E_ERR_NOT_READY;
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/* Stop firmware AdminQ processing */
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if (hw->mac.type == I40E_MAC_VF)
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wr32(hw, I40E_VF_ARQLEN1, 0);
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else
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wr32(hw, I40E_PF_ARQLEN, 0);
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wr32(hw, hw->aq.arq.head, 0);
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wr32(hw, hw->aq.arq.tail, 0);
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wr32(hw, hw->aq.arq.len, 0);
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/* make sure lock is available */
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mutex_lock(&hw->aq.arq_mutex);
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@ -533,8 +535,9 @@ static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
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**/
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i40e_status i40e_init_adminq(struct i40e_hw *hw)
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{
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u16 eetrack_lo, eetrack_hi;
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i40e_status ret_code;
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u16 eetrack_lo, eetrack_hi;
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int retry = 0;
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/* verify input for valid configuration */
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if ((hw->aq.num_arq_entries == 0) ||
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@ -562,11 +565,24 @@ i40e_status i40e_init_adminq(struct i40e_hw *hw)
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if (ret_code)
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goto init_adminq_free_asq;
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ret_code = i40e_aq_get_firmware_version(hw,
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&hw->aq.fw_maj_ver, &hw->aq.fw_min_ver,
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&hw->aq.api_maj_ver, &hw->aq.api_min_ver,
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NULL);
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if (ret_code)
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/* There are some cases where the firmware may not be quite ready
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* for AdminQ operations, so we retry the AdminQ setup a few times
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* if we see timeouts in this first AQ call.
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*/
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do {
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ret_code = i40e_aq_get_firmware_version(hw,
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&hw->aq.fw_maj_ver,
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&hw->aq.fw_min_ver,
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&hw->aq.api_maj_ver,
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&hw->aq.api_min_ver,
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NULL);
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if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
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break;
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retry++;
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msleep(100);
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i40e_resume_aq(hw);
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} while (retry < 10);
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if (ret_code != I40E_SUCCESS)
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goto init_adminq_free_arq;
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if (hw->aq.api_maj_ver != I40E_FW_API_VERSION_MAJOR ||
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@ -956,27 +972,13 @@ void i40e_resume_aq(struct i40e_hw *hw)
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hw->aq.asq.next_to_clean = 0;
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i40e_config_asq_regs(hw);
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reg = hw->aq.num_asq_entries;
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if (hw->mac.type == I40E_MAC_VF) {
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reg |= I40E_VF_ATQLEN_ATQENABLE_MASK;
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wr32(hw, I40E_VF_ATQLEN1, reg);
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} else {
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reg |= I40E_PF_ATQLEN_ATQENABLE_MASK;
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wr32(hw, I40E_PF_ATQLEN, reg);
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}
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reg = hw->aq.num_asq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK;
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wr32(hw, hw->aq.asq.len, reg);
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hw->aq.arq.next_to_use = 0;
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hw->aq.arq.next_to_clean = 0;
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i40e_config_arq_regs(hw);
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reg = hw->aq.num_arq_entries;
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if (hw->mac.type == I40E_MAC_VF) {
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reg |= I40E_VF_ATQLEN_ATQENABLE_MASK;
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wr32(hw, I40E_VF_ARQLEN1, reg);
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} else {
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reg |= I40E_PF_ATQLEN_ATQENABLE_MASK;
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wr32(hw, I40E_PF_ARQLEN, reg);
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}
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reg = hw->aq.num_arq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK;
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wr32(hw, hw->aq.arq.len, reg);
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}
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@ -56,6 +56,7 @@ struct i40e_adminq_ring {
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/* used for queue tracking */
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u32 head;
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u32 tail;
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u32 len;
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};
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/* ASQ transaction details */
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@ -297,7 +297,11 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw)
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}
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/* Determine the PF number based on the PCI fn */
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hw->pf_id = (u8)hw->bus.func;
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reg = rd32(hw, I40E_GLPCI_CAPSUP);
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if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
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hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
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else
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hw->pf_id = (u8)hw->bus.func;
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/* If there was a Global Reset in progress when we got here,
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* we don't need to do the PF Reset
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@ -1472,6 +1472,10 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
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dev_info(&pf->pdev->dev, "forcing GlobR\n");
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i40e_do_reset(pf, (1 << __I40E_GLOBAL_RESET_REQUESTED));
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} else if (strncmp(cmd_buf, "empr", 4) == 0) {
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dev_info(&pf->pdev->dev, "forcing EMPR\n");
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i40e_do_reset(pf, (1 << __I40E_EMP_RESET_REQUESTED));
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} else if (strncmp(cmd_buf, "read", 4) == 0) {
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u32 address;
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u32 value;
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@ -68,16 +68,16 @@ static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
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struct i40e_diag_reg_test_info i40e_reg_list[] = {
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/* offset mask elements stride */
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{I40E_QTX_CTL(0), 0x0000FFBF, 64, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
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{I40E_QTX_CTL(0), 0x0000FFBF, 4, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
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{I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
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{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
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{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
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{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
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{I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0},
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{I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0},
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{I40E_PFINT_LNKLSTN(0), 0x000007FF, 511, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
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{I40E_QINT_TQCTL(0), 0x000000FF, I40E_QINT_TQCTL_MAX_INDEX + 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
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{I40E_QINT_RQCTL(0), 0x000000FF, I40E_QINT_RQCTL_MAX_INDEX + 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
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{I40E_PFINT_LNKLSTN(0), 0x000007FF, 64, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
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{I40E_QINT_TQCTL(0), 0x000000FF, 64, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
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{I40E_QINT_RQCTL(0), 0x000000FF, 64, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
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{I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0},
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{ 0 }
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};
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@ -734,14 +734,20 @@ static int i40e_eeprom_test(struct i40e_pf *pf, u64 *data)
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static int i40e_intr_test(struct i40e_pf *pf, u64 *data)
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{
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*data = -ENOSYS;
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u16 swc_old = pf->sw_int_count;
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wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
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(I40E_PFINT_DYN_CTL0_INTENA_MASK |
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I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
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usleep_range(1000, 2000);
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*data = (swc_old == pf->sw_int_count);
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return *data;
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}
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static int i40e_loopback_test(struct i40e_pf *pf, u64 *data)
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{
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*data = -ENOSYS;
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*data = 0;
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return *data;
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}
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@ -113,8 +113,8 @@ enum i40e_hmc_lan_object_size {
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#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
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#define I40E_HMC_OBJ_SIZE_TXQ 128
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#define I40E_HMC_OBJ_SIZE_RXQ 32
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#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
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#define I40E_HMC_OBJ_SIZE_FCOE_FILT 32
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#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 64
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#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64
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enum i40e_hmc_lan_rsrc_type {
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I40E_HMC_LAN_FULL = 0,
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@ -2752,6 +2752,11 @@ static irqreturn_t i40e_intr(int irq, void *data)
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ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
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|
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/* if interrupt but no bits showing, must be SWINT */
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if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
|
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(icr0 & I40E_PFINT_ICR0_SWINT_MASK))
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pf->sw_int_count++;
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|
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/* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
|
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if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
|
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@ -2790,11 +2795,11 @@ static irqreturn_t i40e_intr(int irq, void *data)
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val = rd32(hw, I40E_GLGEN_RSTAT);
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val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
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>> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
|
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if (val & I40E_RESET_CORER)
|
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if (val == I40E_RESET_CORER)
|
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pf->corer_count++;
|
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else if (val & I40E_RESET_GLOBR)
|
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else if (val == I40E_RESET_GLOBR)
|
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pf->globr_count++;
|
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else if (val & I40E_RESET_EMPR)
|
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else if (val == I40E_RESET_EMPR)
|
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pf->empr_count++;
|
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}
|
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|
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@ -4051,6 +4056,24 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
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wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
|
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i40e_flush(&pf->hw);
|
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|
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} else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
|
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|
||||
/* Request a Firmware Reset
|
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*
|
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* Same as Global reset, plus restarting the
|
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* embedded firmware engine.
|
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*/
|
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/* enable EMP Reset */
|
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val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
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val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
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wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
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|
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/* force the reset */
|
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val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
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val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
|
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wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
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i40e_flush(&pf->hw);
|
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|
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} else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
|
||||
|
||||
/* Request a PF Reset
|
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@ -5579,6 +5602,7 @@ static int i40e_sw_init(struct i40e_pf *pf)
|
||||
|
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pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
|
||||
(NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
|
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pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
|
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if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
|
||||
if (I40E_DEBUG_USER & debug)
|
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pf->hw.debug_mask = debug;
|
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@ -7141,6 +7165,13 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
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|
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err = i40e_init_adminq(hw);
|
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dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
|
||||
if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
|
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>> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
|
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dev_info(&pdev->dev,
|
||||
"warning: NVM version not supported, supported version: %02x.%02x\n",
|
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I40E_CURRENT_NVM_VERSION_HI,
|
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I40E_CURRENT_NVM_VERSION_LO);
|
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}
|
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if (err) {
|
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dev_info(&pdev->dev,
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"init_adminq failed: %d expecting API %02x.%02x\n",
|
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@ -28,6 +28,10 @@
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#ifndef _I40E_REGISTER_H_
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#define _I40E_REGISTER_H_
|
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|
||||
#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */
|
||||
#define I40E_GL_GP_FUSE_MAX_INDEX 28
|
||||
#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0
|
||||
#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK (0xFFFFFFFF << I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
|
||||
#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4
|
||||
#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
|
||||
#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
|
||||
@ -38,6 +42,11 @@
|
||||
#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
|
||||
#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
|
||||
#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
|
||||
#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC
|
||||
#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0
|
||||
#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
|
||||
#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8
|
||||
#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
|
||||
#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8
|
||||
#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
|
||||
#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
|
||||
@ -50,6 +59,10 @@
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE 0x0009C600
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0
|
||||
#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
|
||||
#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880
|
||||
#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
|
||||
#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
|
||||
@ -837,7 +850,7 @@
|
||||
#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
|
||||
#define I40E_GLHMC_PEQ1FLMAX 0x000C2058
|
||||
#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
|
||||
#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK (0x3FFFFF << I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
|
||||
#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
|
||||
#define I40E_GLHMC_PEQ1MAX 0x000C2054
|
||||
#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
|
||||
#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
|
||||
@ -903,7 +916,7 @@
|
||||
#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT)
|
||||
#define I40E_GLHMC_PEXFFLMAX 0x000C204c
|
||||
#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
|
||||
#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK (0x3FFFFF << I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
|
||||
#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK (0x1FFFFFF << I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
|
||||
#define I40E_GLHMC_PEXFMAX 0x000C2048
|
||||
#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
|
||||
#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
|
||||
@ -1636,7 +1649,7 @@
|
||||
#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
|
||||
#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK (0x1 << I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
|
||||
#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4))
|
||||
#define I40E_VSILAN_QTABLE_MAX_INDEX 15
|
||||
#define I40E_VSILAN_QTABLE_MAX_INDEX 7
|
||||
#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
|
||||
#define I40E_VSILAN_QTABLE_QINDEX_0_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
|
||||
#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
|
||||
@ -1773,16 +1786,20 @@
|
||||
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
|
||||
#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM 0x000B6134
|
||||
#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0
|
||||
#define I40E_GL_MNG_FWSM_FW_MODES_MASK (0x3FF << I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10
|
||||
#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 1
|
||||
#define I40E_GL_MNG_FWSM_FW_MODES_MASK (0x7 << I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 6
|
||||
#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK (0x1 << I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11
|
||||
#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK (0xF << I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15
|
||||
#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK (0x1 << I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16
|
||||
#define I40E_GL_MNG_FWSM_RESET_CNT_MASK (0x7 << I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19
|
||||
#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK (0x3F << I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_RSVD_SHIFT 25
|
||||
#define I40E_GL_MNG_FWSM_RSVD_MASK (0x1 << I40E_GL_MNG_FWSM_RSVD_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26
|
||||
#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
|
||||
#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27
|
||||
@ -2380,8 +2397,7 @@
|
||||
#define I40E_PFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
|
||||
#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
|
||||
#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
|
||||
#define I40E_PFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT 17
|
||||
#define I40E_PFPE_IPCONFIG0_USEUPPERIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT)
|
||||
|
||||
#define I40E_PFPE_MRTEIDXMASK 0x00008600
|
||||
#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
|
||||
#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
|
||||
@ -2460,8 +2476,6 @@
|
||||
#define I40E_VFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
|
||||
#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
|
||||
#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
|
||||
#define I40E_VFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT 17
|
||||
#define I40E_VFPE_IPCONFIG0_USEUPPERIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT)
|
||||
#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */
|
||||
#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
|
||||
#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
|
||||
@ -3141,30 +3155,6 @@
|
||||
#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
|
||||
#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
|
||||
#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
|
||||
#define I40E_GLPM_DMACR 0x000881F4
|
||||
#define I40E_GLPM_DMACR_DMACWT_SHIFT 0
|
||||
#define I40E_GLPM_DMACR_DMACWT_MASK (0xFFFF << I40E_GLPM_DMACR_DMACWT_SHIFT)
|
||||
#define I40E_GLPM_DMACR_EXIT_DC_SHIFT 29
|
||||
#define I40E_GLPM_DMACR_EXIT_DC_MASK (0x1 << I40E_GLPM_DMACR_EXIT_DC_SHIFT)
|
||||
#define I40E_GLPM_DMACR_LX_COALESCING_INDICATION_SHIFT 30
|
||||
#define I40E_GLPM_DMACR_LX_COALESCING_INDICATION_MASK (0x1 << I40E_GLPM_DMACR_LX_COALESCING_INDICATION_SHIFT)
|
||||
#define I40E_GLPM_DMACR_DMAC_EN_SHIFT 31
|
||||
#define I40E_GLPM_DMACR_DMAC_EN_MASK (0x1 << I40E_GLPM_DMACR_DMAC_EN_SHIFT)
|
||||
#define I40E_GLPM_LTRC 0x000BE500
|
||||
#define I40E_GLPM_LTRC_SLTRV_SHIFT 0
|
||||
#define I40E_GLPM_LTRC_SLTRV_MASK (0x3FF << I40E_GLPM_LTRC_SLTRV_SHIFT)
|
||||
#define I40E_GLPM_LTRC_SSCALE_SHIFT 10
|
||||
#define I40E_GLPM_LTRC_SSCALE_MASK (0x7 << I40E_GLPM_LTRC_SSCALE_SHIFT)
|
||||
#define I40E_GLPM_LTRC_LTRS_REQUIREMENT_SHIFT 15
|
||||
#define I40E_GLPM_LTRC_LTRS_REQUIREMENT_MASK (0x1 << I40E_GLPM_LTRC_LTRS_REQUIREMENT_SHIFT)
|
||||
#define I40E_GLPM_LTRC_NSLTRV_SHIFT 16
|
||||
#define I40E_GLPM_LTRC_NSLTRV_MASK (0x3FF << I40E_GLPM_LTRC_NSLTRV_SHIFT)
|
||||
#define I40E_GLPM_LTRC_NSSCALE_SHIFT 26
|
||||
#define I40E_GLPM_LTRC_NSSCALE_MASK (0x7 << I40E_GLPM_LTRC_NSSCALE_SHIFT)
|
||||
#define I40E_GLPM_LTRC_LTR_SEND_SHIFT 30
|
||||
#define I40E_GLPM_LTRC_LTR_SEND_MASK (0x1 << I40E_GLPM_LTRC_LTR_SEND_SHIFT)
|
||||
#define I40E_GLPM_LTRC_LTRNS_REQUIREMENT_SHIFT 31
|
||||
#define I40E_GLPM_LTRC_LTRNS_REQUIREMENT_MASK (0x1 << I40E_GLPM_LTRC_LTRNS_REQUIREMENT_SHIFT)
|
||||
#define I40E_PRTPM_EEE_STAT 0x001E4320
|
||||
#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29
|
||||
#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK (0x1 << I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
|
||||
@ -3201,9 +3191,6 @@
|
||||
#define I40E_PRTPM_GC_LCDMP_MASK (0x1 << I40E_PRTPM_GC_LCDMP_SHIFT)
|
||||
#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
|
||||
#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK (0x1 << I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
|
||||
#define I40E_PRTPM_HPTC 0x000AC800
|
||||
#define I40E_PRTPM_HPTC_HIGH_PRI_TC_SHIFT 0
|
||||
#define I40E_PRTPM_HPTC_HIGH_PRI_TC_MASK (0xFF << I40E_PRTPM_HPTC_HIGH_PRI_TC_SHIFT)
|
||||
#define I40E_PRTPM_RLPIC 0x001E43A0
|
||||
#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
|
||||
#define I40E_PRTPM_RLPIC_ERLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
|
||||
@ -3265,8 +3252,8 @@
|
||||
#define I40E_GLQF_CTL_HTOEP_FCOE_MASK (0x1 << I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
|
||||
#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3
|
||||
#define I40E_GLQF_CTL_PCNT_ALLOC_MASK (0x7 << I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
|
||||
#define I40E_GLQF_CTL_DDPLPEN_SHIFT 7
|
||||
#define I40E_GLQF_CTL_DDPLPEN_MASK (0x1 << I40E_GLQF_CTL_DDPLPEN_SHIFT)
|
||||
#define I40E_GLQF_CTL_RSVD_SHIFT 7
|
||||
#define I40E_GLQF_CTL_RSVD_MASK (0x1 << I40E_GLQF_CTL_RSVD_SHIFT)
|
||||
#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8
|
||||
#define I40E_GLQF_CTL_MAXPEBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
|
||||
#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11
|
||||
@ -3416,9 +3403,9 @@
|
||||
#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */
|
||||
#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8
|
||||
#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
|
||||
#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
|
||||
#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 6
|
||||
#define I40E_PRTQF_FLX_PIT_FSIZE_MASK (0xF << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
|
||||
#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK (0x1F << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
|
||||
#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5
|
||||
#define I40E_PRTQF_FLX_PIT_FSIZE_MASK (0x1F << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
|
||||
#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10
|
||||
#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
|
||||
#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4))
|
||||
@ -3504,7 +3491,7 @@
|
||||
#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5
|
||||
#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
|
||||
#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4))
|
||||
#define I40E_VSIQF_TCREGION_MAX_INDEX 7
|
||||
#define I40E_VSIQF_TCREGION_MAX_INDEX 3
|
||||
#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0
|
||||
#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
|
||||
#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9
|
||||
@ -3521,10 +3508,7 @@
|
||||
#define I40E_GL_FCOEDDPC_MAX_INDEX 143
|
||||
#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0
|
||||
#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
|
||||
#define I40E_GL_FCOEDDPEC(_i) (0x00314900 + ((_i) * 8)) /* _i=0...143 */
|
||||
#define I40E_GL_FCOEDDPEC_MAX_INDEX 143
|
||||
#define I40E_GL_FCOEDDPEC_CFOEDDPEC_SHIFT 0
|
||||
#define I40E_GL_FCOEDDPEC_CFOEDDPEC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPEC_CFOEDDPEC_SHIFT)
|
||||
/* _i=0...143 */
|
||||
#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */
|
||||
#define I40E_GL_FCOEDIFEC_MAX_INDEX 143
|
||||
#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0
|
||||
@ -4276,46 +4260,10 @@
|
||||
#define I40E_PFPM_APM 0x000B8080
|
||||
#define I40E_PFPM_APM_APME_SHIFT 0
|
||||
#define I40E_PFPM_APM_APME_MASK (0x1 << I40E_PFPM_APM_APME_SHIFT)
|
||||
#define I40E_PFPM_FHFT_DATA(_i, _j) (0x00060000 + ((_i) * 4096 + (_j) * 128))
|
||||
#define I40E_PFPM_FHFT_DATA_MAX_INDEX 7
|
||||
#define I40E_PFPM_FHFT_DATA_DWORD_SHIFT 0
|
||||
#define I40E_PFPM_FHFT_DATA_DWORD_MASK (0xFFFFFFFF << I40E_PFPM_FHFT_DATA_DWORD_SHIFT)
|
||||
#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */
|
||||
#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7
|
||||
#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
|
||||
#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK (0xFF << I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
|
||||
#define I40E_PFPM_FHFT_MASK(_i, _j) (0x00068000 + ((_i) * 1024 + (_j) * 128))
|
||||
#define I40E_PFPM_FHFT_MASK_MAX_INDEX 7
|
||||
#define I40E_PFPM_FHFT_MASK_MASK_SHIFT 0
|
||||
#define I40E_PFPM_FHFT_MASK_MASK_MASK (0xFFFF << I40E_PFPM_FHFT_MASK_MASK_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC 0x00245A80
|
||||
#define I40E_PFPM_PROXYFC_PPROXYE_SHIFT 0
|
||||
#define I40E_PFPM_PROXYFC_PPROXYE_MASK (0x1 << I40E_PFPM_PROXYFC_PPROXYE_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC_EX_SHIFT 1
|
||||
#define I40E_PFPM_PROXYFC_EX_MASK (0x1 << I40E_PFPM_PROXYFC_EX_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC_ARP_SHIFT 4
|
||||
#define I40E_PFPM_PROXYFC_ARP_MASK (0x1 << I40E_PFPM_PROXYFC_ARP_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC_ARP_DIRECTED_SHIFT 5
|
||||
#define I40E_PFPM_PROXYFC_ARP_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYFC_ARP_DIRECTED_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC_NS_SHIFT 9
|
||||
#define I40E_PFPM_PROXYFC_NS_MASK (0x1 << I40E_PFPM_PROXYFC_NS_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC_NS_DIRECTED_SHIFT 10
|
||||
#define I40E_PFPM_PROXYFC_NS_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYFC_NS_DIRECTED_SHIFT)
|
||||
#define I40E_PFPM_PROXYFC_MLD_SHIFT 12
|
||||
#define I40E_PFPM_PROXYFC_MLD_MASK (0x1 << I40E_PFPM_PROXYFC_MLD_SHIFT)
|
||||
#define I40E_PFPM_PROXYS 0x00245B80
|
||||
#define I40E_PFPM_PROXYS_EX_SHIFT 1
|
||||
#define I40E_PFPM_PROXYS_EX_MASK (0x1 << I40E_PFPM_PROXYS_EX_SHIFT)
|
||||
#define I40E_PFPM_PROXYS_ARP_SHIFT 4
|
||||
#define I40E_PFPM_PROXYS_ARP_MASK (0x1 << I40E_PFPM_PROXYS_ARP_SHIFT)
|
||||
#define I40E_PFPM_PROXYS_ARP_DIRECTED_SHIFT 5
|
||||
#define I40E_PFPM_PROXYS_ARP_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYS_ARP_DIRECTED_SHIFT)
|
||||
#define I40E_PFPM_PROXYS_NS_SHIFT 9
|
||||
#define I40E_PFPM_PROXYS_NS_MASK (0x1 << I40E_PFPM_PROXYS_NS_SHIFT)
|
||||
#define I40E_PFPM_PROXYS_NS_DIRECTED_SHIFT 10
|
||||
#define I40E_PFPM_PROXYS_NS_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYS_NS_DIRECTED_SHIFT)
|
||||
#define I40E_PFPM_PROXYS_MLD_SHIFT 12
|
||||
#define I40E_PFPM_PROXYS_MLD_MASK (0x1 << I40E_PFPM_PROXYS_MLD_SHIFT)
|
||||
#define I40E_PFPM_WUC 0x0006B200
|
||||
#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
|
||||
#define I40E_PFPM_WUC_EN_APM_D0_MASK (0x1 << I40E_PFPM_WUC_EN_APM_D0_SHIFT)
|
||||
@ -4536,21 +4484,21 @@
|
||||
#define I40E_VFMSIX_PBA 0x00002000
|
||||
#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
|
||||
#define I40E_VFMSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA_PENBIT_SHIFT)
|
||||
#define I40E_VFMSIX_TADD(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TADD_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
|
||||
#define I40E_VFMSIX_TMSG(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TMSG_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
|
||||
#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
|
||||
#define I40E_VFMSIX_TUADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TUADD_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
|
||||
#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
|
||||
#define I40E_VFMSIX_TVCTRL(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */
|
||||
#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
|
||||
#define I40E_VFMSIX_TVCTRL_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL_MASK_SHIFT)
|
||||
@ -4610,8 +4558,6 @@
|
||||
#define I40E_VFPE_IPCONFIG01_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
|
||||
#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
|
||||
#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
|
||||
#define I40E_VFPE_IPCONFIG01_USEUPPERIDRANGE_SHIFT 17
|
||||
#define I40E_VFPE_IPCONFIG01_USEUPPERIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEUPPERIDRANGE_SHIFT)
|
||||
#define I40E_VFPE_MRTEIDXMASK1 0x00009000
|
||||
#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
|
||||
#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
|
||||
@ -4684,5 +4630,13 @@
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
|
||||
#define I40E_VFQF_HREGION_REGION_7_MASK (0x7 << I40E_VFQF_HREGION_REGION_7_SHIFT)
|
||||
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS 0x00270110
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT 0
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT)
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT 8
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT)
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT 16
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT)
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT 24
|
||||
#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_MASK (0x7 << I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT)
|
||||
#endif
|
||||
|
||||
@ -852,10 +852,7 @@ struct i40e_filter_program_desc {
|
||||
|
||||
/* Packet Classifier Types for filters */
|
||||
enum i40e_filter_pctype {
|
||||
/* Note: Value 0-25 are reserved for future use */
|
||||
I40E_FILTER_PCTYPE_IPV4_TEREDO_UDP = 26,
|
||||
I40E_FILTER_PCTYPE_IPV6_TEREDO_UDP = 27,
|
||||
I40E_FILTER_PCTYPE_NONF_IPV4_1588_UDP = 28,
|
||||
/* Note: Values 0-28 are reserved for future use */
|
||||
I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
|
||||
I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
|
||||
I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
|
||||
@ -864,8 +861,7 @@ enum i40e_filter_pctype {
|
||||
I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
|
||||
I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
|
||||
I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
|
||||
/* Note: Value 37 is reserved for future use */
|
||||
I40E_FILTER_PCTYPE_NONF_IPV6_1588_UDP = 38,
|
||||
/* Note: Values 37-38 are reserved for future use */
|
||||
I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
|
||||
I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
|
||||
I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
|
||||
@ -877,7 +873,8 @@ enum i40e_filter_pctype {
|
||||
/* Note: Value 47 is reserved for future use */
|
||||
I40E_FILTER_PCTYPE_FCOE_OX = 48,
|
||||
I40E_FILTER_PCTYPE_FCOE_RX = 49,
|
||||
/* Note: Value 50-62 are reserved for future use */
|
||||
I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
|
||||
/* Note: Values 51-62 are reserved for future use */
|
||||
I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
|
||||
};
|
||||
|
||||
|
||||
@ -70,7 +70,7 @@ static inline bool i40e_vc_isvalid_vector_id(struct i40e_vf *vf, u8 vector_id)
|
||||
{
|
||||
struct i40e_pf *pf = vf->pf;
|
||||
|
||||
return vector_id < pf->hw.func_caps.num_msix_vectors_vf;
|
||||
return vector_id <= pf->hw.func_caps.num_msix_vectors_vf;
|
||||
}
|
||||
|
||||
/***********************vf resource mgmt routines*****************/
|
||||
@ -620,13 +620,13 @@ int i40e_reset_vf(struct i40e_vf *vf, bool flr)
|
||||
if (ret)
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Queue control check failed on Tx queue %d of VSI %d VF %d\n",
|
||||
vf->lan_vsi_index, j, vf->vf_id);
|
||||
j, vf->lan_vsi_index, vf->vf_id);
|
||||
ret = i40e_ctrl_vsi_rx_queue(vf, vf->lan_vsi_index, j,
|
||||
I40E_QUEUE_CTRL_FASTDISABLECHECK);
|
||||
if (ret)
|
||||
dev_info(&pf->pdev->dev,
|
||||
"Queue control check failed on Rx queue %d of VSI %d VF %d\n",
|
||||
vf->lan_vsi_index, j, vf->vf_id);
|
||||
j, vf->lan_vsi_index, vf->vf_id);
|
||||
}
|
||||
|
||||
/* clear the irq settings */
|
||||
@ -1603,7 +1603,7 @@ static int i40e_vc_add_mac_addr_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
|
||||
struct i40e_mac_filter *f;
|
||||
|
||||
f = i40e_find_mac(vsi, al->list[i].addr, true, false);
|
||||
if (f) {
|
||||
if (!f) {
|
||||
if (i40e_is_vsi_in_vlan(vsi))
|
||||
f = i40e_put_mac_in_vlan(vsi, al->list[i].addr,
|
||||
true, false);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user