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powerpc/xics: Reduce and comment xics IPI use of memory barriers
A single full sync (mb()) is requrired to order the mmio to the qirr reg with the set or clear of the message word. However, test_and_clear_bit has the effect of smp_mb() and we are not doing any other io from here, so we don't need a mb per bit processed. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -498,26 +498,23 @@ static irqreturn_t xics_ipi_dispatch(int cpu)
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{
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WARN_ON(cpu_is_offline(cpu));
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mb(); /* order mmio clearing qirr */
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while (xics_ipi_message[cpu].value) {
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if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNCTION);
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}
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if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_RESCHEDULE);
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}
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if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
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}
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#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
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if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
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}
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#endif
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