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mtd: rawnand: arasan: Add new Arasan NAND controller
Add the Arasan NAND controller driver. This brings only NAND controller support. The ECC engine being a bit subtle, hardware ECC support will be added in a second time. This work is based on contributions from Naga Sureshkumar Relli. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-8-miquel.raynal@bootlin.com
This commit is contained in:
Miquel Raynal
parent
8201c579ec
commit
197b88fecc
@ -453,6 +453,13 @@ config MTD_NAND_CADENCE
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Enable the driver for NAND flash on platforms using a Cadence NAND
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controller.
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config MTD_NAND_ARASAN
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tristate "Support for Arasan NAND flash controller"
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depends on HAS_IOMEM && HAS_DMA
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help
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Enables the driver for the Arasan NAND flash controller on
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Zynq Ultrascale+ MPSoC.
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comment "Misc"
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config MTD_SM_COMMON
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@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
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obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o
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obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o
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obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o
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obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o
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nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
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nand-objs += nand_onfi.o
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955
drivers/mtd/nand/raw/arasan-nand-controller.c
Normal file
955
drivers/mtd/nand/raw/arasan-nand-controller.c
Normal file
@ -0,0 +1,955 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Arasan NAND Flash Controller Driver
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*
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* Copyright (C) 2014 - 2020 Xilinx, Inc.
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* Author:
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* Miquel Raynal <miquel.raynal@bootlin.com>
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* Original work (fully rewritten):
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* Punnaiah Choudary Kalluri <punnaia@xilinx.com>
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* Naga Sureshkumar Relli <nagasure@xilinx.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define PKT_REG 0x00
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#define PKT_SIZE(x) FIELD_PREP(GENMASK(10, 0), (x))
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#define PKT_STEPS(x) FIELD_PREP(GENMASK(23, 12), (x))
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#define MEM_ADDR1_REG 0x04
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#define MEM_ADDR2_REG 0x08
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#define ADDR2_STRENGTH(x) FIELD_PREP(GENMASK(27, 25), (x))
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#define ADDR2_CS(x) FIELD_PREP(GENMASK(31, 30), (x))
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#define CMD_REG 0x0C
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#define CMD_1(x) FIELD_PREP(GENMASK(7, 0), (x))
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#define CMD_2(x) FIELD_PREP(GENMASK(15, 8), (x))
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#define CMD_PAGE_SIZE(x) FIELD_PREP(GENMASK(25, 23), (x))
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#define CMD_DMA_ENABLE BIT(27)
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#define CMD_NADDRS(x) FIELD_PREP(GENMASK(30, 28), (x))
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#define CMD_ECC_ENABLE BIT(31)
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#define PROG_REG 0x10
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#define PROG_PGRD BIT(0)
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#define PROG_ERASE BIT(2)
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#define PROG_STATUS BIT(3)
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#define PROG_PGPROG BIT(4)
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#define PROG_RDID BIT(6)
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#define PROG_RDPARAM BIT(7)
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#define PROG_RST BIT(8)
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#define PROG_GET_FEATURE BIT(9)
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#define PROG_SET_FEATURE BIT(10)
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#define INTR_STS_EN_REG 0x14
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#define INTR_SIG_EN_REG 0x18
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#define INTR_STS_REG 0x1C
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#define WRITE_READY BIT(0)
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#define READ_READY BIT(1)
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#define XFER_COMPLETE BIT(2)
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#define DMA_BOUNDARY BIT(6)
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#define EVENT_MASK GENMASK(7, 0)
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#define READY_STS_REG 0x20
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#define DMA_ADDR0_REG 0x50
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#define DMA_ADDR1_REG 0x24
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#define FLASH_STS_REG 0x28
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#define DATA_PORT_REG 0x30
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#define ECC_CONF_REG 0x34
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#define ECC_CONF_COL(x) FIELD_PREP(GENMASK(15, 0), (x))
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#define ECC_CONF_LEN(x) FIELD_PREP(GENMASK(26, 16), (x))
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#define ECC_CONF_BCH_EN BIT(27)
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#define ECC_ERR_CNT_REG 0x38
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#define GET_PKT_ERR_CNT(x) FIELD_GET(GENMASK(7, 0), (x))
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#define GET_PAGE_ERR_CNT(x) FIELD_GET(GENMASK(16, 8), (x))
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#define ECC_SP_REG 0x3C
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#define ECC_SP_CMD1(x) FIELD_PREP(GENMASK(7, 0), (x))
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#define ECC_SP_CMD2(x) FIELD_PREP(GENMASK(15, 8), (x))
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#define ECC_SP_ADDRS(x) FIELD_PREP(GENMASK(30, 28), (x))
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#define ECC_1ERR_CNT_REG 0x40
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#define ECC_2ERR_CNT_REG 0x44
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#define DATA_INTERFACE_REG 0x6C
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#define DIFACE_SDR_MODE(x) FIELD_PREP(GENMASK(2, 0), (x))
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#define DIFACE_DDR_MODE(x) FIELD_PREP(GENMASK(5, 3), (X))
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#define DIFACE_SDR 0
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#define DIFACE_NVDDR BIT(9)
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#define ANFC_MAX_CS 2
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#define ANFC_DFLT_TIMEOUT_US 1000000
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#define ANFC_MAX_CHUNK_SIZE SZ_1M
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#define ANFC_MAX_PARAM_SIZE SZ_4K
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#define ANFC_MAX_STEPS SZ_2K
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#define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
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#define ANFC_MAX_ADDR_CYC 5U
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#define ANFC_RSVD_ECC_BYTES 21
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#define ANFC_XLNX_SDR_DFLT_CORE_CLK 100000000
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#define ANFC_XLNX_SDR_HS_CORE_CLK 80000000
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/**
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* struct anfc_op - Defines how to execute an operation
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* @pkt_reg: Packet register
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* @addr1_reg: Memory address 1 register
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* @addr2_reg: Memory address 2 register
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* @cmd_reg: Command register
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* @prog_reg: Program register
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* @steps: Number of "packets" to read/write
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* @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
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* @len: Data transfer length
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* @read: Data transfer direction from the controller point of view
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*/
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struct anfc_op {
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u32 pkt_reg;
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u32 addr1_reg;
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u32 addr2_reg;
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u32 cmd_reg;
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u32 prog_reg;
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int steps;
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unsigned int rdy_timeout_ms;
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unsigned int len;
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bool read;
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u8 *buf;
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};
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/**
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* struct anand - Defines the NAND chip related information
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* @node: Used to store NAND chips into a list
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* @chip: NAND chip information structure
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* @cs: Chip select line
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* @rb: Ready-busy line
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* @page_sz: Register value of the page_sz field to use
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* @clk: Expected clock frequency to use
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* @timings: Data interface timing mode to use
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* @ecc_conf: Hardware ECC configuration value
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* @strength: Register value of the ECC strength
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* @raddr_cycles: Row address cycle information
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* @caddr_cycles: Column address cycle information
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*/
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struct anand {
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struct list_head node;
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struct nand_chip chip;
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unsigned int cs;
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unsigned int rb;
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unsigned int page_sz;
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unsigned long clk;
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u32 timings;
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u32 ecc_conf;
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u32 strength;
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u16 raddr_cycles;
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u16 caddr_cycles;
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};
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/**
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* struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
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* @dev: Pointer to the device structure
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* @base: Remapped register area
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* @controller_clk: Pointer to the system clock
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* @bus_clk: Pointer to the flash clock
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* @controller: Base controller structure
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* @chips: List of all NAND chips attached to the controller
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* @assigned_cs: Bitmask describing already assigned CS lines
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* @cur_clk: Current clock rate
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*/
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struct arasan_nfc {
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struct device *dev;
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void __iomem *base;
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struct clk *controller_clk;
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struct clk *bus_clk;
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struct nand_controller controller;
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struct list_head chips;
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unsigned long assigned_cs;
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unsigned int cur_clk;
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};
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static struct anand *to_anand(struct nand_chip *nand)
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{
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return container_of(nand, struct anand, chip);
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}
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static struct arasan_nfc *to_anfc(struct nand_controller *ctrl)
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{
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return container_of(ctrl, struct arasan_nfc, controller);
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}
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static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)
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{
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u32 val;
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int ret;
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ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
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val & event, 0,
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ANFC_DFLT_TIMEOUT_US);
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if (ret) {
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dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);
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return -ETIMEDOUT;
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}
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writel_relaxed(event, nfc->base + INTR_STS_REG);
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return 0;
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}
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static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,
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unsigned int timeout_ms)
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{
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struct anand *anand = to_anand(chip);
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u32 val;
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int ret;
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/* There is no R/B interrupt, we must poll a register */
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ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
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val & BIT(anand->rb),
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1, timeout_ms * 1000);
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if (ret) {
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dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",
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readl_relaxed(nfc->base + READY_STS_REG));
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
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{
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writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
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writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
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writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
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writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
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writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
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}
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static int anfc_pkt_len_config(unsigned int len, unsigned int *steps,
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unsigned int *pktsize)
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{
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unsigned int nb, sz;
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for (nb = 1; nb < ANFC_MAX_STEPS; nb *= 2) {
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sz = len / nb;
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if (sz <= ANFC_MAX_PKT_SIZE)
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break;
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}
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if (sz * nb != len)
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return -ENOTSUPP;
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if (steps)
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*steps = nb;
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if (pktsize)
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*pktsize = sz;
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return 0;
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}
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/* NAND framework ->exec_op() hooks and related helpers */
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static int anfc_parse_instructions(struct nand_chip *chip,
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const struct nand_subop *subop,
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struct anfc_op *nfc_op)
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{
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struct anand *anand = to_anand(chip);
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const struct nand_op_instr *instr = NULL;
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bool first_cmd = true;
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unsigned int op_id;
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int ret, i;
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memset(nfc_op, 0, sizeof(*nfc_op));
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nfc_op->addr2_reg = ADDR2_CS(anand->cs);
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nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz);
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for (op_id = 0; op_id < subop->ninstrs; op_id++) {
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unsigned int offset, naddrs, pktsize;
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const u8 *addrs;
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u8 *buf;
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instr = &subop->instrs[op_id];
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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if (first_cmd)
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nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode);
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else
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nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode);
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first_cmd = false;
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break;
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case NAND_OP_ADDR_INSTR:
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offset = nand_subop_get_addr_start_off(subop, op_id);
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naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
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addrs = &instr->ctx.addr.addrs[offset];
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nfc_op->cmd_reg |= CMD_NADDRS(naddrs);
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for (i = 0; i < min(ANFC_MAX_ADDR_CYC, naddrs); i++) {
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if (i < 4)
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nfc_op->addr1_reg |= (u32)addrs[i] << i * 8;
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else
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nfc_op->addr2_reg |= addrs[i];
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}
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break;
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case NAND_OP_DATA_IN_INSTR:
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nfc_op->read = true;
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fallthrough;
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case NAND_OP_DATA_OUT_INSTR:
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offset = nand_subop_get_data_start_off(subop, op_id);
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buf = instr->ctx.data.buf.in;
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nfc_op->buf = &buf[offset];
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nfc_op->len = nand_subop_get_data_len(subop, op_id);
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ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps,
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&pktsize);
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if (ret)
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return ret;
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/*
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* Number of DATA cycles must be aligned on 4, this
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* means the controller might read/write more than
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* requested. This is harmless most of the time as extra
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* DATA are discarded in the write path and read pointer
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* adjusted in the read path.
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*
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* FIXME: The core should mark operations where
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* reading/writing more is allowed so the exec_op()
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* implementation can take the right decision when the
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* alignment constraint is not met: adjust the number of
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* DATA cycles when it's allowed, reject the operation
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* otherwise.
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*/
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nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) |
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PKT_STEPS(nfc_op->steps);
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break;
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case NAND_OP_WAITRDY_INSTR:
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nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
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break;
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}
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}
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return 0;
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}
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static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
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{
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unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;
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unsigned int last_len = nfc_op->len % 4;
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unsigned int offset, dir;
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u8 *buf = nfc_op->buf;
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int ret, i;
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for (i = 0; i < nfc_op->steps; i++) {
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dir = nfc_op->read ? READ_READY : WRITE_READY;
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ret = anfc_wait_for_event(nfc, dir);
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if (ret) {
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dev_err(nfc->dev, "PIO %s ready signal not received\n",
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nfc_op->read ? "Read" : "Write");
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return ret;
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}
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offset = i * (dwords * 4);
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if (nfc_op->read)
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ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
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dwords);
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else
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iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
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dwords);
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}
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if (last_len) {
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u32 remainder;
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offset = nfc_op->len - last_len;
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if (nfc_op->read) {
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remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
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memcpy(&buf[offset], &remainder, last_len);
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} else {
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memcpy(&remainder, &buf[offset], last_len);
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writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
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}
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}
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return anfc_wait_for_event(nfc, XFER_COMPLETE);
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}
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static int anfc_misc_data_type_exec(struct nand_chip *chip,
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const struct nand_subop *subop,
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u32 prog_reg)
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{
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struct arasan_nfc *nfc = to_anfc(chip->controller);
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struct anfc_op nfc_op = {};
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int ret;
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ret = anfc_parse_instructions(chip, subop, &nfc_op);
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if (ret)
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return ret;
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nfc_op.prog_reg = prog_reg;
|
||||
anfc_trigger_op(nfc, &nfc_op);
|
||||
|
||||
if (nfc_op.rdy_timeout_ms) {
|
||||
ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return anfc_rw_pio_op(nfc, &nfc_op);
|
||||
}
|
||||
|
||||
static int anfc_param_read_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
return anfc_misc_data_type_exec(chip, subop, PROG_RDPARAM);
|
||||
}
|
||||
|
||||
static int anfc_data_read_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
return anfc_misc_data_type_exec(chip, subop, PROG_PGRD);
|
||||
}
|
||||
|
||||
static int anfc_param_write_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
return anfc_misc_data_type_exec(chip, subop, PROG_SET_FEATURE);
|
||||
}
|
||||
|
||||
static int anfc_data_write_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
return anfc_misc_data_type_exec(chip, subop, PROG_PGPROG);
|
||||
}
|
||||
|
||||
static int anfc_misc_zerolen_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop,
|
||||
u32 prog_reg)
|
||||
{
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
struct anfc_op nfc_op = {};
|
||||
int ret;
|
||||
|
||||
ret = anfc_parse_instructions(chip, subop, &nfc_op);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nfc_op.prog_reg = prog_reg;
|
||||
anfc_trigger_op(nfc, &nfc_op);
|
||||
|
||||
ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (nfc_op.rdy_timeout_ms)
|
||||
ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int anfc_status_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
u32 tmp;
|
||||
int ret;
|
||||
|
||||
/* See anfc_check_op() for details about this constraint */
|
||||
if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS)
|
||||
return -ENOTSUPP;
|
||||
|
||||
ret = anfc_misc_zerolen_type_exec(chip, subop, PROG_STATUS);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
|
||||
memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anfc_reset_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
return anfc_misc_zerolen_type_exec(chip, subop, PROG_RST);
|
||||
}
|
||||
|
||||
static int anfc_erase_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
return anfc_misc_zerolen_type_exec(chip, subop, PROG_ERASE);
|
||||
}
|
||||
|
||||
static int anfc_wait_type_exec(struct nand_chip *chip,
|
||||
const struct nand_subop *subop)
|
||||
{
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
struct anfc_op nfc_op = {};
|
||||
int ret;
|
||||
|
||||
ret = anfc_parse_instructions(chip, subop, &nfc_op);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
|
||||
}
|
||||
|
||||
static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER(
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_param_read_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
|
||||
NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_param_write_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
|
||||
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_PARAM_SIZE)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_data_read_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
|
||||
NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, ANFC_MAX_CHUNK_SIZE)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_data_write_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
|
||||
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_CHUNK_SIZE),
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_reset_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_erase_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_status_type_exec,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),
|
||||
NAND_OP_PARSER_PATTERN(
|
||||
anfc_wait_type_exec,
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
|
||||
);
|
||||
|
||||
static int anfc_select_target(struct nand_chip *chip, int target)
|
||||
{
|
||||
struct anand *anand = to_anand(chip);
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
int ret;
|
||||
|
||||
/* Update the controller timings and the potential ECC configuration */
|
||||
writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG);
|
||||
|
||||
/* Update clock frequency */
|
||||
if (nfc->cur_clk != anand->clk) {
|
||||
clk_disable_unprepare(nfc->controller_clk);
|
||||
ret = clk_set_rate(nfc->controller_clk, anand->clk);
|
||||
if (ret) {
|
||||
dev_err(nfc->dev, "Failed to change clock rate\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(nfc->controller_clk);
|
||||
if (ret) {
|
||||
dev_err(nfc->dev,
|
||||
"Failed to re-enable the controller clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
nfc->cur_clk = anand->clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anfc_check_op(struct nand_chip *chip,
|
||||
const struct nand_operation *op)
|
||||
{
|
||||
const struct nand_op_instr *instr;
|
||||
int op_id;
|
||||
|
||||
/*
|
||||
* The controller abstracts all the NAND operations and do not support
|
||||
* data only operations.
|
||||
*
|
||||
* TODO: The nand_op_parser framework should be extended to
|
||||
* support custom checks on DATA instructions.
|
||||
*/
|
||||
for (op_id = 0; op_id < op->ninstrs; op_id++) {
|
||||
instr = &op->instrs[op_id];
|
||||
|
||||
switch (instr->type) {
|
||||
case NAND_OP_ADDR_INSTR:
|
||||
if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC)
|
||||
return -ENOTSUPP;
|
||||
|
||||
break;
|
||||
case NAND_OP_DATA_IN_INSTR:
|
||||
case NAND_OP_DATA_OUT_INSTR:
|
||||
if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE)
|
||||
return -ENOTSUPP;
|
||||
|
||||
if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0))
|
||||
return -ENOTSUPP;
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The controller does not allow to proceed with a CMD+DATA_IN cycle
|
||||
* manually on the bus by reading data from the data register. Instead,
|
||||
* the controller abstract a status read operation with its own status
|
||||
* register after ordering a read status operation. Hence, we cannot
|
||||
* support any CMD+DATA_IN operation other than a READ STATUS.
|
||||
*
|
||||
* TODO: The nand_op_parser() framework should be extended to describe
|
||||
* fixed patterns instead of open-coding this check here.
|
||||
*/
|
||||
if (op->ninstrs == 2 &&
|
||||
op->instrs[0].type == NAND_OP_CMD_INSTR &&
|
||||
op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS &&
|
||||
op->instrs[1].type == NAND_OP_DATA_IN_INSTR)
|
||||
return -ENOTSUPP;
|
||||
|
||||
return nand_op_parser_exec_op(chip, &anfc_op_parser, op, true);
|
||||
}
|
||||
|
||||
static int anfc_exec_op(struct nand_chip *chip,
|
||||
const struct nand_operation *op,
|
||||
bool check_only)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (check_only)
|
||||
return anfc_check_op(chip, op);
|
||||
|
||||
ret = anfc_select_target(chip, op->cs);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);
|
||||
}
|
||||
|
||||
static int anfc_setup_data_interface(struct nand_chip *chip, int target,
|
||||
const struct nand_data_interface *conf)
|
||||
{
|
||||
struct anand *anand = to_anand(chip);
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
struct device_node *np = nfc->dev->of_node;
|
||||
|
||||
if (target < 0)
|
||||
return 0;
|
||||
|
||||
anand->timings = DIFACE_SDR | DIFACE_SDR_MODE(conf->timings.mode);
|
||||
anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
|
||||
|
||||
/*
|
||||
* Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
|
||||
* with f > 90MHz (default clock is 100MHz) but signals are unstable
|
||||
* with higher modes. Hence we decrease a little bit the clock rate to
|
||||
* 80MHz when using modes 2-5 with this SoC.
|
||||
*/
|
||||
if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
|
||||
conf->timings.mode >= 2)
|
||||
anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int anfc_attach_chip(struct nand_chip *chip)
|
||||
{
|
||||
struct anand *anand = to_anand(chip);
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
int ret = 0;
|
||||
|
||||
if (mtd->writesize <= SZ_512)
|
||||
anand->caddr_cycles = 1;
|
||||
else
|
||||
anand->caddr_cycles = 2;
|
||||
|
||||
if (chip->options & NAND_ROW_ADDR_3)
|
||||
anand->raddr_cycles = 3;
|
||||
else
|
||||
anand->raddr_cycles = 2;
|
||||
|
||||
switch (mtd->writesize) {
|
||||
case 512:
|
||||
anand->page_sz = 0;
|
||||
break;
|
||||
case 1024:
|
||||
anand->page_sz = 5;
|
||||
break;
|
||||
case 2048:
|
||||
anand->page_sz = 1;
|
||||
break;
|
||||
case 4096:
|
||||
anand->page_sz = 2;
|
||||
break;
|
||||
case 8192:
|
||||
anand->page_sz = 3;
|
||||
break;
|
||||
case 16384:
|
||||
anand->page_sz = 4;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* These hooks are valid for all ECC providers */
|
||||
chip->ecc.read_page_raw = nand_monolithic_read_page_raw;
|
||||
chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
|
||||
|
||||
switch (chip->ecc.mode) {
|
||||
case NAND_ECC_NONE:
|
||||
case NAND_ECC_SOFT:
|
||||
case NAND_ECC_ON_DIE:
|
||||
break;
|
||||
case NAND_ECC_HW:
|
||||
default:
|
||||
dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
|
||||
chip->ecc.mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct nand_controller_ops anfc_ops = {
|
||||
.exec_op = anfc_exec_op,
|
||||
.setup_data_interface = anfc_setup_data_interface,
|
||||
.attach_chip = anfc_attach_chip,
|
||||
};
|
||||
|
||||
static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)
|
||||
{
|
||||
struct anand *anand;
|
||||
struct nand_chip *chip;
|
||||
struct mtd_info *mtd;
|
||||
int cs, rb, ret;
|
||||
|
||||
anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);
|
||||
if (!anand)
|
||||
return -ENOMEM;
|
||||
|
||||
/* We do not support multiple CS per chip yet */
|
||||
if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) != 1) {
|
||||
dev_err(nfc->dev, "Invalid reg property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(np, "reg", &cs);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_property_read_u32(np, "nand-rb", &rb);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (cs >= ANFC_MAX_CS || rb >= ANFC_MAX_CS) {
|
||||
dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (test_and_set_bit(cs, &nfc->assigned_cs)) {
|
||||
dev_err(nfc->dev, "Already assigned CS %d\n", cs);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
anand->cs = cs;
|
||||
anand->rb = rb;
|
||||
|
||||
chip = &anand->chip;
|
||||
mtd = nand_to_mtd(chip);
|
||||
mtd->dev.parent = nfc->dev;
|
||||
chip->controller = &nfc->controller;
|
||||
chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
|
||||
NAND_USES_DMA;
|
||||
|
||||
nand_set_flash_node(chip, np);
|
||||
if (!mtd->name) {
|
||||
dev_err(nfc->dev, "NAND label property is mandatory\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = nand_scan(chip, 1);
|
||||
if (ret) {
|
||||
dev_err(nfc->dev, "Scan operation failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mtd_device_register(mtd, NULL, 0);
|
||||
if (ret) {
|
||||
nand_cleanup(chip);
|
||||
return ret;
|
||||
}
|
||||
|
||||
list_add_tail(&anand->node, &nfc->chips);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void anfc_chips_cleanup(struct arasan_nfc *nfc)
|
||||
{
|
||||
struct anand *anand, *tmp;
|
||||
struct nand_chip *chip;
|
||||
int ret;
|
||||
|
||||
list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {
|
||||
chip = &anand->chip;
|
||||
ret = mtd_device_unregister(nand_to_mtd(chip));
|
||||
WARN_ON(ret);
|
||||
nand_cleanup(chip);
|
||||
list_del(&anand->node);
|
||||
}
|
||||
}
|
||||
|
||||
static int anfc_chips_init(struct arasan_nfc *nfc)
|
||||
{
|
||||
struct device_node *np = nfc->dev->of_node, *nand_np;
|
||||
int nchips = of_get_child_count(np);
|
||||
int ret;
|
||||
|
||||
if (!nchips || nchips > ANFC_MAX_CS) {
|
||||
dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
|
||||
nchips);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for_each_child_of_node(np, nand_np) {
|
||||
ret = anfc_chip_init(nfc, nand_np);
|
||||
if (ret) {
|
||||
of_node_put(nand_np);
|
||||
anfc_chips_cleanup(nfc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void anfc_reset(struct arasan_nfc *nfc)
|
||||
{
|
||||
/* Disable interrupt signals */
|
||||
writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
|
||||
|
||||
/* Enable interrupt status */
|
||||
writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
|
||||
}
|
||||
|
||||
static int anfc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct arasan_nfc *nfc;
|
||||
int ret;
|
||||
|
||||
nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
|
||||
if (!nfc)
|
||||
return -ENOMEM;
|
||||
|
||||
nfc->dev = &pdev->dev;
|
||||
nand_controller_init(&nfc->controller);
|
||||
nfc->controller.ops = &anfc_ops;
|
||||
INIT_LIST_HEAD(&nfc->chips);
|
||||
|
||||
nfc->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(nfc->base))
|
||||
return PTR_ERR(nfc->base);
|
||||
|
||||
anfc_reset(nfc);
|
||||
|
||||
nfc->controller_clk = devm_clk_get(&pdev->dev, "controller");
|
||||
if (IS_ERR(nfc->controller_clk))
|
||||
return PTR_ERR(nfc->controller_clk);
|
||||
|
||||
nfc->bus_clk = devm_clk_get(&pdev->dev, "bus");
|
||||
if (IS_ERR(nfc->bus_clk))
|
||||
return PTR_ERR(nfc->bus_clk);
|
||||
|
||||
ret = clk_prepare_enable(nfc->controller_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(nfc->bus_clk);
|
||||
if (ret)
|
||||
goto disable_controller_clk;
|
||||
|
||||
ret = anfc_chips_init(nfc);
|
||||
if (ret)
|
||||
goto disable_bus_clk;
|
||||
|
||||
platform_set_drvdata(pdev, nfc);
|
||||
|
||||
return 0;
|
||||
|
||||
disable_bus_clk:
|
||||
clk_disable_unprepare(nfc->bus_clk);
|
||||
|
||||
disable_controller_clk:
|
||||
clk_disable_unprepare(nfc->controller_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int anfc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct arasan_nfc *nfc = platform_get_drvdata(pdev);
|
||||
|
||||
anfc_chips_cleanup(nfc);
|
||||
|
||||
clk_disable_unprepare(nfc->bus_clk);
|
||||
clk_disable_unprepare(nfc->controller_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id anfc_ids[] = {
|
||||
{
|
||||
.compatible = "xlnx,zynqmp-nand-controller",
|
||||
},
|
||||
{
|
||||
.compatible = "arasan,nfc-v3p10",
|
||||
},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, anfc_ids);
|
||||
|
||||
static struct platform_driver anfc_driver = {
|
||||
.driver = {
|
||||
.name = "arasan-nand-controller",
|
||||
.of_match_table = anfc_ids,
|
||||
},
|
||||
.probe = anfc_probe,
|
||||
.remove = anfc_remove,
|
||||
};
|
||||
module_platform_driver(anfc_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>");
|
||||
MODULE_AUTHOR("Naga Sureshkumar Relli <nagasure@xilinx.com>");
|
||||
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
|
||||
MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");
|
||||
Loading…
Reference in New Issue
Block a user