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tty: serial: ucc_uart: replace qe_io{read,write}* wrappers by generic io{read,write}*
Commit6ac9b61786("soc: fsl: qe: introduce qe_io{read,write}* wrappers") added specific I/O accessors for qe because at that time ioread/iowrite functions were sub-optimal on powerpc/32 compared to the architecture specific in_/out_ IO accessors. But as ioread/iowrite accessors are now equivalent since commit894fa235eb("powerpc: inline iomap accessors"), use them in order to allow removal of the qe specific ones. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Li Yang <leoyang.li@nxp.com>
This commit is contained in:
Christophe Leroy
Li Yang
parent
3f39f38ea9
commit
18f0211c9a
@ -261,11 +261,11 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)
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struct qe_bd *bdp = qe_port->tx_bd_base;
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while (1) {
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if (qe_ioread16be(&bdp->status) & BD_SC_READY)
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if (ioread16be(&bdp->status) & BD_SC_READY)
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/* This BD is not done, so return "not done" */
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return 0;
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if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
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if (ioread16be(&bdp->status) & BD_SC_WRAP)
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/*
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* This BD is done and it's the last one, so return
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* "done"
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@ -344,10 +344,10 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
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p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
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*p++ = port->x_char;
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qe_iowrite16be(1, &bdp->length);
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iowrite16be(1, &bdp->length);
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qe_setbits_be16(&bdp->status, BD_SC_READY);
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/* Get next BD. */
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if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
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if (ioread16be(&bdp->status) & BD_SC_WRAP)
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bdp = qe_port->tx_bd_base;
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else
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bdp++;
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@ -366,7 +366,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
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/* Pick next descriptor and fill from buffer */
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bdp = qe_port->tx_cur;
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while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
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while (!(ioread16be(&bdp->status) & BD_SC_READY) &&
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(xmit->tail != xmit->head)) {
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count = 0;
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p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
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@ -379,11 +379,11 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
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break;
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}
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qe_iowrite16be(count, &bdp->length);
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iowrite16be(count, &bdp->length);
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qe_setbits_be16(&bdp->status, BD_SC_READY);
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/* Get next BD. */
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if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
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if (ioread16be(&bdp->status) & BD_SC_WRAP)
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bdp = qe_port->tx_bd_base;
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else
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bdp++;
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@ -416,7 +416,7 @@ static void qe_uart_start_tx(struct uart_port *port)
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container_of(port, struct uart_qe_port, port);
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/* If we currently are transmitting, then just return */
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if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
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if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
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return;
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/* Otherwise, pump the port and start transmission */
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@ -471,14 +471,14 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
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*/
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bdp = qe_port->rx_cur;
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while (1) {
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status = qe_ioread16be(&bdp->status);
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status = ioread16be(&bdp->status);
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/* If this one is empty, then we assume we've read them all */
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if (status & BD_SC_EMPTY)
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break;
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/* get number of characters, and check space in RX buffer */
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i = qe_ioread16be(&bdp->length);
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i = ioread16be(&bdp->length);
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/* If we don't have enough room in RX buffer for the entire BD,
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* then we try later, which will be the next RX interrupt.
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@ -512,7 +512,7 @@ error_return:
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qe_clrsetbits_be16(&bdp->status,
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BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
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BD_SC_EMPTY);
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if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
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if (ioread16be(&bdp->status) & BD_SC_WRAP)
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bdp = qe_port->rx_bd_base;
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else
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bdp++;
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@ -569,8 +569,8 @@ static irqreturn_t qe_uart_int(int irq, void *data)
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u16 events;
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/* Clear the interrupts */
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events = qe_ioread16be(&uccp->ucce);
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qe_iowrite16be(events, &uccp->ucce);
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events = ioread16be(&uccp->ucce);
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iowrite16be(events, &uccp->ucce);
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if (events & UCC_UART_UCCE_BRKE)
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uart_handle_break(&qe_port->port);
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@ -601,17 +601,17 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
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bdp = qe_port->rx_bd_base;
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qe_port->rx_cur = qe_port->rx_bd_base;
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for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
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qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
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qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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qe_iowrite16be(0, &bdp->length);
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iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
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iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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iowrite16be(0, &bdp->length);
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bd_virt += qe_port->rx_fifosize;
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bdp++;
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}
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/* */
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qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
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qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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qe_iowrite16be(0, &bdp->length);
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iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
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iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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iowrite16be(0, &bdp->length);
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/* Set the physical address of the host memory
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* buffers in the buffer descriptors, and the
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@ -622,9 +622,9 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
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qe_port->tx_cur = qe_port->tx_bd_base;
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bdp = qe_port->tx_bd_base;
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for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
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qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
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qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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qe_iowrite16be(0, &bdp->length);
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iowrite16be(BD_SC_INTRPT, &bdp->status);
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iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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iowrite16be(0, &bdp->length);
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bd_virt += qe_port->tx_fifosize;
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bdp++;
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}
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@ -634,9 +634,9 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
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qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
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#endif
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qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
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qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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qe_iowrite16be(0, &bdp->length);
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iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
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iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
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iowrite16be(0, &bdp->length);
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}
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/*
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@ -658,21 +658,21 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
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ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
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/* Program the UCC UART parameter RAM */
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qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
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qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
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qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
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qe_iowrite16be(0x10, &uccup->maxidl);
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qe_iowrite16be(1, &uccup->brkcr);
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qe_iowrite16be(0, &uccup->parec);
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qe_iowrite16be(0, &uccup->frmec);
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qe_iowrite16be(0, &uccup->nosec);
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qe_iowrite16be(0, &uccup->brkec);
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qe_iowrite16be(0, &uccup->uaddr[0]);
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qe_iowrite16be(0, &uccup->uaddr[1]);
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qe_iowrite16be(0, &uccup->toseq);
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iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
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iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
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iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
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iowrite16be(0x10, &uccup->maxidl);
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iowrite16be(1, &uccup->brkcr);
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iowrite16be(0, &uccup->parec);
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iowrite16be(0, &uccup->frmec);
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iowrite16be(0, &uccup->nosec);
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iowrite16be(0, &uccup->brkec);
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iowrite16be(0, &uccup->uaddr[0]);
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iowrite16be(0, &uccup->uaddr[1]);
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iowrite16be(0, &uccup->toseq);
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for (i = 0; i < 8; i++)
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qe_iowrite16be(0xC000, &uccup->cchars[i]);
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qe_iowrite16be(0xc0ff, &uccup->rccm);
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iowrite16be(0xC000, &uccup->cchars[i]);
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iowrite16be(0xc0ff, &uccup->rccm);
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/* Configure the GUMR registers for UART */
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if (soft_uart) {
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@ -702,30 +702,30 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
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#endif
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/* Disable rx interrupts and clear all pending events. */
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qe_iowrite16be(0, &uccp->uccm);
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qe_iowrite16be(0xffff, &uccp->ucce);
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qe_iowrite16be(0x7e7e, &uccp->udsr);
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iowrite16be(0, &uccp->uccm);
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iowrite16be(0xffff, &uccp->ucce);
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iowrite16be(0x7e7e, &uccp->udsr);
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/* Initialize UPSMR */
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qe_iowrite16be(0, &uccp->upsmr);
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iowrite16be(0, &uccp->upsmr);
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if (soft_uart) {
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qe_iowrite16be(0x30, &uccup->supsmr);
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qe_iowrite16be(0, &uccup->res92);
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qe_iowrite32be(0, &uccup->rx_state);
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qe_iowrite32be(0, &uccup->rx_cnt);
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qe_iowrite8(0, &uccup->rx_bitmark);
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qe_iowrite8(10, &uccup->rx_length);
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qe_iowrite32be(0x4000, &uccup->dump_ptr);
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qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
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qe_iowrite32be(0, &uccup->rx_frame_rem);
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qe_iowrite8(0, &uccup->rx_frame_rem_size);
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iowrite16be(0x30, &uccup->supsmr);
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iowrite16be(0, &uccup->res92);
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iowrite32be(0, &uccup->rx_state);
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iowrite32be(0, &uccup->rx_cnt);
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iowrite8(0, &uccup->rx_bitmark);
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iowrite8(10, &uccup->rx_length);
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iowrite32be(0x4000, &uccup->dump_ptr);
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iowrite8(0, &uccup->rx_temp_dlst_qe);
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iowrite32be(0, &uccup->rx_frame_rem);
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iowrite8(0, &uccup->rx_frame_rem_size);
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/* Soft-UART requires TX to be 1X */
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qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
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iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
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&uccup->tx_mode);
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qe_iowrite16be(0, &uccup->tx_state);
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qe_iowrite8(0, &uccup->resD4);
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qe_iowrite16be(0, &uccup->resD5);
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iowrite16be(0, &uccup->tx_state);
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iowrite8(0, &uccup->resD4);
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iowrite16be(0, &uccup->resD5);
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/* Set UART mode.
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* Enable receive and transmit.
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@ -850,9 +850,9 @@ static void qe_uart_set_termios(struct uart_port *port,
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struct ucc_slow __iomem *uccp = qe_port->uccp;
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unsigned int baud;
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unsigned long flags;
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u16 upsmr = qe_ioread16be(&uccp->upsmr);
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u16 upsmr = ioread16be(&uccp->upsmr);
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struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
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u16 supsmr = qe_ioread16be(&uccup->supsmr);
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u16 supsmr = ioread16be(&uccup->supsmr);
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u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
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/* Character length programmed into the mode register is the
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@ -950,10 +950,10 @@ static void qe_uart_set_termios(struct uart_port *port,
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/* Update the per-port timeout. */
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uart_update_timeout(port, termios->c_cflag, baud);
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qe_iowrite16be(upsmr, &uccp->upsmr);
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iowrite16be(upsmr, &uccp->upsmr);
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if (soft_uart) {
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qe_iowrite16be(supsmr, &uccup->supsmr);
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qe_iowrite8(char_length, &uccup->rx_length);
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iowrite16be(supsmr, &uccup->supsmr);
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iowrite8(char_length, &uccup->rx_length);
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/* Soft-UART requires a 1X multiplier for TX */
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qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
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