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[ARM] 3294/1: don't invalidate individual BTB entries on ARMv6

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Patch from Nicolas Pitre

Doing so adds a much larger cost to the loop than the cost implied by
simply invalidating the whole BTB at once.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Pitre 2006-02-01 19:26:01 +00:00 committed by Russell King
parent 8a052e0bc2
commit 18afea04f1
1 changed files with 6 additions and 12 deletions
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18
arch/arm/mm/cache-v6.S
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@ -92,22 +92,16 @@ ENTRY(v6_coherent_kern_range)
* - the Icache does not read data from the write buffer
*/
ENTRY(v6_coherent_user_range)
bic r0, r0, #CACHE_LINE_SIZE - 1
1:
#ifdef HARVARD_CACHE
mcr p15, 0, r0, c7, c10, 1 @ clean D line
bic r0, r0, #CACHE_LINE_SIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
#endif
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
add r0, r0, #CACHE_LINE_SIZE
cmp r0, r1
blo 1b
#endif
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
#ifdef HARVARD_CACHE
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer