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powerpc/perf: power9 raw event format encoding
Patch to update the power9 raw event encoding format information and add support for the same in power9-pmu.c. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Madhavan Srinivasan
Michael Ellerman
parent
520ed5b04f
commit
18201b2042
@ -15,6 +15,78 @@
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#include "isa207-common.h"
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/*
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* Raw event encoding for Power9:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
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* | | | | |
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* | | *- IFM (Linux) | thresh start/stop OR FAB match -*
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* | *- BHRB (Linux) *sm
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* *- EBB (Linux)
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ]
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* | | | | |
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* | | | | *- mark
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* | | *- L1/L2/L3 cache_sel |
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* | | |
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* | *- sampling mode for marked events *- combine
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* |
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* *- thresh_sel
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*
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* Below uses IBM bit numbering.
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*
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* MMCR1[x:y] = unit (PMCxUNIT)
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* MMCR1[24] = pmc1combine[0]
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* MMCR1[25] = pmc1combine[1]
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* MMCR1[26] = pmc2combine[0]
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* MMCR1[27] = pmc2combine[1]
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* MMCR1[28] = pmc3combine[0]
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* MMCR1[29] = pmc3combine[1]
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* MMCR1[30] = pmc4combine[0]
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* MMCR1[31] = pmc4combine[1]
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*
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* if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
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* # PM_MRK_FAB_RSP_MATCH
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* MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
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* else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
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* # PM_MRK_FAB_RSP_MATCH_CYC
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* MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
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* else
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* MMCRA[48:55] = thresh_ctl (THRESH START/END)
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*
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* if thresh_sel:
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* MMCRA[45:47] = thresh_sel
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*
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* if thresh_cmp:
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* MMCRA[9:11] = thresh_cmp[0:2]
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* MMCRA[12:18] = thresh_cmp[3:9]
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*
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* if unit == 6 or unit == 7
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* MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
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* else if unit == 8 or unit == 9:
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* if cache_sel[0] == 0: # L3 bank
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* MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
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* else if cache_sel[0] == 1:
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* MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1)
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* else if cache_sel[1]: # L1 event
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* MMCR1[16] = cache_sel[2]
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* MMCR1[17] = cache_sel[3]
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*
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* if mark:
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* MMCRA[63] = 1 (SAMPLE_ENABLE)
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* MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
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* MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
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*
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* if EBB and BHRB:
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* MMCRA[32:33] = IFM
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*
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* MMCRA[SDAR_MODE] = sm
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*/
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/*
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* Some power9 event codes.
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*/
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@ -99,6 +171,48 @@ static const struct attribute_group *power9_isa207_pmu_attr_groups[] = {
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NULL,
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};
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PMU_FORMAT_ATTR(event, "config:0-51");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:10-11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
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PMU_FORMAT_ATTR(sdar_mode, "config:50-51");
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static struct attribute *power9_pmu_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_mark.attr,
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&format_attr_combine.attr,
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&format_attr_unit.attr,
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&format_attr_pmc.attr,
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&format_attr_cache_sel.attr,
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&format_attr_sample_mode.attr,
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&format_attr_thresh_sel.attr,
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&format_attr_thresh_stop.attr,
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&format_attr_thresh_start.attr,
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&format_attr_thresh_cmp.attr,
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&format_attr_sdar_mode.attr,
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NULL,
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};
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static struct attribute_group power9_pmu_format_group = {
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.name = "format",
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.attrs = power9_pmu_format_attr,
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};
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static const struct attribute_group *power9_pmu_attr_groups[] = {
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&power9_pmu_format_group,
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&power9_pmu_events_group,
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NULL,
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};
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static int power9_generic_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
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@ -278,6 +392,24 @@ static struct power_pmu power9_isa207_pmu = {
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.bhrb_nr = 32,
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};
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static struct power_pmu power9_pmu = {
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.name = "POWER9",
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.n_counter = MAX_PMU_COUNTERS,
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.add_fields = ISA207_ADD_FIELDS,
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.test_adder = ISA207_TEST_ADDER,
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.compute_mmcr = isa207_compute_mmcr,
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.config_bhrb = power9_config_bhrb,
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.bhrb_filter_map = power9_bhrb_filter_map,
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.get_constraint = isa207_get_constraint,
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.disable_pmc = isa207_disable_pmc,
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.flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
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.n_generic = ARRAY_SIZE(power9_generic_events),
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.generic_events = power9_generic_events,
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.cache_events = &power9_cache_events,
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.attr_groups = power9_pmu_attr_groups,
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.bhrb_nr = 32,
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};
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static int __init init_power9_pmu(void)
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{
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int rc = 0;
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@ -289,6 +421,8 @@ static int __init init_power9_pmu(void)
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if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
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rc = register_power_pmu(&power9_isa207_pmu);
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} else {
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rc = register_power_pmu(&power9_pmu);
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}
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if (rc)
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