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https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-25 05:04:09 +08:00
Merge branch 'pci/controller/layerscape'
- Add suspend/resume support for Layerscape LS1043a, including software-managed PME_Turn_Off and transitions between L0, L2/L3_Ready Link states (Frank Li) * pci/controller/layerscape: PCI: layerscape: Add suspend/resume for ls1043a PCI: layerscape(ep): Rename pf_* as pf_lut_* PCI: layerscape: Add suspend/resume for ls1021a PCI: layerscape: Add function pointer for exit_from_l2()
This commit is contained in:
Bjorn Helgaas
commit
1800c660b0
@ -49,7 +49,7 @@ struct ls_pcie_ep {
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bool big_endian;
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};
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static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset)
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static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset)
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{
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struct dw_pcie *pci = pcie->pci;
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@ -59,7 +59,7 @@ static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset)
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return ioread32(pci->dbi_base + offset);
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}
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static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)
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static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)
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{
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struct dw_pcie *pci = pcie->pci;
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@ -76,8 +76,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
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u32 val, cfg;
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u8 offset;
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val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
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ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
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val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR);
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ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
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if (!val)
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return IRQ_NONE;
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@ -96,9 +96,9 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
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dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
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dw_pcie_dbi_ro_wr_dis(pci);
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cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
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cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG);
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cfg |= PEX_PF0_CFG_READY;
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ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
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ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
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dw_pcie_ep_linkup(&pci->ep);
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dev_dbg(pci->dev, "Link up\n");
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@ -130,10 +130,10 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie,
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}
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/* Enable interrupts */
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val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER);
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val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER);
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val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE |
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PEX_PF0_PME_MES_IER_LUDIE;
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ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);
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ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);
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return 0;
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}
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@ -35,21 +35,41 @@
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#define PF_MCR_PTOMR BIT(0)
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#define PF_MCR_EXL2S BIT(1)
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/* LS1021A PEXn PM Write Control Register */
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#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64)
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#define PMXMTTURNOFF BIT(31)
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#define SCFG_PEXSFTRSTCR 0x190
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#define PEXSR(idx) BIT(idx)
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/* LS1043A PEX PME control register */
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#define SCFG_PEXPMECR 0x144
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#define PEXPME(idx) BIT(31 - (idx) * 4)
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/* LS1043A PEX LUT debug register */
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#define LS_PCIE_LDBG 0x7fc
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#define LDBG_SR BIT(30)
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#define LDBG_WE BIT(31)
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#define PCIE_IATU_NUM 6
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struct ls_pcie_drvdata {
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const u32 pf_off;
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const u32 pf_lut_off;
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const struct dw_pcie_host_ops *ops;
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int (*exit_from_l2)(struct dw_pcie_rp *pp);
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bool scfg_support;
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bool pm_support;
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};
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struct ls_pcie {
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struct dw_pcie *pci;
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const struct ls_pcie_drvdata *drvdata;
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void __iomem *pf_base;
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void __iomem *pf_lut_base;
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struct regmap *scfg;
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int index;
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bool big_endian;
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};
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#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr)
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#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr)
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#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
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static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
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@ -90,20 +110,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
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}
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static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)
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static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)
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{
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if (pcie->big_endian)
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return ioread32be(pcie->pf_base + off);
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return ioread32be(pcie->pf_lut_base + off);
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return ioread32(pcie->pf_base + off);
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return ioread32(pcie->pf_lut_base + off);
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}
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static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)
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static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)
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{
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if (pcie->big_endian)
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iowrite32be(val, pcie->pf_base + off);
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iowrite32be(val, pcie->pf_lut_base + off);
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else
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iowrite32(val, pcie->pf_base + off);
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iowrite32(val, pcie->pf_lut_base + off);
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}
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static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
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@ -113,11 +133,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
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u32 val;
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int ret;
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val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
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val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
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val |= PF_MCR_PTOMR;
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ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
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ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
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ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
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ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,
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val, !(val & PF_MCR_PTOMR),
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PCIE_PME_TO_L2_TIMEOUT_US/10,
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PCIE_PME_TO_L2_TIMEOUT_US);
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@ -125,7 +145,7 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
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dev_err(pcie->pci->dev, "PME_Turn_off timeout\n");
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}
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static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)
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static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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@ -136,20 +156,22 @@ static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)
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* Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link
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* to exit L2 state.
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*/
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val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
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val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
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val |= PF_MCR_EXL2S;
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ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
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ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
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/*
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* L2 exit timeout of 10ms is not defined in the specifications,
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* it was chosen based on empirical observations.
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*/
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ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
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ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,
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val, !(val & PF_MCR_EXL2S),
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1000,
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10000);
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if (ret)
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dev_err(pcie->pci->dev, "L2 exit timeout\n");
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return ret;
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}
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static int ls_pcie_host_init(struct dw_pcie_rp *pp)
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@ -168,25 +190,130 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp)
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return 0;
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}
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static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask)
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{
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/* Send PME_Turn_Off message */
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regmap_write_bits(scfg, reg, mask, mask);
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/*
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* There is no specific register to check for PME_To_Ack from endpoint.
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* So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US.
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*/
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mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
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/*
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* Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit
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* to complete the PME_Turn_Off handshake.
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*/
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regmap_write_bits(scfg, reg, mask, 0);
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}
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static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);
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}
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static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask)
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{
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/* Reset the PEX wrapper to bring the link out of L2 */
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regmap_write_bits(scfg, reg, mask, mask);
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regmap_write_bits(scfg, reg, mask, 0);
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return 0;
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}
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static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
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}
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static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index));
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}
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static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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u32 val;
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/*
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* Reset the PEX wrapper to bring the link out of L2.
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* LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and
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* clearing the soft reset on the PEX module.
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* LDBG_SR: When SR is set to 1, the PEX module enters soft reset.
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*/
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val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
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val |= LDBG_WE;
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ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
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val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
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val |= LDBG_SR;
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ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
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val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
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val &= ~LDBG_SR;
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ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
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val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
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val &= ~LDBG_WE;
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ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
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return 0;
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}
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static const struct dw_pcie_host_ops ls_pcie_host_ops = {
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.init = ls_pcie_host_init,
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.pme_turn_off = ls_pcie_send_turnoff_msg,
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};
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static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = {
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.init = ls_pcie_host_init,
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.pme_turn_off = ls1021a_pcie_send_turnoff_msg,
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};
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static const struct ls_pcie_drvdata ls1021a_drvdata = {
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.pm_support = false,
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.pm_support = true,
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.scfg_support = true,
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.ops = &ls1021a_pcie_host_ops,
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.exit_from_l2 = ls1021a_pcie_exit_from_l2,
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};
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static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = {
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.init = ls_pcie_host_init,
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.pme_turn_off = ls1043a_pcie_send_turnoff_msg,
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};
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static const struct ls_pcie_drvdata ls1043a_drvdata = {
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.pf_lut_off = 0x10000,
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.pm_support = true,
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.scfg_support = true,
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.ops = &ls1043a_pcie_host_ops,
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.exit_from_l2 = ls1043a_pcie_exit_from_l2,
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};
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static const struct ls_pcie_drvdata layerscape_drvdata = {
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.pf_off = 0xc0000,
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.pf_lut_off = 0xc0000,
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.pm_support = true,
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.ops = &ls_pcie_host_ops,
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.exit_from_l2 = ls_pcie_exit_from_l2,
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};
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
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{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },
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{ .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata },
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },
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{ .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
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{ .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
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{ .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
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@ -201,6 +328,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
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struct dw_pcie *pci;
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struct ls_pcie *pcie;
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struct resource *dbi_base;
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u32 index[2];
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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@ -213,9 +342,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
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pcie->drvdata = of_device_get_match_data(dev);
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pci->dev = dev;
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pci->pp.ops = &ls_pcie_host_ops;
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pcie->pci = pci;
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pci->pp.ops = pcie->drvdata->ops;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
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@ -224,7 +352,21 @@ static int ls_pcie_probe(struct platform_device *pdev)
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pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
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pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;
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pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;
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if (pcie->drvdata->scfg_support) {
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pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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dev_err(dev, "No syscfg phandle specified\n");
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return PTR_ERR(pcie->scfg);
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}
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ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);
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if (ret)
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return ret;
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pcie->index = index[1];
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}
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if (!ls_pcie_is_bridge(pcie))
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return -ENODEV;
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@ -247,11 +389,14 @@ static int ls_pcie_suspend_noirq(struct device *dev)
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static int ls_pcie_resume_noirq(struct device *dev)
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{
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struct ls_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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if (!pcie->drvdata->pm_support)
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return 0;
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ls_pcie_exit_from_l2(&pcie->pci->pp);
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ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp);
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if (ret)
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return ret;
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return dw_pcie_resume_noirq(pcie->pci);
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}
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