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iio: 104-quad-8: Provide defines for magic numbers
This patch adds several register and bit defines to help improve the clarity of the code by cleaning up magic numbers throughout the driver. Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
William Breathitt Gray
Jonathan Cameron
parent
f5057e7b2d
commit
17f0361936
@ -59,6 +59,39 @@ struct quad8_iio {
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unsigned int base;
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};
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#define QUAD8_REG_CHAN_OP 0x11
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#define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
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/* Borrow Toggle flip-flop */
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#define QUAD8_FLAG_BT BIT(0)
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/* Carry Toggle flip-flop */
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#define QUAD8_FLAG_CT BIT(1)
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/* Error flag */
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#define QUAD8_FLAG_E BIT(4)
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/* Up/Down flag */
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#define QUAD8_FLAG_UD BIT(5)
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/* Reset and Load Signal Decoders */
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#define QUAD8_CTR_RLD 0x00
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/* Counter Mode Register */
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#define QUAD8_CTR_CMR 0x20
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/* Input / Output Control Register */
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#define QUAD8_CTR_IOR 0x40
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/* Index Control Register */
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#define QUAD8_CTR_IDR 0x60
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/* Reset Byte Pointer (three byte data pointer) */
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#define QUAD8_RLD_RESET_BP 0x01
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/* Reset Counter */
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#define QUAD8_RLD_RESET_CNTR 0x02
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/* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
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#define QUAD8_RLD_RESET_FLAGS 0x04
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/* Reset Error flag */
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#define QUAD8_RLD_RESET_E 0x06
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/* Preset Register to Counter */
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#define QUAD8_RLD_PRESET_CNTR 0x08
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/* Transfer Counter to Output Latch */
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#define QUAD8_RLD_CNTR_OUT 0x10
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#define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
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#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
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static int quad8_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val, int *val2, long mask)
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{
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@ -72,19 +105,21 @@ static int quad8_read_raw(struct iio_dev *indio_dev,
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (chan->type == IIO_INDEX) {
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*val = !!(inb(priv->base + 0x16) & BIT(chan->channel));
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*val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
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& BIT(chan->channel));
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return IIO_VAL_INT;
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}
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flags = inb(base_offset + 1);
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borrow = flags & BIT(0);
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carry = !!(flags & BIT(1));
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borrow = flags & QUAD8_FLAG_BT;
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carry = !!(flags & QUAD8_FLAG_CT);
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/* Borrow XOR Carry effectively doubles count range */
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*val = (borrow ^ carry) << 24;
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/* Reset Byte Pointer; transfer Counter to Output Latch */
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outb(0x11, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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base_offset + 1);
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for (i = 0; i < 3; i++)
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*val |= (unsigned int)inb(base_offset) << (8 * i);
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@ -120,17 +155,17 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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return -EINVAL;
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/* Reset Byte Pointer */
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outb(0x01, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Counter can only be set via Preset Register */
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for (i = 0; i < 3; i++)
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outb(val >> (8 * i), base_offset);
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/* Transfer Preset Register to Counter */
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outb(0x08, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
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/* Reset Byte Pointer */
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outb(0x01, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Set Preset Register back to original value */
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val = priv->preset[chan->channel];
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@ -138,9 +173,9 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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outb(val >> (8 * i), base_offset);
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/* Reset Borrow, Carry, Compare, and Sign flags */
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outb(0x04, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
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/* Reset Error flag */
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outb(0x06, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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return 0;
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case IIO_CHAN_INFO_ENABLE:
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@ -153,7 +188,7 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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ior_cfg = val | priv->preset_enable[chan->channel] << 1;
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/* Load I/O control configuration */
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outb(0x40 | ior_cfg, base_offset + 1);
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
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return 0;
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case IIO_CHAN_INFO_SCALE:
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@ -217,7 +252,7 @@ static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
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priv->preset[chan->channel] = preset;
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/* Reset Byte Pointer */
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outb(0x01, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Set Preset Register */
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for (i = 0; i < 3; i++)
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@ -258,7 +293,7 @@ static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
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(unsigned int)preset_enable << 1;
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/* Load I/O control configuration to Input / Output Control Register */
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outb(0x40 | ior_cfg, base_offset);
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
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return len;
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}
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@ -274,7 +309,7 @@ static int quad8_get_noise_error(struct iio_dev *indio_dev,
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struct quad8_iio *const priv = iio_priv(indio_dev);
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const int base_offset = priv->base + 2 * chan->channel + 1;
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return !!(inb(base_offset) & BIT(4));
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return !!(inb(base_offset) & QUAD8_FLAG_E);
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}
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static const struct iio_enum quad8_noise_error_enum = {
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@ -294,7 +329,7 @@ static int quad8_get_count_direction(struct iio_dev *indio_dev,
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struct quad8_iio *const priv = iio_priv(indio_dev);
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const int base_offset = priv->base + 2 * chan->channel + 1;
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return !!(inb(base_offset) & BIT(5));
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return !!(inb(base_offset) & QUAD8_FLAG_UD);
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}
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static const struct iio_enum quad8_count_direction_enum = {
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@ -324,7 +359,7 @@ static int quad8_set_count_mode(struct iio_dev *indio_dev,
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mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
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/* Load mode configuration to Counter Mode Register */
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outb(0x20 | mode_cfg, base_offset);
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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return 0;
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}
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@ -364,7 +399,7 @@ static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
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priv->synchronous_mode[chan->channel] = synchronous_mode;
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/* Load Index Control configuration to Index Control Register */
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outb(0x60 | idr_cfg, base_offset);
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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return 0;
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}
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@ -410,7 +445,7 @@ static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
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priv->quadrature_mode[chan->channel] = quadrature_mode;
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/* Load mode configuration to Counter Mode Register */
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outb(0x20 | mode_cfg, base_offset);
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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return 0;
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}
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@ -446,7 +481,7 @@ static int quad8_set_index_polarity(struct iio_dev *indio_dev,
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priv->index_polarity[chan->channel] = index_polarity;
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/* Load Index Control configuration to Index Control Register */
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outb(0x60 | idr_cfg, base_offset);
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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return 0;
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}
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@ -556,28 +591,28 @@ static int quad8_probe(struct device *dev, unsigned int id)
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priv->base = base[id];
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/* Reset all counters and disable interrupt function */
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outb(0x01, base[id] + 0x11);
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outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
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/* Set initial configuration for all counters */
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for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
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base_offset = base[id] + 2 * i;
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/* Reset Byte Pointer */
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outb(0x01, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Reset Preset Register */
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for (j = 0; j < 3; j++)
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outb(0x00, base_offset);
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/* Reset Borrow, Carry, Compare, and Sign flags */
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outb(0x04, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
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/* Reset Error flag */
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outb(0x06, base_offset + 1);
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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/* Binary encoding; Normal count; non-quadrature mode */
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outb(0x20, base_offset + 1);
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outb(QUAD8_CTR_CMR, base_offset + 1);
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/* Disable A and B inputs; preset on index; FLG1 as Carry */
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outb(0x40, base_offset + 1);
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outb(QUAD8_CTR_IOR, base_offset + 1);
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/* Disable index function; negative index polarity */
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outb(0x60, base_offset + 1);
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outb(QUAD8_CTR_IDR, base_offset + 1);
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}
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/* Enable all counters */
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outb(0x00, base[id] + 0x11);
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outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
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return devm_iio_device_register(dev, indio_dev);
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}
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