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KVM: PPC: Book 3S: XICS: Implement ICS P/Q states
This patch implements P(Presented)/Q(Queued) states for ICS irqs. When the interrupt is presented, set P. Present if P was not set. If P is already set, don't present again, set Q. When the interrupt is EOI'ed, move Q into P (and clear Q). If it is set, re-present. The asserted flag used by LSI is also incorporated into the P bit. When the irq state is saved, P/Q bits are also saved, they need some qemu modifications to be recognized and passed around to be restored. KVM_XICS_PENDING bit set and saved should also indicate KVM_XICS_PRESENTED bit set and saved. But it is possible some old code doesn't have/recognize the P bit, so when we restore, we set P for PENDING bit, too. The idea and much of the code come from Ben. Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
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@ -613,5 +613,7 @@ struct kvm_get_htab_header {
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#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
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#define KVM_XICS_MASKED (1ULL << 41)
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#define KVM_XICS_PENDING (1ULL << 42)
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#define KVM_XICS_PRESENTED (1ULL << 43)
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#define KVM_XICS_QUEUED (1ULL << 44)
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#endif /* __LINUX_KVM_POWERPC_H */
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@ -672,51 +672,39 @@ int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
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return check_too_hard(xics, icp);
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}
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int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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static int ics_rm_eoi(struct kvm_vcpu *vcpu, u32 irq)
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{
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u32 irq = xirr & 0x00ffffff;
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u16 src;
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if (!xics || !xics->real_mode)
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return H_TOO_HARD;
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u32 pq_old, pq_new;
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/*
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* ICP State: EOI
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* ICS EOI handling: For LSI, if P bit is still set, we need to
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* resend it.
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*
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* Note: If EOI is incorrectly used by SW to lower the CPPR
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* value (ie more favored), we do not check for rejection of
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* a pending interrupt, this is a SW error and PAPR sepcifies
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* that we don't have to deal with it.
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*
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* The sending of an EOI to the ICS is handled after the
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* CPPR update
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*
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* ICP State: Down_CPPR which we handle
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* in a separate function as it's shared with H_CPPR.
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* For MSI, we move Q bit into P (and clear Q). If it is set,
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* resend it.
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*/
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icp_rm_down_cppr(xics, icp, xirr >> 24);
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/* IPIs have no EOI */
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if (irq == XICS_IPI)
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goto bail;
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/*
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* EOI handling: If the interrupt is still asserted, we need to
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* resend it. We can take a lockless "peek" at the ICS state here.
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*
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* "Message" interrupts will never have "asserted" set
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*/
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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goto bail;
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state = &ics->irq_state[src];
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/* Still asserted, resend it */
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if (state->asserted)
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icp_rm_deliver_irq(xics, icp, irq);
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if (state->lsi)
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pq_new = state->pq_state;
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else
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do {
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pq_old = state->pq_state;
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pq_new = pq_old >> 1;
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} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
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if (pq_new & PQ_PRESENTED)
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icp_rm_deliver_irq(xics, NULL, irq);
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if (!hlist_empty(&vcpu->kvm->irq_ack_notifier_list)) {
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icp->rm_action |= XICS_RM_NOTIFY_EOI;
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@ -737,10 +725,43 @@ int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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state->intr_cpu = -1;
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}
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}
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bail:
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return check_too_hard(xics, icp);
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}
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int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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{
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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u32 irq = xirr & 0x00ffffff;
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if (!xics || !xics->real_mode)
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return H_TOO_HARD;
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/*
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* ICP State: EOI
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*
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* Note: If EOI is incorrectly used by SW to lower the CPPR
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* value (ie more favored), we do not check for rejection of
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* a pending interrupt, this is a SW error and PAPR specifies
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* that we don't have to deal with it.
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*
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* The sending of an EOI to the ICS is handled after the
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* CPPR update
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*
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* ICP State: Down_CPPR which we handle
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* in a separate function as it's shared with H_CPPR.
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*/
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icp_rm_down_cppr(xics, icp, xirr >> 24);
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/* IPIs have no EOI */
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if (irq == XICS_IPI)
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return check_too_hard(xics, icp);
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return ics_rm_eoi(vcpu, irq);
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}
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unsigned long eoi_rc;
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static void icp_eoi(struct irq_chip *c, u32 hwirq, __be32 xirr, bool *again)
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@ -827,14 +848,33 @@ long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu,
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{
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struct kvmppc_xics *xics;
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struct kvmppc_icp *icp;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u32 irq;
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u16 src;
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u32 pq_old, pq_new;
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irq = irq_map->v_hwirq;
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xics = vcpu->kvm->arch.xics;
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icp = vcpu->arch.icp;
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kvmppc_rm_handle_irq_desc(irq_map->desc);
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icp_rm_deliver_irq(xics, icp, irq);
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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return 2;
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state = &ics->irq_state[src];
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/* only MSIs register bypass producers, so it must be MSI here */
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do {
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pq_old = state->pq_state;
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pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED;
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} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
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/* Test P=1, Q=0, this is the only case where we present */
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if (pq_new == PQ_PRESENTED)
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icp_rm_deliver_irq(xics, icp, irq);
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/* EOI the interrupt */
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icp_eoi(irq_desc_get_chip(irq_map->desc), irq_map->r_hwirq, xirr,
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@ -75,6 +75,7 @@ static int ics_deliver_irq(struct kvmppc_xics *xics, u32 irq, u32 level)
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struct ics_irq_state *state;
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struct kvmppc_ics *ics;
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u16 src;
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u32 pq_old, pq_new;
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XICS_DBG("ics deliver %#x (level: %d)\n", irq, level);
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@ -87,25 +88,41 @@ static int ics_deliver_irq(struct kvmppc_xics *xics, u32 irq, u32 level)
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if (!state->exists)
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return -EINVAL;
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if (level == KVM_INTERRUPT_SET_LEVEL || level == KVM_INTERRUPT_SET)
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level = 1;
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else if (level == KVM_INTERRUPT_UNSET)
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level = 0;
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/*
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* We set state->asserted locklessly. This should be fine as
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* we are the only setter, thus concurrent access is undefined
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* to begin with.
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* Take other values the same as 1, consistent with original code.
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* maybe WARN here?
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*/
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if ((level == 1 && state->lsi) || level == KVM_INTERRUPT_SET_LEVEL)
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state->asserted = 1;
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else if (level == 0 || level == KVM_INTERRUPT_UNSET) {
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state->asserted = 0;
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if (!state->lsi && level == 0) /* noop for MSI */
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return 0;
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}
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do {
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pq_old = state->pq_state;
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if (state->lsi) {
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if (level) {
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if (pq_old & PQ_PRESENTED)
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/* Setting already set LSI ... */
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return 0;
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pq_new = PQ_PRESENTED;
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} else
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pq_new = 0;
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} else
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pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED;
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} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
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/* Test P=1, Q=0, this is the only case where we present */
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if (pq_new == PQ_PRESENTED)
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icp_deliver_irq(xics, NULL, irq);
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/* Record which CPU this arrived on for passed-through interrupts */
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if (state->host_irq)
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state->intr_cpu = raw_smp_processor_id();
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/* Attempt delivery */
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icp_deliver_irq(xics, NULL, irq);
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return 0;
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}
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@ -768,14 +785,51 @@ static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
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icp_deliver_irq(xics, icp, reject);
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}
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static noinline int kvmppc_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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static int ics_eoi(struct kvm_vcpu *vcpu, u32 irq)
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{
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u32 irq = xirr & 0x00ffffff;
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u16 src;
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u32 pq_old, pq_new;
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/*
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* ICS EOI handling: For LSI, if P bit is still set, we need to
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* resend it.
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*
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* For MSI, we move Q bit into P (and clear Q). If it is set,
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* resend it.
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*/
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics) {
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XICS_DBG("ios_eoi: IRQ 0x%06x not found !\n", irq);
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return H_PARAMETER;
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}
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state = &ics->irq_state[src];
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if (state->lsi)
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pq_new = state->pq_state;
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else
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do {
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pq_old = state->pq_state;
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pq_new = pq_old >> 1;
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} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
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if (pq_new & PQ_PRESENTED)
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icp_deliver_irq(xics, icp, irq);
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kvm_notify_acked_irq(vcpu->kvm, 0, irq);
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return H_SUCCESS;
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}
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static noinline int kvmppc_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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{
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struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
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struct kvmppc_icp *icp = vcpu->arch.icp;
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u32 irq = xirr & 0x00ffffff;
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XICS_DBG("h_eoi vcpu %d eoi %#lx\n", vcpu->vcpu_id, xirr);
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@ -798,26 +852,8 @@ static noinline int kvmppc_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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/* IPIs have no EOI */
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if (irq == XICS_IPI)
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return H_SUCCESS;
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/*
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* EOI handling: If the interrupt is still asserted, we need to
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* resend it. We can take a lockless "peek" at the ICS state here.
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*
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* "Message" interrupts will never have "asserted" set
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*/
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics) {
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XICS_DBG("h_eoi: IRQ 0x%06x not found !\n", irq);
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return H_PARAMETER;
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}
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state = &ics->irq_state[src];
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/* Still asserted, resend it */
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if (state->asserted)
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icp_deliver_irq(xics, icp, irq);
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kvm_notify_acked_irq(vcpu->kvm, 0, irq);
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return H_SUCCESS;
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return ics_eoi(vcpu, irq);
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}
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int kvmppc_xics_rm_complete(struct kvm_vcpu *vcpu, u32 hcall)
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@ -975,9 +1011,9 @@ static int xics_debug_show(struct seq_file *m, void *private)
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for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
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struct ics_irq_state *irq = &ics->irq_state[i];
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seq_printf(m, "irq 0x%06x: server %#x prio %#x save prio %#x asserted %d resend %d masked pending %d\n",
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seq_printf(m, "irq 0x%06x: server %#x prio %#x save prio %#x pq_state %d resend %d masked pending %d\n",
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irq->number, irq->server, irq->priority,
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irq->saved_priority, irq->asserted,
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irq->saved_priority, irq->pq_state,
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irq->resend, irq->masked_pending);
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}
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@ -1196,10 +1232,17 @@ static int xics_get_source(struct kvmppc_xics *xics, long irq, u64 addr)
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val |= prio << KVM_XICS_PRIORITY_SHIFT;
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if (irqp->lsi) {
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val |= KVM_XICS_LEVEL_SENSITIVE;
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if (irqp->asserted)
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if (irqp->pq_state & PQ_PRESENTED)
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val |= KVM_XICS_PENDING;
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} else if (irqp->masked_pending || irqp->resend)
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val |= KVM_XICS_PENDING;
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if (irqp->pq_state & PQ_PRESENTED)
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val |= KVM_XICS_PRESENTED;
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if (irqp->pq_state & PQ_QUEUED)
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val |= KVM_XICS_QUEUED;
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ret = 0;
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}
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arch_spin_unlock(&ics->lock);
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@ -1251,12 +1294,14 @@ static int xics_set_source(struct kvmppc_xics *xics, long irq, u64 addr)
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irqp->resend = 0;
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irqp->masked_pending = 0;
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irqp->lsi = 0;
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irqp->asserted = 0;
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if (val & KVM_XICS_LEVEL_SENSITIVE) {
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irqp->pq_state = 0;
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if (val & KVM_XICS_LEVEL_SENSITIVE)
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irqp->lsi = 1;
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if (val & KVM_XICS_PENDING)
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irqp->asserted = 1;
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}
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/* If PENDING, set P in case P is not saved because of old code */
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if (val & KVM_XICS_PRESENTED || val & KVM_XICS_PENDING)
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irqp->pq_state |= PQ_PRESENTED;
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if (val & KVM_XICS_QUEUED)
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irqp->pq_state |= PQ_QUEUED;
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irqp->exists = 1;
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arch_spin_unlock(&ics->lock);
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local_irq_restore(flags);
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@ -31,16 +31,19 @@
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/* Priority value to use for disabling an interrupt */
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#define MASKED 0xff
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#define PQ_PRESENTED 1
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#define PQ_QUEUED 2
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/* State for one irq source */
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struct ics_irq_state {
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u32 number;
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u32 server;
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u32 pq_state;
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u8 priority;
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u8 saved_priority;
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u8 resend;
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u8 masked_pending;
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u8 lsi; /* level-sensitive interrupt */
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u8 asserted; /* Only for LSI */
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u8 exists;
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int intr_cpu;
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u32 host_irq;
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