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drm/amd/powerplay: move shared function of vi to hwmgr. (v2)
v2: agd: rebase on upstream Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
1ea6c1e8e4
commit
17c00a2fed
@ -91,12 +91,6 @@ enum DPM_EVENT_SRC {
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DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
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};
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enum DISPLAY_GAP {
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DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
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DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
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DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. */
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DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
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};
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/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
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* not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
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@ -27,9 +27,12 @@
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#include "cgs_common.h"
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#include "power_state.h"
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#include "hwmgr.h"
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#include "cz_hwmgr.h"
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#include "tonga_hwmgr.h"
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#include "pppcielanes.h"
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#include "pp_debug.h"
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#include "ppatomctrl.h"
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extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
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int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
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@ -112,6 +115,7 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
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for (i = 0; i < table_entries; i++) {
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result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
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if (state->classification.flags & PP_StateClassificationFlag_Boot) {
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hwmgr->boot_ps = state;
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hwmgr->current_ps = hwmgr->request_ps = state;
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@ -226,3 +230,331 @@ bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
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{
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return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
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}
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int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
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{
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uint32_t i, j;
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uint16_t vvalue;
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bool found = false;
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struct pp_atomctrl_voltage_table *table;
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"Voltage Table empty.", return -EINVAL);
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table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
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GFP_KERNEL);
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if (NULL == table)
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return -EINVAL;
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table->mask_low = vol_table->mask_low;
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table->phase_delay = vol_table->phase_delay;
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for (i = 0; i < vol_table->count; i++) {
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vvalue = vol_table->entries[i].value;
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found = false;
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for (j = 0; j < table->count; j++) {
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if (vvalue == table->entries[j].value) {
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found = true;
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break;
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}
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}
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if (!found) {
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table->entries[table->count].value = vvalue;
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table->entries[table->count].smio_low =
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vol_table->entries[i].smio_low;
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table->count++;
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}
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}
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memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
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kfree(table);
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return 0;
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}
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int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
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phm_ppt_v1_clock_voltage_dependency_table *dep_table)
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{
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uint32_t i;
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int result;
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PP_ASSERT_WITH_CODE((0 != dep_table->count),
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"Voltage Dependency Table empty.", return -EINVAL);
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"vol_table empty.", return -EINVAL);
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vol_table->mask_low = 0;
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vol_table->phase_delay = 0;
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vol_table->count = dep_table->count;
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for (i = 0; i < dep_table->count; i++) {
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vol_table->entries[i].value = dep_table->entries[i].mvdd;
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vol_table->entries[i].smio_low = 0;
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}
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result = phm_trim_voltage_table(vol_table);
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PP_ASSERT_WITH_CODE((0 == result),
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"Failed to trim MVDD table.", return result);
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return 0;
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}
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int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
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phm_ppt_v1_clock_voltage_dependency_table *dep_table)
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{
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uint32_t i;
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int result;
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PP_ASSERT_WITH_CODE((0 != dep_table->count),
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"Voltage Dependency Table empty.", return -EINVAL);
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"vol_table empty.", return -EINVAL);
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vol_table->mask_low = 0;
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vol_table->phase_delay = 0;
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vol_table->count = dep_table->count;
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for (i = 0; i < dep_table->count; i++) {
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vol_table->entries[i].value = dep_table->entries[i].vddci;
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vol_table->entries[i].smio_low = 0;
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}
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result = phm_trim_voltage_table(vol_table);
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PP_ASSERT_WITH_CODE((0 == result),
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"Failed to trim VDDCI table.", return result);
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return 0;
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}
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int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
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phm_ppt_v1_voltage_lookup_table *lookup_table)
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{
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int i = 0;
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PP_ASSERT_WITH_CODE((0 != lookup_table->count),
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"Voltage Lookup Table empty.", return -EINVAL);
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PP_ASSERT_WITH_CODE((NULL != vol_table),
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"vol_table empty.", return -EINVAL);
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vol_table->mask_low = 0;
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vol_table->phase_delay = 0;
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vol_table->count = lookup_table->count;
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for (i = 0; i < vol_table->count; i++) {
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vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
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vol_table->entries[i].smio_low = 0;
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}
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return 0;
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}
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void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
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struct pp_atomctrl_voltage_table *vol_table)
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{
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unsigned int i, diff;
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if (vol_table->count <= max_vol_steps)
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return;
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diff = vol_table->count - max_vol_steps;
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for (i = 0; i < max_vol_steps; i++)
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vol_table->entries[i] = vol_table->entries[i + diff];
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vol_table->count = max_vol_steps;
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return;
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}
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int phm_reset_single_dpm_table(void *table,
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uint32_t count, int max)
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{
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int i;
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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PP_ASSERT_WITH_CODE(count <= max,
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"Fatal error, can not set up single DPM table entries to exceed max number!",
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);
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dpm_table->count = count;
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for (i = 0; i < max; i++)
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dpm_table->dpm_level[i].enabled = false;
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return 0;
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}
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void phm_setup_pcie_table_entry(
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void *table,
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uint32_t index, uint32_t pcie_gen,
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uint32_t pcie_lanes)
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{
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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dpm_table->dpm_level[index].value = pcie_gen;
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dpm_table->dpm_level[index].param1 = pcie_lanes;
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dpm_table->dpm_level[index].enabled = 1;
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}
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int32_t phm_get_dpm_level_enable_mask_value(void *table)
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{
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int32_t i;
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int32_t mask = 0;
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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for (i = dpm_table->count; i > 0; i--) {
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mask = mask << 1;
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if (dpm_table->dpm_level[i - 1].enabled)
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mask |= 0x1;
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else
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mask &= 0xFFFFFFFE;
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}
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return mask;
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}
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uint8_t phm_get_voltage_index(
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struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
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{
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uint8_t count = (uint8_t) (lookup_table->count);
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uint8_t i;
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PP_ASSERT_WITH_CODE((NULL != lookup_table),
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"Lookup Table empty.", return 0);
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PP_ASSERT_WITH_CODE((0 != count),
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"Lookup Table empty.", return 0);
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for (i = 0; i < lookup_table->count; i++) {
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/* find first voltage equal or bigger than requested */
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if (lookup_table->entries[i].us_vdd >= voltage)
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return i;
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}
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/* voltage is bigger than max voltage in the table */
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return i - 1;
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}
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uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
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{
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uint32_t i;
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for (i = 0; i < vddci_table->count; i++) {
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if (vddci_table->entries[i].value >= vddci)
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return vddci_table->entries[i].value;
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}
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PP_ASSERT_WITH_CODE(false,
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"VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
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return vddci_table->entries[i].value);
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}
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int phm_find_boot_level(void *table,
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uint32_t value, uint32_t *boot_level)
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{
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int result = -EINVAL;
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uint32_t i;
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struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
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for (i = 0; i < dpm_table->count; i++) {
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if (value == dpm_table->dpm_level[i].value) {
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*boot_level = i;
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result = 0;
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}
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}
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return result;
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}
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int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
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phm_ppt_v1_voltage_lookup_table *lookup_table,
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uint16_t virtual_voltage_id, int32_t *sclk)
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{
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uint8_t entryId;
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uint8_t voltageId;
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
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/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
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for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
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voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
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if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
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break;
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}
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PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
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"Can't find requested voltage id in vdd_dep_on_sclk table!",
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return -EINVAL;
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);
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*sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
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return 0;
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}
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/**
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* Initialize Dynamic State Adjustment Rule Settings
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*
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* @param hwmgr the address of the powerplay hardware manager.
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*/
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int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
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{
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uint32_t table_size;
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struct phm_clock_voltage_dependency_table *table_clk_vlt;
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struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
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/* initialize vddc_dep_on_dal_pwrl table */
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table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
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table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
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if (NULL == table_clk_vlt) {
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printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
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return -ENOMEM;
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} else {
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table_clk_vlt->count = 4;
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table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
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table_clk_vlt->entries[0].v = 0;
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table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
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table_clk_vlt->entries[1].v = 720;
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table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
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table_clk_vlt->entries[2].v = 810;
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table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
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table_clk_vlt->entries[3].v = 900;
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pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
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hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
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}
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return 0;
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}
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int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
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{
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if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
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kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
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hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
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}
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if (NULL != hwmgr->backend) {
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kfree(hwmgr->backend);
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hwmgr->backend = NULL;
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}
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return 0;
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}
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uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
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{
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uint32_t level = 0;
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while (0 == (mask & (1 << level)))
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level++;
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return level;
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}
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@ -110,14 +110,6 @@ enum DPM_EVENT_SRC {
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};
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typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
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enum DISPLAY_GAP {
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DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
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DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
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DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
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DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
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};
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typedef enum DISPLAY_GAP DISPLAY_GAP;
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const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
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struct tonga_power_state *cast_phw_tonga_power_state(
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@ -29,6 +29,8 @@
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#include "hardwaremanager.h"
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#include "pp_power_source.h"
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#include "hwmgr_ppt.h"
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#include "ppatomctrl.h"
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#include "hwmgr_ppt.h"
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struct pp_instance;
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struct pp_hwmgr;
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@ -36,6 +38,28 @@ struct pp_hw_power_state;
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struct pp_power_state;
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struct PP_VCEState;
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struct phm_fan_speed_info;
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struct pp_atomctrl_voltage_table;
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enum DISPLAY_GAP {
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DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
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DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
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DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
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DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
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};
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typedef enum DISPLAY_GAP DISPLAY_GAP;
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struct vi_dpm_level {
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bool enabled;
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uint32_t value;
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uint32_t param1;
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};
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struct vi_dpm_table {
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uint32_t count;
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struct vi_dpm_level dpm_level[1];
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};
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enum PP_Result {
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PP_Result_TableImmediateExit = 0x13,
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@ -628,9 +652,27 @@ extern void phm_wait_for_indirect_register_unequal(
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uint32_t value,
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uint32_t mask);
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bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
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bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
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bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
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extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
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extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
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extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
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extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
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extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
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extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
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extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
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extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
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extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
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extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
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extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
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extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
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extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
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extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
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extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
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uint16_t virtual_voltage_id, int32_t *sclk);
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extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
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extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
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extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
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||||
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#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
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||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user