phy: ti: gmii-sel: Enable SGMII mode for J7200

TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230309063514.398705-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Siddharth Vadapalli 2023-03-09 12:05:13 +05:30 committed by Vinod Koul
parent 6a30118842
commit 178b651521

View File

@ -221,7 +221,7 @@ static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true, .use_of_data = true,
.regfields = phy_gmii_sel_fields_am654, .regfields = phy_gmii_sel_fields_am654,
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
.num_ports = 4, .num_ports = 4,
.num_qsgmii_main_ports = 1, .num_qsgmii_main_ports = 1,
}; };