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drm/tegra: rgb: Parameterize V- and H-sync polarities
The polarities of the V- and H-sync signals are encoded as flags in the display mode, so use the existing information to setup the signals for the RGB interface. Signed-off-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> [tomi.valkeinen@ideasonboard.com: default to positive sync] Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> # Asus TF700T Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230906-tc358768-v4-1-31725f008a50@ideasonboard.com
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@ -99,6 +99,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
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static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
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{
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struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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struct tegra_output *output = encoder_to_output(encoder);
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struct tegra_rgb *rgb = to_rgb(output);
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u32 value;
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@ -108,10 +109,19 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
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value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
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tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
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/* XXX: parameterize? */
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/* configure H- and V-sync signal polarities */
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value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
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value &= ~LVS_OUTPUT_POLARITY_LOW;
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value &= ~LHS_OUTPUT_POLARITY_LOW;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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value |= LHS_OUTPUT_POLARITY_LOW;
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else
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value &= ~LHS_OUTPUT_POLARITY_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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value |= LVS_OUTPUT_POLARITY_LOW;
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else
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value &= ~LVS_OUTPUT_POLARITY_LOW;
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tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
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/* XXX: parameterize? */
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