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LoongArch: Fix GMAC's phy-mode definitions in dts
[ Upstream commit eb36e520f4
]
The GMAC of Loongson chips cannot insert the correct 1.5-2ns delay. So
we need the PHY to insert internal delays for both transmit and receive
data lines from/to the PHY device. Fix this by changing the "phy-mode"
from "rgmii" to "rgmii-id" in dts.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
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@ -44,14 +44,14 @@
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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bus_id = <0x0>;
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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bus_id = <0x1>;
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};
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@ -43,7 +43,7 @@
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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mdio {
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compatible = "snps,dwmac-mdio";
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@ -58,7 +58,7 @@
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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phy-handle = <&phy1>;
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mdio {
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compatible = "snps,dwmac-mdio";
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@ -92,7 +92,7 @@
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&gmac2 {
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status = "okay";
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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phy-handle = <&phy2>;
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mdio {
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compatible = "snps,dwmac-mdio";
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