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drm/amdgpu: EEPROM: add explicit read and write
Add explicit amdgpu_eeprom_read() and amdgpu_eeprom_write() for clarity. Cc: Jean Delvare <jdelvare@suse.de> Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Cc: Stanley Yang <Stanley.Yang@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -29,4 +29,20 @@
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int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
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u8 *eeprom_buf, u16 bytes, bool read);
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static inline int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
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u32 eeprom_addr, u8 *eeprom_buf,
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u16 bytes)
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{
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return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
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true);
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}
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static inline int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
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u32 eeprom_addr, u8 *eeprom_buf,
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u16 bytes)
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{
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return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
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false);
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}
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#endif
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@ -66,7 +66,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
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{
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int ret, size;
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ret = amdgpu_eeprom_xfer(&adev->pm.smu_i2c, addrptr, buff, 1, true);
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ret = amdgpu_eeprom_read(&adev->pm.smu_i2c, addrptr, buff, 1);
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if (ret < 1) {
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DRM_WARN("FRU: Failed to get size field");
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return ret;
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@ -77,8 +77,7 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
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*/
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size = buff[0] - I2C_PRODUCT_INFO_OFFSET;
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ret = amdgpu_eeprom_xfer(&adev->pm.smu_i2c, addrptr + 1, buff, size,
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true);
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ret = amdgpu_eeprom_read(&adev->pm.smu_i2c, addrptr + 1, buff, size);
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if (ret < 1) {
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DRM_WARN("FRU: Failed to get data field");
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return ret;
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@ -151,9 +151,9 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
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/* i2c may be unstable in gpu reset */
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down_read(&adev->reset_sem);
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ret = amdgpu_eeprom_xfer(&adev->pm.smu_i2c,
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control->i2c_address + RAS_HDR_START,
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buff, RAS_TABLE_HEADER_SIZE, false);
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ret = amdgpu_eeprom_write(&adev->pm.smu_i2c,
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control->i2c_address + RAS_HDR_START,
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buff, RAS_TABLE_HEADER_SIZE);
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up_read(&adev->reset_sem);
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if (ret < 1)
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@ -298,9 +298,9 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
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mutex_init(&control->tbl_mutex);
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/* Read/Create table header from EEPROM address 0 */
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ret = amdgpu_eeprom_xfer(&adev->pm.smu_i2c,
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ret = amdgpu_eeprom_read(&adev->pm.smu_i2c,
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control->i2c_address + RAS_HDR_START,
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buff, RAS_TABLE_HEADER_SIZE, true);
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buff, RAS_TABLE_HEADER_SIZE);
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if (ret < 1) {
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DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
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return ret;
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