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clk: at91: fix div by zero in USB clock driver

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Test rate value before calculating the div value to avoid div by zero.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Boris BREZILLON 2014-09-02 09:50:18 +02:00 committed by Mike Turquette
parent 13a6073d4c
commit 16eeaec779
1 changed files with 5 additions and 2 deletions
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7
drivers/clk/at91/clk-usb.c
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@ -279,10 +279,13 @@ static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
int i;
struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
struct at91_pmc *pmc = usb->pmc;
unsigned long div = parent_rate / rate;
unsigned long div;
if (parent_rate % rate)
if (!rate || parent_rate % rate)
return -EINVAL;
div = parent_rate / rate;
for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
if (usb->divisors[i] == div) {
tmp = pmc_read(pmc, AT91_CKGR_PLLBR) &