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drm/amdgpu: rename amdgpu_update_display_priority
Rename as amdgpu_display_update_priority for consistency. Signed-off-by: Samuel Li <Samuel.Li@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1833,7 +1833,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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struct amdgpu_job* job, bool force);
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void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
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bool amdgpu_device_need_post(struct amdgpu_device *adev);
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void amdgpu_update_display_priority(struct amdgpu_device *adev);
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void amdgpu_display_update_priority(struct amdgpu_device *adev);
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void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
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u64 num_vis_bytes);
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@ -646,7 +646,7 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
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return 0;
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}
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void amdgpu_update_display_priority(struct amdgpu_device *adev)
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void amdgpu_display_update_priority(struct amdgpu_device *adev)
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{
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/* adjustment options for the display watermarks */
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if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
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@ -1205,7 +1205,7 @@ static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
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u32 num_heads = 0, lb_size;
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int i;
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amdgpu_update_display_priority(adev);
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amdgpu_display_update_priority(adev);
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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if (adev->mode_info.crtcs[i]->base.enabled)
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@ -1229,7 +1229,7 @@ static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
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u32 num_heads = 0, lb_size;
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int i;
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amdgpu_update_display_priority(adev);
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amdgpu_display_update_priority(adev);
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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if (adev->mode_info.crtcs[i]->base.enabled)
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@ -1108,7 +1108,7 @@ static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
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if (!adev->mode_info.mode_config_initialized)
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return;
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amdgpu_update_display_priority(adev);
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amdgpu_display_update_priority(adev);
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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if (adev->mode_info.crtcs[i]->base.enabled)
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@ -1144,7 +1144,7 @@ static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
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u32 num_heads = 0, lb_size;
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int i;
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amdgpu_update_display_priority(adev);
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amdgpu_display_update_priority(adev);
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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if (adev->mode_info.crtcs[i]->base.enabled)
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