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drm/i915: Move uncore definitions into a separate header
In order to allow use of e.g. forcewake_domains in a other feature headers included from the top of i915_drv.h, move all uncore related definitions into their own header. v2: move __mask_next_bit macro to utils header (Mika) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
This commit is contained in:
Michal Wajdeczko
Mika Kuoppala
parent
261aeba834
commit
16586fcd86
@ -55,6 +55,7 @@
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#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_uncore.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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@ -676,116 +677,6 @@ struct drm_i915_display_funcs {
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void (*load_luts)(struct drm_crtc_state *crtc_state);
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};
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enum forcewake_domain_id {
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FW_DOMAIN_ID_RENDER = 0,
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FW_DOMAIN_ID_BLITTER,
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FW_DOMAIN_ID_MEDIA,
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FW_DOMAIN_ID_COUNT
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};
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enum forcewake_domains {
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FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
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FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
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FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
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FORCEWAKE_ALL = (FORCEWAKE_RENDER |
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FORCEWAKE_BLITTER |
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FORCEWAKE_MEDIA)
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};
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#define FW_REG_READ (1)
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#define FW_REG_WRITE (2)
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enum decoupled_power_domain {
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GEN9_DECOUPLED_PD_BLITTER = 0,
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GEN9_DECOUPLED_PD_RENDER,
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GEN9_DECOUPLED_PD_MEDIA,
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GEN9_DECOUPLED_PD_ALL
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};
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enum decoupled_ops {
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GEN9_DECOUPLED_OP_WRITE = 0,
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GEN9_DECOUPLED_OP_READ
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};
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enum forcewake_domains
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intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
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i915_reg_t reg, unsigned int op);
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struct intel_uncore_funcs {
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void (*force_wake_get)(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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void (*force_wake_put)(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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void (*mmio_writeb)(struct drm_i915_private *dev_priv,
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i915_reg_t r, uint8_t val, bool trace);
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void (*mmio_writew)(struct drm_i915_private *dev_priv,
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i915_reg_t r, uint16_t val, bool trace);
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void (*mmio_writel)(struct drm_i915_private *dev_priv,
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i915_reg_t r, uint32_t val, bool trace);
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};
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struct intel_forcewake_range {
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u32 start;
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u32 end;
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enum forcewake_domains domains;
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};
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struct intel_uncore {
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spinlock_t lock; /** lock is also taken in irq contexts. */
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const struct intel_forcewake_range *fw_domains_table;
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unsigned int fw_domains_table_entries;
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struct notifier_block pmic_bus_access_nb;
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struct intel_uncore_funcs funcs;
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unsigned fifo_count;
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enum forcewake_domains fw_domains;
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enum forcewake_domains fw_domains_active;
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u32 fw_set;
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u32 fw_clear;
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u32 fw_reset;
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struct intel_uncore_forcewake_domain {
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enum forcewake_domain_id id;
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enum forcewake_domains mask;
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unsigned wake_count;
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struct hrtimer timer;
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i915_reg_t reg_set;
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i915_reg_t reg_ack;
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} fw_domain[FW_DOMAIN_ID_COUNT];
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int unclaimed_mmio_check;
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};
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#define __mask_next_bit(mask) ({ \
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int __idx = ffs(mask) - 1; \
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mask &= ~BIT(__idx); \
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__idx; \
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})
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/* Iterate over initialised fw domains */
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#define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
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for (tmp__ = (mask__); \
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tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
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#define for_each_fw_domain(domain__, dev_priv__, tmp__) \
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for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
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#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
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#define CSR_VERSION_MAJOR(version) ((version) >> 16)
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#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
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@ -3063,52 +2954,6 @@ extern void intel_irq_fini(struct drm_i915_private *dev_priv);
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int intel_irq_install(struct drm_i915_private *dev_priv);
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void intel_irq_uninstall(struct drm_i915_private *dev_priv);
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extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
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extern void intel_uncore_init(struct drm_i915_private *dev_priv);
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extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
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extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
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extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
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extern void intel_uncore_suspend(struct drm_i915_private *dev_priv);
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extern void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
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const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
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void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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/* Like above but the caller must manage the uncore.lock itself.
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* Must be used with I915_READ_FW and friends.
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*/
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void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
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void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
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int intel_wait_for_register(struct drm_i915_private *dev_priv,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int timeout_ms);
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int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms,
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u32 *out_value);
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static inline
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int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int timeout_ms)
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{
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return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
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2, timeout_ms, NULL);
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}
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static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
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{
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return dev_priv->gvt;
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@ -92,4 +92,10 @@
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__T; \
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})
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#define __mask_next_bit(mask) ({ \
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int __idx = ffs(mask) - 1; \
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mask &= ~BIT(__idx); \
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__idx; \
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})
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#endif /* !__I915_UTILS_H */
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@ -801,6 +801,18 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
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__unclaimed_reg_debug(dev_priv, reg, read, before);
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}
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enum decoupled_power_domain {
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GEN9_DECOUPLED_PD_BLITTER = 0,
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GEN9_DECOUPLED_PD_RENDER,
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GEN9_DECOUPLED_PD_MEDIA,
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GEN9_DECOUPLED_PD_ALL
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};
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enum decoupled_ops {
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GEN9_DECOUPLED_OP_WRITE = 0,
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GEN9_DECOUPLED_OP_READ
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};
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static const enum decoupled_power_domain fw2dpd_domain[] = {
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GEN9_DECOUPLED_PD_RENDER,
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GEN9_DECOUPLED_PD_BLITTER,
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169
drivers/gpu/drm/i915/intel_uncore.h
Normal file
169
drivers/gpu/drm/i915/intel_uncore.h
Normal file
@ -0,0 +1,169 @@
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef __INTEL_UNCORE_H__
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#define __INTEL_UNCORE_H__
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struct drm_i915_private;
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enum forcewake_domain_id {
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FW_DOMAIN_ID_RENDER = 0,
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FW_DOMAIN_ID_BLITTER,
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FW_DOMAIN_ID_MEDIA,
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FW_DOMAIN_ID_COUNT
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};
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enum forcewake_domains {
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FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
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FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
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FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
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FORCEWAKE_ALL = (FORCEWAKE_RENDER |
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FORCEWAKE_BLITTER |
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FORCEWAKE_MEDIA)
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};
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struct intel_uncore_funcs {
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void (*force_wake_get)(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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void (*force_wake_put)(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv,
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i915_reg_t r, bool trace);
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void (*mmio_writeb)(struct drm_i915_private *dev_priv,
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i915_reg_t r, uint8_t val, bool trace);
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void (*mmio_writew)(struct drm_i915_private *dev_priv,
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i915_reg_t r, uint16_t val, bool trace);
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void (*mmio_writel)(struct drm_i915_private *dev_priv,
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i915_reg_t r, uint32_t val, bool trace);
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};
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struct intel_forcewake_range {
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u32 start;
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u32 end;
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enum forcewake_domains domains;
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};
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struct intel_uncore {
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spinlock_t lock; /** lock is also taken in irq contexts. */
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const struct intel_forcewake_range *fw_domains_table;
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unsigned int fw_domains_table_entries;
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struct notifier_block pmic_bus_access_nb;
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struct intel_uncore_funcs funcs;
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unsigned int fifo_count;
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enum forcewake_domains fw_domains;
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enum forcewake_domains fw_domains_active;
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u32 fw_set;
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u32 fw_clear;
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u32 fw_reset;
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struct intel_uncore_forcewake_domain {
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enum forcewake_domain_id id;
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enum forcewake_domains mask;
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unsigned int wake_count;
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struct hrtimer timer;
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i915_reg_t reg_set;
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i915_reg_t reg_ack;
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} fw_domain[FW_DOMAIN_ID_COUNT];
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int unclaimed_mmio_check;
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};
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/* Iterate over initialised fw domains */
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#define for_each_fw_domain_masked(domain__, mask__, dev_priv__, tmp__) \
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for (tmp__ = (mask__); \
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tmp__ ? (domain__ = &(dev_priv__)->uncore.fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
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#define for_each_fw_domain(domain__, dev_priv__, tmp__) \
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for_each_fw_domain_masked(domain__, (dev_priv__)->uncore.fw_domains, dev_priv__, tmp__)
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void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
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void intel_uncore_init(struct drm_i915_private *dev_priv);
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bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
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bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
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void intel_uncore_fini(struct drm_i915_private *dev_priv);
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void intel_uncore_suspend(struct drm_i915_private *dev_priv);
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void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
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u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
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void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
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const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
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enum forcewake_domains
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intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
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i915_reg_t reg, unsigned int op);
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#define FW_REG_READ (1)
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#define FW_REG_WRITE (2)
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void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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/* Like above but the caller must manage the uncore.lock itself.
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* Must be used with I915_READ_FW and friends.
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*/
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void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
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enum forcewake_domains domains);
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int intel_wait_for_register(struct drm_i915_private *dev_priv,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int timeout_ms);
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int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms,
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u32 *out_value);
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static inline
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int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
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i915_reg_t reg,
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u32 mask,
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u32 value,
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unsigned int timeout_ms)
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{
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return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
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2, timeout_ms, NULL);
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}
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#endif /* !__INTEL_UNCORE_H__ */
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