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drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
If VRR is enabled, the sink should ignore MSA parameters and regenerate incoming video stream without depending on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN bit if VRR is enabled. Reset this bit on VRR disable. v2: * ACtually set the dpcd msa ignore bit (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
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@ -3553,6 +3553,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
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return DP_TP_STATUS(encoder->port);
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return DP_TP_STATUS(encoder->port);
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}
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}
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static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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bool enable)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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if (!crtc_state->vrr.enable)
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return;
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if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
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enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
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drm_dbg_kms(&i915->drm,
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"Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
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enable ? "enable" : "disable");
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}
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static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
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static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state)
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const struct intel_crtc_state *crtc_state)
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{
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{
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@ -4351,6 +4367,9 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state,
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/* Disable the decompression in DP Sink */
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/* Disable the decompression in DP Sink */
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intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
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intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
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false);
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false);
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/* Disable Ignore_MSA bit in DP Sink */
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intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
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false);
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}
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}
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static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
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static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
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@ -434,7 +434,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
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drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
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drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
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&rate_select, 1);
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&rate_select, 1);
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link_config[0] = 0;
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link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
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link_config[1] = DP_SET_ANSI_8B10B;
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link_config[1] = DP_SET_ANSI_8B10B;
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drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
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drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
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