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MIPS: store the appended dtb address in a variable
Instead of rewriting the arguments to match the UHI spec, store the address of a appended or UHI supplied dtb in fw_supplied_dtb. That way the original bootloader arugments are kept intact while still making the use of an appended dtb invisible for mach code. Mach code can still find out if it is an appended dtb by comparing fw_arg1 with fw_supplied_dtb. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alban Bedel <albeu@free.fr> Cc: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -204,8 +204,8 @@ void __init plat_mem_setup(void)
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fdt_start = fw_getenvl("fdt_start");
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if (fdt_start)
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__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
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else if (fw_arg0 == -2)
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__dt_setup_arch((void *)KSEG0ADDR(fw_arg1));
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else if (fw_passed_dtb)
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__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
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if (mips_machtype != ATH79_MACH_GENERIC_OF) {
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ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
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@ -162,8 +162,8 @@ void __init plat_mem_setup(void)
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/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
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if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
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dtb = phys_to_virt(fw_arg2);
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else if (fw_arg0 == -2) /* UHI interface */
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dtb = (void *)fw_arg1;
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else if (fw_passed_dtb) /* UHI interface */
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dtb = (void *)fw_passed_dtb;
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else if (__dtb_start != __dtb_end)
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dtb = (void *)__dtb_start;
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else
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@ -127,6 +127,10 @@ extern char arcs_cmdline[COMMAND_LINE_SIZE];
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*/
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extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
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#ifdef CONFIG_USE_OF
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extern unsigned long fw_passed_dtb;
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#endif
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/*
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* Platform memory detection hook called by setup_arch
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*/
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@ -93,21 +93,24 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
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jr t0
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0:
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#ifdef CONFIG_USE_OF
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#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
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PTR_LA t0, __appended_dtb
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PTR_LA t2, __appended_dtb
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#ifdef CONFIG_CPU_BIG_ENDIAN
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li t1, 0xd00dfeed
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#else
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li t1, 0xedfe0dd0
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#endif
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lw t2, (t0)
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bne t1, t2, not_found
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nop
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lw t0, (t2)
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beq t0, t1, dtb_found
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#endif
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li t1, -2
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beq a0, t1, dtb_found
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move t2, a1
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move a1, t0
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PTR_LI a0, -2
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not_found:
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li t2, 0
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dtb_found:
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#endif
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PTR_LA t0, __bss_start # clear .bss
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LONG_S zero, (t0)
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@ -122,6 +125,10 @@ not_found:
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LONG_S a2, fw_arg2
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LONG_S a3, fw_arg3
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#ifdef CONFIG_USE_OF
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LONG_S t2, fw_passed_dtb
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#endif
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MTC0 zero, CP0_CONTEXT # clear context register
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PTR_LA $28, init_thread_union
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/* Set the SP after an empty pt_regs. */
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@ -875,6 +875,10 @@ void __init setup_arch(char **cmdline_p)
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unsigned long kernelsp[NR_CPUS];
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unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
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#ifdef CONFIG_USE_OF
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unsigned long fw_passed_dtb;
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#endif
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#ifdef CONFIG_DEBUG_FS
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struct dentry *mips_debugfs_dir;
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static int __init debugfs_mips(void)
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@ -74,8 +74,8 @@ void __init plat_mem_setup(void)
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set_io_port_base((unsigned long) KSEG1);
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if (fw_arg0 == -2) /* UHI interface */
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dtb = (void *)fw_arg1;
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if (fw_passed_dtb) /* UHI interface */
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dtb = (void *)fw_passed_dtb;
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else if (__dtb_start != __dtb_end)
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dtb = (void *)__dtb_start;
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else
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@ -33,8 +33,8 @@ static ulong get_fdtaddr(void)
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{
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ulong ftaddr = 0;
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if ((fw_arg0 == -2) && fw_arg1 && !fw_arg2 && !fw_arg3)
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return (ulong)fw_arg1;
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if (fw_passed_dtb && !fw_arg2 && !fw_arg3)
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return (ulong)fw_passed_dtb;
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if (__dtb_start < __dtb_end)
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ftaddr = (ulong)__dtb_start;
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