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iwlwifi: pcie: use shadow registers for updating write pointer
The RX queues have a shadow register for the write pointer that enables updates without grabbing NIC access. Use them instead of the periphery registers because accessing those is much more expensive. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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@ -321,6 +321,9 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
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/* Write index table */
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#define RFH_Q0_FRBDCB_WIDX 0xA08080
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#define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4)
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/* Write index table - shadow registers */
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#define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
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#define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
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/* Read index table */
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#define RFH_Q0_FRBDCB_RIDX 0xA080C0
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#define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4)
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@ -208,8 +208,8 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
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rxq->write_actual = round_down(rxq->write, 8);
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if (trans->cfg->mq_rx_supported)
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iwl_write_prph(trans, RFH_Q_FRBDCB_WIDX(rxq->id),
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rxq->write_actual);
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iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
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rxq->write_actual);
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/*
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* write to FH_RSCSR_CHNL0_WPTR register even in MQ as a W/A to
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* hardware shadow registers bug - writing to RFH_Q_FRBDCB_WIDX will
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