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net: dsa: Add Lantiq / Intel DSA driver for vrx200
This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC. This switch is integrated in the DSL SoC, this SoC uses a GSWIP version 2.1, there are other SoCs using different versions of this IP block, but this driver was only tested with the version found in the VRX200. Currently only the basic features are implemented which will forward all packages to the CPU and let the CPU do the forwarding. The hardware also support Layer 2 offloading which is not yet implemented in this driver. The GPHY FW loaded is now done by this driver and not any more by the separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver is a separate patch. to make use of the GPHY this switch driver is needed anyway. Other SoCs have more embedded GPHYs so this driver should support a variable number of GPHYs. After the firmware was loaded the GPHY can be probed on the MDIO bus and it behaves like an external GPHY, without the firmware it can not be probed on the MDIO bus. The clock names in the sysctrl.c file have to be changed because the clocks are now used by a different driver. This should be cleaned up and a real common clock driver should provide the clocks instead. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hauke Mehrtens
David S. Miller
parent
86ce2bc73c
commit
14fceff477
@ -8173,6 +8173,8 @@ L: netdev@vger.kernel.org
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S: Maintained
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F: net/dsa/tag_gswip.c
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F: drivers/net/ethernet/lantiq_xrx200.c
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F: drivers/net/dsa/lantiq_pce.h
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F: drivers/net/dsa/intel_gswip.c
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LANTIQ MIPS ARCHITECTURE
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M: John Crispin <john@phrozen.org>
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@ -516,8 +516,8 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
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PMU_PPE_DP | PMU_PPE_TC);
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clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
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clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);
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clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);
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clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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@ -540,8 +540,8 @@ void __init ltq_soc_init(void)
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB | PMU_PPE_TOP);
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clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
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clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e108000.gswip", "gphy0", 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e108000.gswip", "gphy1", 0, 0, PMU_GPHY);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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@ -23,6 +23,14 @@ config NET_DSA_LOOP
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This enables support for a fake mock-up switch chip which
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exercises the DSA APIs.
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config NET_DSA_LANTIQ_GSWIP
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tristate "Lantiq / Intel GSWIP"
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depends on NET_DSA
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select NET_DSA_TAG_GSWIP
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---help---
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This enables support for the Lantiq / Intel GSWIP 2.1 found in
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the xrx200 / VR9 SoC.
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config NET_DSA_MT7530
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tristate "Mediatek MT7530 Ethernet switch support"
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depends on NET_DSA
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@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
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ifdef CONFIG_NET_DSA_LOOP
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obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o
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endif
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obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
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obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
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obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
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obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
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1169
drivers/net/dsa/lantiq_gswip.c
Normal file
1169
drivers/net/dsa/lantiq_gswip.c
Normal file
File diff suppressed because it is too large
Load Diff
153
drivers/net/dsa/lantiq_pce.h
Normal file
153
drivers/net/dsa/lantiq_pce.h
Normal file
@ -0,0 +1,153 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCE microcode extracted from UGW 7.1.1 switch api
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*
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* Copyright (c) 2012, 2014, 2015 Lantiq Deutschland GmbH
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* Copyright (C) 2012 John Crispin <john@phrozen.org>
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* Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
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*/
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enum {
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OUT_MAC0 = 0,
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OUT_MAC1,
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OUT_MAC2,
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OUT_MAC3,
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OUT_MAC4,
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OUT_MAC5,
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OUT_ETHTYP,
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OUT_VTAG0,
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OUT_VTAG1,
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OUT_ITAG0,
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OUT_ITAG1, /*10 */
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OUT_ITAG2,
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OUT_ITAG3,
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OUT_IP0,
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OUT_IP1,
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OUT_IP2,
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OUT_IP3,
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OUT_SIP0,
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OUT_SIP1,
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OUT_SIP2,
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OUT_SIP3, /*20*/
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OUT_SIP4,
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OUT_SIP5,
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OUT_SIP6,
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OUT_SIP7,
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OUT_DIP0,
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OUT_DIP1,
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OUT_DIP2,
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OUT_DIP3,
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OUT_DIP4,
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OUT_DIP5, /*30*/
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OUT_DIP6,
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OUT_DIP7,
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OUT_SESID,
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OUT_PROT,
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OUT_APP0,
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OUT_APP1,
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OUT_IGMP0,
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OUT_IGMP1,
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OUT_IPOFF, /*39*/
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OUT_NONE = 63,
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};
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/* parser's microcode length type */
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#define INSTR 0
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#define IPV6 1
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#define LENACCU 2
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/* parser's microcode flag type */
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enum {
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FLAG_ITAG = 0,
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FLAG_VLAN,
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FLAG_SNAP,
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FLAG_PPPOE,
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FLAG_IPV6,
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FLAG_IPV6FL,
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FLAG_IPV4,
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FLAG_IGMP,
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FLAG_TU,
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FLAG_HOP,
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FLAG_NN1, /*10 */
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FLAG_NN2,
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FLAG_END,
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FLAG_NO, /*13*/
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};
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struct gswip_pce_microcode {
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u16 val_3;
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u16 val_2;
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u16 val_1;
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u16 val_0;
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};
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#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
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{ val, msk, ((ns) << 10 | (out) << 4 | (len) >> 1),\
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((len) & 1) << 15 | (type) << 13 | (flags) << 9 | (ipv4_len) << 8 }
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static const struct gswip_pce_microcode gswip_pce_microcode[] = {
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/* value mask ns fields L type flags ipv4_len */
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MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
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MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
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MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
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MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
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MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 40, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0600, 0x0600, 40, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0300, 0xFF00, 41, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
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MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 40, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
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MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 40, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
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MC_ENTRY(0x1100, 0xFF00, 39, OUT_PROT, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0600, 0xFF00, 39, OUT_PROT, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
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MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
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MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
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MC_ENTRY(0x0000, 0x0000, 39, OUT_PROT, 1, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x00E0, 35, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 40, OUT_NONE, 0, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
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MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
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MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
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MC_ENTRY(0x0000, 0x0000, 40, OUT_PROT, 1, IPV6, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 40, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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MC_ENTRY(0x0000, 0x0000, 41, OUT_NONE, 0, INSTR, FLAG_END, 0),
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};
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