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drm/i915: Fix a buch of kerneldoc warnings
Just a bunch of stale kerneldocs generating warnings when building the docs. Mostly function parameters so not very useful but still. v2: Tidy. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1464958937-23344-1-git-send-email-tvrtko.ursulin@linux.intel.com
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@ -737,7 +737,7 @@ static void fini_hash_table(struct intel_engine_cs *engine)
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/**
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* i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
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* @ring: the ringbuffer to initialize
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* @engine: the engine to initialize
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*
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* Optionally initializes fields related to batch buffer command parsing in the
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* struct intel_engine_cs based on whether the platform requires software
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@ -830,7 +830,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
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/**
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* i915_cmd_parser_fini_ring() - clean up cmd parser related fields
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* @ring: the ringbuffer to clean up
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* @engine: the engine to clean up
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*
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* Releases any resources related to command parsing that may have been
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* initialized for the specified ring.
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@ -1024,7 +1024,7 @@ unpin_src:
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/**
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* i915_needs_cmd_parser() - should a given ring use software command parsing?
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* @ring: the ring in question
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* @engine: the engine in question
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*
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* Only certain platforms require software batch buffer command parsing, and
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* only when enabled via module parameter.
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@ -1176,7 +1176,7 @@ static bool check_cmd(const struct intel_engine_cs *engine,
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/**
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* i915_parse_cmds() - parse a submitted batch buffer for privilege violations
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* @ring: the ring on which the batch is to execute
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* @engine: the engine on which the batch is to execute
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* @batch_obj: the batch buffer in question
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* @shadow_batch_obj: copy of the batch buffer in question
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* @batch_start_offset: byte offset in the batch at which execution starts
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@ -1281,6 +1281,7 @@ int i915_parse_cmds(struct intel_engine_cs *engine,
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/**
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* i915_cmd_parser_get_version() - get the cmd parser version number
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* @dev_priv: i915 device private
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*
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* The cmd parser maintains a simple increasing integer version number suitable
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* for passing to userspace clients to determine what operations are permitted.
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@ -409,6 +409,9 @@ i915_gem_dumb_create(struct drm_file *file,
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/**
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* Creates a new mm object and returns a handle to it.
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* @dev: drm device pointer
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* @data: ioctl data blob
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* @file: drm file pointer
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*/
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int
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i915_gem_create_ioctl(struct drm_device *dev, void *data,
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@ -672,6 +675,9 @@ out:
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/**
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* Reads data from the object referenced by handle.
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* @dev: drm device pointer
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* @data: ioctl data blob
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* @file: drm file pointer
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*
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* On error, the contents of *data are undefined.
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*/
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@ -753,6 +759,10 @@ fast_user_write(struct io_mapping *mapping,
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/**
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* This is the fast pwrite path, where we copy the data directly from the
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* user into the GTT, uncached.
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* @dev: drm device pointer
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* @obj: i915 gem object
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* @args: pwrite arguments structure
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* @file: drm file pointer
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*/
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static int
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i915_gem_gtt_pwrite_fast(struct drm_device *dev,
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@ -1016,6 +1026,9 @@ out:
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/**
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* Writes data to the object referenced by handle.
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* @dev: drm device
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* @data: ioctl data blob
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* @file: drm file
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*
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* On error, the contents of the buffer that were to be modified are undefined.
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*/
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@ -1213,6 +1226,7 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
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* @req: duh!
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* @interruptible: do an interruptible wait (normally yes)
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* @timeout: in - how long to wait (NULL forever); out - how much time remaining
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* @rps: RPS client
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*
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* Note: It is of utmost importance that the passed in seqno and reset_counter
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* values have been read by the caller in an smp safe manner. Where read-side
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@ -1446,6 +1460,7 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
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/**
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* Waits for a request to be signaled, and cleans up the
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* request and object lists appropriately for that event.
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* @req: request to wait on
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*/
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int
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i915_wait_request(struct drm_i915_gem_request *req)
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@ -1472,6 +1487,8 @@ i915_wait_request(struct drm_i915_gem_request *req)
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/**
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* Ensures that all rendering to the object has completed and the object is
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* safe to unbind from the GTT or access from the CPU.
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* @obj: i915 gem object
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* @readonly: waiting for read access or write
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*/
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int
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i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
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@ -1589,6 +1606,9 @@ static struct intel_rps_client *to_rps_client(struct drm_file *file)
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/**
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* Called when user space prepares to use an object with the CPU, either
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* through the mmap ioctl's mapping or a GTT mapping.
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* @dev: drm device
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* @data: ioctl data blob
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* @file: drm file
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*/
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int
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i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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@ -1652,6 +1672,9 @@ unlock:
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/**
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* Called when user space has done writes to this buffer
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* @dev: drm device
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* @data: ioctl data blob
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* @file: drm file
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*/
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int
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i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
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@ -1682,8 +1705,11 @@ unlock:
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}
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/**
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* Maps the contents of an object, returning the address it is mapped
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* into.
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* i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
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* it is mapped to.
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* @dev: drm device
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* @data: ioctl data blob
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* @file: drm file
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*
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* While the mapping holds a reference on the contents of the object, it doesn't
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* imply a ref on the object itself.
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@ -2001,7 +2027,10 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
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/**
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* i915_gem_get_gtt_alignment - return required GTT alignment for an object
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* @obj: object to check
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* @dev: drm device
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* @size: object size
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* @tiling_mode: tiling mode
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* @fenced: is fenced alignemned required or not
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*
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* Return the required GTT alignment for an object, taking into account
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* potential fence register mapping.
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@ -2951,6 +2980,7 @@ void i915_gem_reset(struct drm_device *dev)
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/**
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* This function clears the request list as sequence numbers are passed.
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* @engine: engine to retire requests on
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*/
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void
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i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
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@ -3074,6 +3104,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
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* Ensures that an object will eventually get non-busy by flushing any required
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* write domains, emitting any outstanding lazy request and retiring and
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* completed requests.
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* @obj: object to flush
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*/
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static int
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i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
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@ -3099,7 +3130,9 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
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/**
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* i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
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* @DRM_IOCTL_ARGS: standard ioctl arguments
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* @dev: drm device pointer
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* @data: ioctl data blob
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* @file: drm file pointer
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*
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* Returns 0 if successful, else an error is returned with the remaining time in
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* the timeout parameter.
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@ -3489,6 +3522,11 @@ static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
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/**
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* Finds free space in the GTT aperture and binds the object or a view of it
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* there.
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* @obj: object to bind
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* @vm: address space to bind into
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* @ggtt_view: global gtt view if applicable
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* @alignment: requested alignment
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* @flags: mask of PIN_* flags to use
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*/
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static struct i915_vma *
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i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
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@ -3746,6 +3784,8 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
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/**
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* Moves a single object to the GTT read, and possibly write domain.
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* @obj: object to act on
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* @write: ask for write access or read only
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*
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* This function returns when the move is complete, including waiting on
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* flushes to occur.
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@ -3817,6 +3857,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
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/**
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* Changes the cache-level of an object across all VMA.
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* @obj: object to act on
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* @cache_level: new cache level to set for the object
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*
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* After this function returns, the object will be in the new cache-level
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* across all GTT and the contents of the backing storage will be coherent,
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@ -4098,6 +4140,8 @@ i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
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/**
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* Moves a single object to the CPU read, and possibly write domain.
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* @obj: object to act on
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* @write: requesting write or read-only access
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*
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* This function returns when the move is complete, including waiting on
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* flushes to occur.
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@ -588,7 +588,7 @@ i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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/**
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* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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* @dev: drm device
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* @dev_priv: i915 device private
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*/
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static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
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{
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@ -2517,7 +2517,7 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
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/**
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* i915_reset_and_wakeup - do process context error handling work
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* @dev: drm device
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* @dev_priv: i915 device private
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*
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* Fire an error uevent so userspace can see that a hang or error
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* was detected.
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@ -2674,13 +2674,14 @@ static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
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/**
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* i915_handle_error - handle a gpu error
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* @dev: drm device
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* @dev_priv: i915 device private
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* @engine_mask: mask representing engines that are hung
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* Do some basic checking of register state at error time and
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* dump it to the syslog. Also call i915_capture_error_state() to make
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* sure we get a record and make it available in debugfs. Fire a uevent
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* so userspace knows something bad happened (should trigger collection
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* of a ring dump etc.).
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* @fmt: Error message format string
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*/
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void i915_handle_error(struct drm_i915_private *dev_priv,
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u32 engine_mask,
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@ -53,7 +53,7 @@
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/**
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* i915_check_vgpu - detect virtual GPU
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* @dev: drm device *
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* @dev_priv: i915 device private
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*
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* This function is called at the initialization stage, to detect whether
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* running on a vGPU.
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@ -135,7 +135,7 @@ static int vgt_balloon_space(struct drm_mm *mm,
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/**
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* intel_vgt_balloon - balloon out reserved graphics address trunks
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* @dev_priv: i915 device
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* @dev: drm device
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*
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* This function is called at the initialization stage, to balloon out the
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* graphic address space allocated to other vGPUs, by marking these spaces as
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@ -238,7 +238,7 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx,
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/**
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* intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
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* @dev: DRM device.
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* @dev_priv: i915 device private
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* @enable_execlists: value of i915.enable_execlists module parameter.
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*
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* Only certain platforms support Execlists (the prerequisites being
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@ -516,7 +516,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
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/**
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* intel_lrc_irq_handler() - handle Context Switch interrupts
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* @engine: Engine Command Streamer to handle.
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* @data: tasklet handler passed in unsigned long
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*
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* Check the unread Context Status Buffers and manage the submission of new
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* contexts to the ELSP accordingly.
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@ -786,15 +786,9 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
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/**
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* execlists_submission() - submit a batchbuffer for execution, Execlists style
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* @dev: DRM device.
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* @file: DRM file.
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* @ring: Engine Command Streamer to submit to.
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* @ctx: Context to employ for this submission.
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* @params: execbuffer call parameters.
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* @args: execbuffer call arguments.
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* @vmas: list of vmas.
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* @batch_obj: the batchbuffer to submit.
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* @exec_start: batchbuffer start virtual address pointer.
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* @dispatch_flags: translated execbuffer call flags.
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*
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* This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
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* away the submission details of the execbuffer ioctl call.
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@ -1138,7 +1132,7 @@ static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
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/**
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* gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
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*
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* @ring: only applicable for RCS
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* @engine: only applicable for RCS
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* @wa_ctx: structure representing wa_ctx
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* offset: specifies start of the batch, should be cache-aligned. This is updated
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* with the offset value received as input.
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@ -1212,7 +1206,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
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/**
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* gen8_init_perctx_bb() - initialize per ctx batch with WA
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*
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* @ring: only applicable for RCS
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* @engine: only applicable for RCS
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* @wa_ctx: structure representing wa_ctx
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* offset: specifies start of the batch, should be cache-aligned.
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* size: size of the batch in DWORDS but HW expects in terms of cachelines
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@ -1860,7 +1854,7 @@ static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
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/**
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* intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
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*
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* @ring: Engine Command Streamer.
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* @engine: Engine Command Streamer.
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*
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*/
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
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@ -2413,7 +2407,7 @@ populate_lr_context(struct i915_gem_context *ctx,
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/**
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* intel_lr_context_size() - return the size of the context for an engine
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* @ring: which engine to find the context size for
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* @engine: which engine to find the context size for
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*
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* Each engine may require a different amount of space for a context image,
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* so when allocating (or copying) an image, this function can be used to
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@ -2448,6 +2448,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
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/**
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* intel_power_domains_init_hw - initialize hardware power domain state
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* @dev_priv: i915 device instance
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* @resume: Called from resume code paths or not
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*
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* This function initializes the hardware power domain state and enables all
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* power domains using intel_display_set_init_power().
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