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ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled

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This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible
cache data corruption with hit-under-miss enabled). It sets the
undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2011-08-15 11:04:41 +01:00 committed by Russell King
parent 43c734be55
commit 145e10e173
2 changed files with 28 additions and 0 deletions
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12
arch/arm/Kconfig
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@ -1271,6 +1271,18 @@ config ARM_ERRATA_754327
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
config ARM_ERRATA_364296
bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
depends on CPU_V6 && !SMP
help
This options enables the workaround for the 364296 ARM1136
r0p2 erratum (possible cache data corruption with
hit-under-miss enabled). It sets the undocumented bit 31 in
the auxiliary control register and the FI bit in the control
register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode. ARM11MPCore
is not affected.
endmenu
source "arch/arm/common/Kconfig"

16
arch/arm/mm/proc-v6.S
View File

@ -223,6 +223,22 @@ __v6_setup:
mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, r0, r5 @ clear bits them
orr r0, r0, r6 @ set them
#ifdef CONFIG_ARM_ERRATA_364296
/*
* Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
* corruption with hit-under-miss enabled). The conditional code below
* (setting the undocumented bit 31 in the auxiliary control register
* and the FI bit in the control register) disables hit-under-miss
* without putting the processor into full low interrupt latency mode.
*/
ldr r6, =0x4107b362 @ id for ARM1136 r0p2
mrc p15, 0, r5, c0, c0, 0 @ get processor id
teq r5, r6 @ check for the faulty core
mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
#endif
mov pc, lr @ return to head.S:__ret
/*