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xen/pci: Use APIC directly when APIC virtualization hardware is available
When hardware supports APIC/x2APIC virtualization we don't need to use pirqs for MSI handling and instead use APIC since most APIC accesses (MMIO or MSR) will now be processed without VMEXITs. As an example, netperf on the original code produces this profile (collected wih 'xentrace -e 0x0008ffff -T 5'): 342 cpu_change 260 CPUID 34638 HLT 64067 INJ_VIRQ 28374 INTR 82733 INTR_WINDOW 10 NPF 24337 TRAP 370610 vlapic_accept_pic_intr 307528 VMENTRY 307527 VMEXIT 140998 VMMCALL 127 wrap_buffer After applying this patch the same test shows 230 cpu_change 260 CPUID 36542 HLT 174 INJ_VIRQ 27250 INTR 222 INTR_WINDOW 20 NPF 24999 TRAP 381812 vlapic_accept_pic_intr 166480 VMENTRY 166479 VMEXIT 77208 VMMCALL 81 wrap_buffer ApacheBench results (ab -n 10000 -c 200) improve by about 10% Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
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arch/x86/include/asm/xen/cpuid.h
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arch/x86/include/asm/xen/cpuid.h
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/******************************************************************************
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* arch-x86/cpuid.h
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*
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* CPUID interface to Xen.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Copyright (c) 2007 Citrix Systems, Inc.
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*
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* Authors:
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* Keir Fraser <keir@xen.org>
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*/
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#ifndef __XEN_PUBLIC_ARCH_X86_CPUID_H__
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#define __XEN_PUBLIC_ARCH_X86_CPUID_H__
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/*
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* For compatibility with other hypervisor interfaces, the Xen cpuid leaves
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* can be found at the first otherwise unused 0x100 aligned boundary starting
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* from 0x40000000.
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*
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* e.g If viridian extensions are enabled for an HVM domain, the Xen cpuid
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* leaves will start at 0x40000100
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*/
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#define XEN_CPUID_FIRST_LEAF 0x40000000
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#define XEN_CPUID_LEAF(i) (XEN_CPUID_FIRST_LEAF + (i))
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/*
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* Leaf 1 (0x40000x00)
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* EAX: Largest Xen-information leaf. All leaves up to an including @EAX
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* are supported by the Xen host.
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* EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification
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* of a Xen host.
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*/
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#define XEN_CPUID_SIGNATURE_EBX 0x566e6558 /* "XenV" */
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#define XEN_CPUID_SIGNATURE_ECX 0x65584d4d /* "MMXe" */
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#define XEN_CPUID_SIGNATURE_EDX 0x4d4d566e /* "nVMM" */
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/*
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* Leaf 2 (0x40000x01)
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* EAX[31:16]: Xen major version.
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* EAX[15: 0]: Xen minor version.
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* EBX-EDX: Reserved (currently all zeroes).
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*/
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/*
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* Leaf 3 (0x40000x02)
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* EAX: Number of hypercall transfer pages. This register is always guaranteed
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* to specify one hypercall page.
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* EBX: Base address of Xen-specific MSRs.
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* ECX: Features 1. Unused bits are set to zero.
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* EDX: Features 2. Unused bits are set to zero.
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*/
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/* Does the host support MMU_PT_UPDATE_PRESERVE_AD for this guest? */
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#define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
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#define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD (1u<<0)
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/*
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* Leaf 5 (0x40000x04)
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* HVM-specific features
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*/
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/* EAX Features */
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/* Virtualized APIC registers */
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#define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0)
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/* Virtualized x2APIC accesses */
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#define XEN_HVM_CPUID_X2APIC_VIRT (1u << 1)
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/* Memory mapped from other domains has valid IOMMU entries */
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#define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2)
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#define XEN_CPUID_MAX_NUM_LEAVES 4
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#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
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@ -23,6 +23,8 @@
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#include <xen/features.h>
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#include <xen/events.h>
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#include <asm/xen/pci.h>
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#include <asm/xen/cpuid.h>
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#include <asm/apic.h>
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#include <asm/i8259.h>
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static int xen_pcifront_enable_irq(struct pci_dev *dev)
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@ -434,6 +436,20 @@ int __init pci_xen_init(void)
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#ifdef CONFIG_PCI_MSI
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void __init xen_msi_init(void)
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{
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if (!disable_apic) {
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/*
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* If hardware supports (x2)APIC virtualization (as indicated
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* by hypervisor's leaf 4) then we don't need to use pirqs/
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* event channels for MSI handling and instead use regular
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* APIC processing
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*/
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uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
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if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
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((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && cpu_has_apic))
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return;
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}
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x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
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x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
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}
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