mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 23:14:31 +08:00
Samsung DTS ARM64 changes for v6.9
Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding
support for:
1. Multi Core Timer (MCT) clocksource.
2. Several clock controllers (DTS and DT bindings) and use new clocks in
several other device nodes.
3. More serial-interface instances: USI8 and USI12 with I2C.
Exynos850:
1. SPI and DMA controllers (PL330).
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmXSSV8QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1xrKD/sHdEhe+Ry7KJs4TanYYHDJUq7I1x5K7xYd
M1A1TAsdU+YegESN9JSxYO+p/zCmjvlS3yeoWSEKFokRUDxNQNZeCVN2tGeRQvzK
uZyj1D6n31taDAA6zVneeZ7Xn3C5Zh0eNMy3+j6ZhqeTyW85ECdxEN+KwbrQ324r
00+9FUH42RYNqXF8pxAMmWEEwtzdwzeQ+dU7RkcL4LZaY3HOsesX0ZxHzprVpzOo
vQYtwoLcQ1Q4sEPOYNtDflUv33y8vfX04BUnXliNHBmgHT7XGRk35vfAnDjGEmBr
UiDkLFs1xlaTjJCOSqmto8cQToRvX58DSEBBtGO4jPe/F1ZxYTyYymSB1ygDlz+a
hSRRdlS5MeeV2kc1yO1uXMAI5UfNM1zXbV3fsuWjquXki/kdl7l5uj/3/UL8Jgvf
j9G6MuNFCUcho6uXtgEf9G5FsEIW6yBtoCoSX/izIM/5o3wUy0u9DT6hnjIjnemN
L0dahtgyrSPDKAh9yoAWhlkcs5em0LN8bPi9tLCuVAEhmcgiqlHyK9tFzwQkIJGa
7Eq9jx2BDFJADCPXD9jWDhsNyHMZZOwK41TuSFH6i3EgLlwpUfN1TbGfUrgw5iAx
hT7t0ecaN8xJYOb7xI6f8fO0qDYHqcxSon5b1iKr2w+7t4XLEEEMrq6B0uLsCZib
PcBFBYsm0A==
=Qz5k
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgnmwACgkQYKtH/8kJ
Uidu5A//Q7tpYouP0tKMESalkZoKYx32hCMs7ldp1TRZ11M2RxWKvxdayMiW7WNG
8/YMOJ74VyFjVdQp7uO9V3d2brHjX4SzUucD+UX2cHSdg7ccfMuVnUo6xEtKvxX9
OQPZwZ8iG9jQmi5MtxNqdP8c+7lk+SScVFzdZ0rJWL/OBGdTtFFct9lrXZg8Wctg
dXBiiqBiZnBWQIvkGm5zbdM+u6/8lQuISa7xSgJfIiTEqtgR6Y5pByGpTrGVeFMW
sCdkVFOnz4v5whNkkRPxZy1IJhkW2OqSooReIuPqo0zqcEnFEEKQfoifZWarvXqr
wpyk6prVDi8698ebUTacyHKoaMtraXC7AVEQiEobjR136ZdTBR+Eze4fCzQJQTs4
cAcjD49qbJJPgarM8z/zU+VUa4PQfN1x2TRrvx/8BdqXd0nACxLWrHuRwgtKgfIK
1Ytycw3FnNUrBZ1mARWX+LmZzypzcPJ5bbn6BUxdV+w6m3lwbos3SoyFzLyO3k5W
r6dr++vNBWLJYHkia6i0Ft/YnbUMmRe2UrfibFvaS8LJSCxQkobfDTWpvFeA8k8q
cqZWc+bBQ3CZxat7DD3L4aFBwAnlFFokoKf8M6JVBFfyxpiikZFBfK+xcD7uR8oV
SzbyJY2g44xoGEbVAub7fe4QH6xcgpj3mSJDnHqkzRks8jf7Jcs=
=KV1f
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.9
Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding
support for:
1. Multi Core Timer (MCT) clocksource.
2. Several clock controllers (DTS and DT bindings) and use new clocks in
several other device nodes.
3. More serial-interface instances: USI8 and USI12 with I2C.
Exynos850:
1. SPI and DMA controllers (PL330).
* tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: Add fifosize for UART in Device Tree
arm64: dts: exynos: gs101: minor whitespace cleanup
arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
arm64: dts: exynos: gs101: define USI12 with I2C configuration
arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
arm64: dts: exynos: Add SPI nodes for Exynos850
arm64: dts: exynos: Add PDMA node for Exynos850
arm64: dts: exynos: gs101: use correct clocks for usi_uart
arm64: dts: exynos: gs101: use correct clocks for usi8
arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
arm64: dts: exynos: gs101: define USI8 with I2C configuration
arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
arm64: dts: exynos: gs101: remove reg-io-width from serial
arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
dt-bindings: clock: exynos850: Add PDMA clocks
dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit
Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
1422eb8585
@ -30,14 +30,16 @@ properties:
|
||||
- google,gs101-cmu-top
|
||||
- google,gs101-cmu-apm
|
||||
- google,gs101-cmu-misc
|
||||
- google,gs101-cmu-peric0
|
||||
- google,gs101-cmu-peric1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
maxItems: 3
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
@ -88,6 +90,28 @@ allOf:
|
||||
- const: bus
|
||||
- const: sss
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-cmu-peric0
|
||||
- google,gs101-cmu-peric1
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24.576 MHz)
|
||||
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
|
||||
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: ip
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -184,6 +184,16 @@
|
||||
clock-names = "fin_pll", "mct";
|
||||
};
|
||||
|
||||
pdma0: dma-controller@120c0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x120c0000 0x1000>;
|
||||
clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@12a01000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@ -728,6 +738,24 @@
|
||||
<&cmu_peri CLK_GOUT_SPI0_IPCLK>;
|
||||
clock-names = "pclk", "ipclk";
|
||||
status = "disabled";
|
||||
|
||||
spi_0: spi@13940000 {
|
||||
compatible = "samsung,exynos850-spi";
|
||||
reg = <0x13940000 0x30>;
|
||||
clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
|
||||
<&cmu_peri CLK_GOUT_SPI0_IPCLK>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
dmas = <&pdma0 5>, <&pdma0 4>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
num-cs = <1>;
|
||||
samsung,spi-src-clk = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usi_cmgp0: usi@11d000c0 {
|
||||
@ -769,6 +797,24 @@
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_1: spi@11d00000 {
|
||||
compatible = "samsung,exynos850-spi";
|
||||
reg = <0x11d00000 0x30>;
|
||||
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
|
||||
<&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
dmas = <&pdma0 12>, <&pdma0 13>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
num-cs = <1>;
|
||||
samsung,spi-src-clk = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usi_cmgp1: usi@11d200c0 {
|
||||
@ -810,6 +856,24 @@
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_2: spi@11d20000 {
|
||||
compatible = "samsung,exynos850-spi";
|
||||
reg = <0x11d20000 0x30>;
|
||||
clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
|
||||
<&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
dmas = <&pdma0 14>, <&pdma0 15>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-0 = <&spi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
num-cs = <1>;
|
||||
samsung,spi-src-clk = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -63,6 +63,20 @@
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
&hsi2c_8 {
|
||||
status = "okay";
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&hsi2c_12 {
|
||||
status = "okay";
|
||||
/* TODO: add the devices once drivers exist */
|
||||
};
|
||||
|
||||
&pinctrl_far_alive {
|
||||
key_voldown: key-voldown-pins {
|
||||
samsung,pins = "gpa7-3";
|
||||
@ -99,6 +113,16 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usi8 {
|
||||
samsung,mode = <USI_V2_I2C>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usi12 {
|
||||
samsung,mode = <USI_V2_I2C>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog_cl0 {
|
||||
timeout-sec = <30>;
|
||||
status = "okay";
|
||||
|
||||
@ -251,7 +251,7 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcie0_clkreq: pcie0-clkreq-pins{
|
||||
pcie0_clkreq: pcie0-clkreq-pins {
|
||||
samsung,pins = "gph0-1";
|
||||
samsung,pin-function = <GS101_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <GS101_PIN_PULL_UP>;
|
||||
|
||||
@ -73,7 +73,7 @@
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <250>;
|
||||
dynamic-power-coefficient = <70>;
|
||||
};
|
||||
@ -83,7 +83,7 @@
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <250>;
|
||||
dynamic-power-coefficient = <70>;
|
||||
};
|
||||
@ -93,7 +93,7 @@
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0200>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <250>;
|
||||
dynamic-power-coefficient = <70>;
|
||||
};
|
||||
@ -103,7 +103,7 @@
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0300>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
cpu-idle-states = <&ANANKE_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <250>;
|
||||
dynamic-power-coefficient = <70>;
|
||||
};
|
||||
@ -113,7 +113,7 @@
|
||||
compatible = "arm,cortex-a76";
|
||||
reg = <0x0400>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&ENYO_CPU_SLEEP>;
|
||||
cpu-idle-states = <&ENYO_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <620>;
|
||||
dynamic-power-coefficient = <284>;
|
||||
};
|
||||
@ -123,7 +123,7 @@
|
||||
compatible = "arm,cortex-a76";
|
||||
reg = <0x0500>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&ENYO_CPU_SLEEP>;
|
||||
cpu-idle-states = <&ENYO_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <620>;
|
||||
dynamic-power-coefficient = <284>;
|
||||
};
|
||||
@ -133,7 +133,7 @@
|
||||
compatible = "arm,cortex-x1";
|
||||
reg = <0x0600>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&HERA_CPU_SLEEP>;
|
||||
cpu-idle-states = <&HERA_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <650>;
|
||||
};
|
||||
@ -143,7 +143,7 @@
|
||||
compatible = "arm,cortex-x1";
|
||||
reg = <0x0700>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&HERA_CPU_SLEEP>;
|
||||
cpu-idle-states = <&HERA_CPU_SLEEP>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <650>;
|
||||
};
|
||||
@ -180,14 +180,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
/* TODO replace with CCF clock */
|
||||
dummy_clk: clock-3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12345>;
|
||||
clock-output-names = "pclk";
|
||||
};
|
||||
|
||||
/* ect node is required to be present by bootloader */
|
||||
ect {
|
||||
};
|
||||
@ -292,6 +284,26 @@
|
||||
clock-names = "bus", "sss";
|
||||
};
|
||||
|
||||
timer@10050000 {
|
||||
compatible = "google,gs101-mct",
|
||||
"samsung,exynos4210-mct";
|
||||
reg = <0x10050000 0x800>;
|
||||
interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
|
||||
clock-names = "fin_pll", "mct";
|
||||
};
|
||||
|
||||
watchdog_cl0: watchdog@10060000 {
|
||||
compatible = "google,gs101-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
@ -339,9 +351,20 @@
|
||||
};
|
||||
};
|
||||
|
||||
cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "google,gs101-cmu-peric0";
|
||||
reg = <0x10800000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ext_24_5m>,
|
||||
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
|
||||
clock-names = "oscclk", "bus", "ip";
|
||||
};
|
||||
|
||||
sysreg_peric0: syscon@10820000 {
|
||||
compatible = "google,gs101-peric0-sysreg", "syscon";
|
||||
reg = <0x10820000 0x10000>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>;
|
||||
};
|
||||
|
||||
pinctrl_peric0: pinctrl@10840000 {
|
||||
@ -350,6 +373,35 @@
|
||||
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
usi8: usi@109700c0 {
|
||||
compatible = "google,gs101-usi",
|
||||
"samsung,exynos850-usi";
|
||||
reg = <0x109700c0 0x20>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>,
|
||||
<&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
|
||||
clock-names = "pclk", "ipclk";
|
||||
samsung,sysreg = <&sysreg_peric0 0x101c>;
|
||||
status = "disabled";
|
||||
|
||||
hsi2c_8: i2c@10970000 {
|
||||
compatible = "google,gs101-hsi2c",
|
||||
"samsung,exynosautov9-hsi2c";
|
||||
reg = <0x10970000 0xc0>;
|
||||
interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hsi2c8_bus>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>,
|
||||
<&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>;
|
||||
clock-names = "hsi2c", "hsi2c_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usi_uart: usi@10a000c0 {
|
||||
compatible = "google,gs101-usi",
|
||||
"samsung,exynos850-usi";
|
||||
@ -357,7 +409,8 @@
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&dummy_clk>, <&dummy_clk>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,
|
||||
<&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
|
||||
clock-names = "pclk", "ipclk";
|
||||
samsung,sysreg = <&sysreg_peric0 0x1020>;
|
||||
samsung,mode = <USI_V2_UART>;
|
||||
@ -366,19 +419,30 @@
|
||||
serial_0: serial@10a00000 {
|
||||
compatible = "google,gs101-uart";
|
||||
reg = <0x10a00000 0xc0>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 634
|
||||
IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&dummy_clk 0>, <&dummy_clk 0>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,
|
||||
<&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
samsung,uart-fifosize = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cmu_peric1: clock-controller@10c00000 {
|
||||
compatible = "google,gs101-cmu-peric1";
|
||||
reg = <0x10c00000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ext_24_5m>,
|
||||
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
|
||||
clock-names = "oscclk", "bus", "ip";
|
||||
};
|
||||
|
||||
sysreg_peric1: syscon@10c20000 {
|
||||
compatible = "google,gs101-peric1-sysreg", "syscon";
|
||||
reg = <0x10c20000 0x10000>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>;
|
||||
};
|
||||
|
||||
pinctrl_peric1: pinctrl@10c40000 {
|
||||
@ -387,6 +451,35 @@
|
||||
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
usi12: usi@10d500c0 {
|
||||
compatible = "google,gs101-usi",
|
||||
"samsung,exynos850-usi";
|
||||
reg = <0x10d500c0 0x20>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>,
|
||||
<&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>;
|
||||
clock-names = "pclk", "ipclk";
|
||||
samsung,sysreg = <&sysreg_peric1 0x1010>;
|
||||
status = "disabled";
|
||||
|
||||
hsi2c_12: i2c@10d50000 {
|
||||
compatible = "google,gs101-hsi2c",
|
||||
"samsung,exynosautov9-hsi2c";
|
||||
reg = <0x10d50000 0xc0>;
|
||||
interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&hsi2c12_bus>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>,
|
||||
<&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>;
|
||||
clock-names = "hsi2c", "hsi2c_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_hsi1: pinctrl@11840000 {
|
||||
compatible = "google,gs101-pinctrl";
|
||||
reg = <0x11840000 0x00001000>;
|
||||
|
||||
@ -601,6 +601,7 @@
|
||||
clocks = <&clock_peric PERIC_PCLK_UART0>,
|
||||
<&clock_peric PERIC_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
samsung,uart-fifosize = <64>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -613,6 +614,7 @@
|
||||
clocks = <&clock_peric PERIC_PCLK_UART1>,
|
||||
<&clock_peric PERIC_SCLK_UART1>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
samsung,uart-fifosize = <64>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -320,6 +320,8 @@
|
||||
#define CLK_GOUT_SSS_PCLK 12
|
||||
#define CLK_GOUT_GPIO_CORE_PCLK 13
|
||||
#define CLK_GOUT_SYSREG_CORE_PCLK 14
|
||||
#define CLK_GOUT_PDMA_CORE_ACLK 15
|
||||
#define CLK_GOUT_SPDMA_CORE_ACLK 16
|
||||
|
||||
/* CMU_DPU */
|
||||
#define CLK_MOUT_DPU_USER 1
|
||||
|
||||
@ -389,4 +389,133 @@
|
||||
#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
|
||||
#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC0_I3C_USER 2
|
||||
#define CLK_MOUT_PERIC0_USI0_UART_USER 3
|
||||
#define CLK_MOUT_PERIC0_USI14_USI_USER 4
|
||||
#define CLK_MOUT_PERIC0_USI1_USI_USER 5
|
||||
#define CLK_MOUT_PERIC0_USI2_USI_USER 6
|
||||
#define CLK_MOUT_PERIC0_USI3_USI_USER 7
|
||||
#define CLK_MOUT_PERIC0_USI4_USI_USER 8
|
||||
#define CLK_MOUT_PERIC0_USI5_USI_USER 9
|
||||
#define CLK_MOUT_PERIC0_USI6_USI_USER 10
|
||||
#define CLK_MOUT_PERIC0_USI7_USI_USER 11
|
||||
#define CLK_MOUT_PERIC0_USI8_USI_USER 12
|
||||
#define CLK_DOUT_PERIC0_I3C 13
|
||||
#define CLK_DOUT_PERIC0_USI0_UART 14
|
||||
#define CLK_DOUT_PERIC0_USI14_USI 15
|
||||
#define CLK_DOUT_PERIC0_USI1_USI 16
|
||||
#define CLK_DOUT_PERIC0_USI2_USI 17
|
||||
#define CLK_DOUT_PERIC0_USI3_USI 18
|
||||
#define CLK_DOUT_PERIC0_USI4_USI 19
|
||||
#define CLK_DOUT_PERIC0_USI5_USI 20
|
||||
#define CLK_DOUT_PERIC0_USI6_USI 21
|
||||
#define CLK_DOUT_PERIC0_USI7_USI 22
|
||||
#define CLK_DOUT_PERIC0_USI8_USI 23
|
||||
#define CLK_GOUT_PERIC0_IP 24
|
||||
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26
|
||||
#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27
|
||||
#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28
|
||||
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29
|
||||
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65
|
||||
#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77
|
||||
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
|
||||
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC1_I3C_USER 2
|
||||
#define CLK_MOUT_PERIC1_USI0_USI_USER 3
|
||||
#define CLK_MOUT_PERIC1_USI10_USI_USER 4
|
||||
#define CLK_MOUT_PERIC1_USI11_USI_USER 5
|
||||
#define CLK_MOUT_PERIC1_USI12_USI_USER 6
|
||||
#define CLK_MOUT_PERIC1_USI13_USI_USER 7
|
||||
#define CLK_MOUT_PERIC1_USI9_USI_USER 8
|
||||
#define CLK_DOUT_PERIC1_I3C 9
|
||||
#define CLK_DOUT_PERIC1_USI0_USI 10
|
||||
#define CLK_DOUT_PERIC1_USI10_USI 11
|
||||
#define CLK_DOUT_PERIC1_USI11_USI 12
|
||||
#define CLK_DOUT_PERIC1_USI12_USI 13
|
||||
#define CLK_DOUT_PERIC1_USI13_USI 14
|
||||
#define CLK_DOUT_PERIC1_USI9_USI 15
|
||||
#define CLK_GOUT_PERIC1_IP 16
|
||||
#define CLK_GOUT_PERIC1_PCLK 17
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
|
||||
#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
|
||||
#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
|
||||
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
|
||||
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
|
||||
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
|
||||
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
|
||||
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user