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drm/i915/gt: Rearrange ivb workarounds
Some rcs0 workarounds were being incorrectly applied to the GT, and so we failed to restore the expected register settings after a reset. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210113225144.30810-2-chris@chris-wilson.co.uk
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@ -829,18 +829,6 @@ snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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static void
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ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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/* WaDisableEarlyCull:ivb */
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wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
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/* WaDisablePSDDualDispatchEnable:ivb */
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if (IS_IVB_GT1(i915))
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wa_masked_en(wal,
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GEN7_HALF_SLICE_CHICKEN1,
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
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/* WaDisable_RenderCache_OperationalFlush:ivb */
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wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
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/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
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wa_masked_dis(wal,
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GEN7_COMMON_SLICE_CHICKEN1,
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@ -852,38 +840,6 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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/* WaForceL3Serialization:ivb */
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wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
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/*
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* WaVSThreadDispatchOverride:ivb,vlv
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*
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* This actually overrides the dispatch
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* mode for all thread types.
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*/
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wa_write_clr_set(wal, GEN7_FF_THREAD_MODE,
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GEN7_FF_SCHED_MASK,
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GEN7_FF_TS_SCHED_HW |
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GEN7_FF_VS_SCHED_HW |
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GEN7_FF_DS_SCHED_HW);
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if (0) { /* causes HiZ corruption on ivb:gt1 */
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/* enable HiZ Raw Stall Optimization */
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wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
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}
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/* WaDisable4x2SubspanOptimization:ivb */
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wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal, GEN7_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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}
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static void
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@ -1887,26 +1843,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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wa_masked_dis(wal,
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CACHE_MODE_0_GEN7,
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/* WaDisable_RenderCache_OperationalFlush:hsw */
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RC_OP_FLUSH_ENABLE |
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/* enable HiZ Raw Stall Optimization */
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HIZ_RAW_STALL_OPT_DISABLE);
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/* WaDisable4x2SubspanOptimization:hsw */
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wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal, GEN7_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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}
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if (IS_VALLEYVIEW(i915)) {
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@ -1928,11 +1869,59 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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GEN7_FF_VS_SCHED_HW |
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GEN7_FF_DS_SCHED_HW);
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/* WaDisable_RenderCache_OperationalFlush:vlv */
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/* WaPsdDispatchEnable:vlv */
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/* WaDisablePSDDualDispatchEnable:vlv */
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wa_masked_en(wal,
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GEN7_HALF_SLICE_CHICKEN1,
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GEN7_MAX_PS_THREAD_DEP |
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
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}
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if (IS_IVYBRIDGE(i915)) {
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/* WaDisableEarlyCull:ivb */
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wa_masked_en(wal,
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_3D_CHICKEN3,
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_3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
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if (0) { /* causes HiZ corruption on ivb:gt1 */
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/* enable HiZ Raw Stall Optimization */
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wa_masked_dis(wal,
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CACHE_MODE_0_GEN7,
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HIZ_RAW_STALL_OPT_DISABLE);
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}
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/*
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* WaVSThreadDispatchOverride:ivb,vlv
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*
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* This actually overrides the dispatch
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* mode for all thread types.
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*/
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wa_write_clr_set(wal,
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GEN7_FF_THREAD_MODE,
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GEN7_FF_SCHED_MASK,
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GEN7_FF_TS_SCHED_HW |
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GEN7_FF_VS_SCHED_HW |
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GEN7_FF_DS_SCHED_HW);
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/* WaDisablePSDDualDispatchEnable:ivb */
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if (IS_IVB_GT1(i915))
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wa_masked_en(wal,
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GEN7_HALF_SLICE_CHICKEN1,
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
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}
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if (IS_GEN(i915, 7)) {
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/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
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wa_masked_en(wal,
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GFX_MODE_GEN7,
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GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
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/* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
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wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
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/*
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* BSpec says this must be set, even though
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* WaDisable4x2SubspanOptimization:ivb,hsw
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* WaDisable4x2SubspanOptimization isn't listed for VLV.
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*/
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wa_masked_en(wal,
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@ -1951,21 +1940,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK,
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GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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/* WaPsdDispatchEnable:vlv */
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/* WaDisablePSDDualDispatchEnable:vlv */
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wa_masked_en(wal,
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GEN7_HALF_SLICE_CHICKEN1,
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GEN7_MAX_PS_THREAD_DEP |
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
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}
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if (IS_GEN(i915, 7))
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/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
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wa_masked_en(wal,
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GFX_MODE_GEN7,
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GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
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if (IS_GEN_RANGE(i915, 6, 7))
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/*
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* We need to disable the AsyncFlip performance optimisations in
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