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drm/nouveau/bios/ramcfg: 10_02_40 -> DLLoff

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Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Roy Spliet 2014-10-02 18:01:50 +02:00 committed by Ben Skeggs
parent 7bb6d4428d
commit 13a757dbc7
4 changed files with 4 additions and 4 deletions
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2
drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h
View File

@ -43,7 +43,7 @@ struct nvbios_ramcfg {
unsigned ramcfg_10_02_08:1; unsigned ramcfg_10_02_08:1;
unsigned ramcfg_10_02_10:1; unsigned ramcfg_10_02_10:1;
unsigned ramcfg_10_02_20:1; unsigned ramcfg_10_02_20:1;
unsigned ramcfg_10_02_40:1; unsigned ramcfg_10_DLLoff:1;
unsigned ramcfg_10_03_0f:4; unsigned ramcfg_10_03_0f:4;
unsigned ramcfg_10_05:8; unsigned ramcfg_10_05:8;
unsigned ramcfg_10_06:8; unsigned ramcfg_10_06:8;

2
drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c
View File

@ -162,7 +162,7 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5; p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
p->ramcfg_10_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; p->ramcfg_10_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0; p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;

2
drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c
View File

@ -66,7 +66,7 @@ nouveau_sddr2_calc(struct nouveau_ram *ram)
case 0x10: case 0x10:
CL = ram->next->bios.timing_10_CL; CL = ram->next->bios.timing_10_CL;
WR = ram->next->bios.timing_10_WR; WR = ram->next->bios.timing_10_WR;
DLL = !ram->next->bios.ramcfg_10_02_40; DLL = !ram->next->bios.ramcfg_10_DLLoff;
ODT = ram->next->bios.timing_10_ODT & 3; ODT = ram->next->bios.timing_10_ODT & 3;
break; break;
case 0x20: case 0x20:

2
drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c
View File

@ -80,7 +80,7 @@ nouveau_sddr3_calc(struct nouveau_ram *ram)
CWL = ram->next->bios.timing_10_CWL; CWL = ram->next->bios.timing_10_CWL;
CL = ram->next->bios.timing_10_CL; CL = ram->next->bios.timing_10_CL;
WR = ram->next->bios.timing_10_WR; WR = ram->next->bios.timing_10_WR;
DLL = !ram->next->bios.ramcfg_10_02_40; DLL = !ram->next->bios.ramcfg_10_DLLoff;
ODT = ram->next->bios.timing_10_ODT; ODT = ram->next->bios.timing_10_ODT;
break; break;
case 0x20: case 0x20: