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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
The MSCC bug fix in 'net' had to be slightly adjusted because the register accesses are done slightly differently in net-next. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
13209a8f73
2
.mailmap
2
.mailmap
@ -288,6 +288,8 @@ Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
|
||||
Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
|
||||
Takashi YOSHII <takashi.yoshii.zj@renesas.com>
|
||||
Will Deacon <will@kernel.org> <will.deacon@arm.com>
|
||||
Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de>
|
||||
Wolfram Sang <wsa@kernel.org> <w.sang@pengutronix.de>
|
||||
Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>
|
||||
Yusuke Goda <goda.yusuke@renesas.com>
|
||||
Gustavo Padovan <gustavo@las.ic.unicamp.br>
|
||||
|
@ -10,7 +10,8 @@ Required properties:
|
||||
- compatible :
|
||||
- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
|
||||
- "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
|
||||
- "fsl,fsl,ls1028a-edma" for eDMA used similar to that on Vybrid vf610 SoC
|
||||
- "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
|
||||
LS1028A SoC.
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- reg : Specifies base physical address(s) and size of the eDMA registers.
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||||
The 1st region is eDMA control register's address and size.
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The 2nd and the 3rd regions are programmable channel multiplexing
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||||
|
@ -110,6 +110,9 @@ Ethernet switch connected via MDIO to the host, CPU port wired to eth0:
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||||
#size-cells = <0>;
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||||
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||||
ports {
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||||
#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
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||||
port0@0 {
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||||
reg = <0>;
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||||
label = "lan1";
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||||
|
@ -27,9 +27,8 @@ differences are:
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||||
3. Raw Gadget provides a way to select a UDC device/driver to bind to,
|
||||
while GadgetFS currently binds to the first available UDC.
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||||
|
||||
4. Raw Gadget uses predictable endpoint names (handles) across different
|
||||
UDCs (as long as UDCs have enough endpoints of each required transfer
|
||||
type).
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||||
4. Raw Gadget explicitly exposes information about endpoints addresses and
|
||||
capabilities allowing a user to write UDC-agnostic gadgets.
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||||
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5. Raw Gadget has ioctl-based interface instead of a filesystem-based one.
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@ -50,12 +49,36 @@ The typical usage of Raw Gadget looks like:
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Raw Gadget and react to those depending on what kind of USB device
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||||
needs to be emulated.
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|
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Note, that some UDC drivers have fixed addresses assigned to endpoints, and
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therefore arbitrary endpoint addresses can't be used in the descriptors.
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Nevertheles, Raw Gadget provides a UDC-agnostic way to write USB gadgets.
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Once a USB_RAW_EVENT_CONNECT event is received via USB_RAW_IOCTL_EVENT_FETCH,
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the USB_RAW_IOCTL_EPS_INFO ioctl can be used to find out information about
|
||||
endpoints that the UDC driver has. Based on that information, the user must
|
||||
chose UDC endpoints that will be used for the gadget being emulated, and
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||||
properly assign addresses in endpoint descriptors.
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||||
|
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You can find usage examples (along with a test suite) here:
|
||||
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||||
https://github.com/xairy/raw-gadget
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|
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Internal details
|
||||
~~~~~~~~~~~~~~~~
|
||||
|
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Currently every endpoint read/write ioctl submits a USB request and waits until
|
||||
its completion. This is the desired mode for coverage-guided fuzzing (as we'd
|
||||
like all USB request processing happen during the lifetime of a syscall),
|
||||
and must be kept in the implementation. (This might be slow for real world
|
||||
applications, thus the O_NONBLOCK improvement suggestion below.)
|
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|
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Potential future improvements
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
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- Implement ioctl's for setting/clearing halt status on endpoints.
|
||||
|
||||
- Reporting more events (suspend, resume, etc.) through
|
||||
USB_RAW_IOCTL_EVENT_FETCH.
|
||||
- Report more events (suspend, resume, etc.) through USB_RAW_IOCTL_EVENT_FETCH.
|
||||
|
||||
- Support O_NONBLOCK I/O.
|
||||
|
||||
- Support USB 3 features (accept SS endpoint companion descriptor when
|
||||
enabling endpoints; allow providing stream_id for bulk transfers).
|
||||
|
||||
- Support ISO transfer features (expose frame_number for completed requests).
|
||||
|
20
MAINTAINERS
20
MAINTAINERS
@ -5507,10 +5507,10 @@ F: drivers/gpu/drm/vboxvideo/
|
||||
|
||||
DRM DRIVER FOR VMWARE VIRTUAL GPU
|
||||
M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>
|
||||
M: Thomas Hellstrom <thellstrom@vmware.com>
|
||||
M: Roland Scheidegger <sroland@vmware.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
T: git git://people.freedesktop.org/~thomash/linux
|
||||
T: git git://people.freedesktop.org/~sroland/linux
|
||||
F: drivers/gpu/drm/vmwgfx/
|
||||
F: include/uapi/drm/vmwgfx_drm.h
|
||||
|
||||
@ -7829,7 +7829,7 @@ T: git git://linuxtv.org/media_tree.git
|
||||
F: drivers/media/platform/sti/hva
|
||||
|
||||
HWPOISON MEMORY FAILURE HANDLING
|
||||
M: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com>
|
||||
M: Naoya Horiguchi <naoya.horiguchi@nec.com>
|
||||
L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
F: mm/hwpoison-inject.c
|
||||
@ -7941,7 +7941,7 @@ F: Documentation/i2c/busses/i2c-parport.rst
|
||||
F: drivers/i2c/busses/i2c-parport.c
|
||||
|
||||
I2C SUBSYSTEM
|
||||
M: Wolfram Sang <wsa@the-dreams.de>
|
||||
M: Wolfram Sang <wsa@kernel.org>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
W: https://i2c.wiki.kernel.org/
|
||||
@ -9185,6 +9185,11 @@ L: kexec@lists.infradead.org
|
||||
S: Maintained
|
||||
W: http://lse.sourceforge.net/kdump/
|
||||
F: Documentation/admin-guide/kdump/
|
||||
F: fs/proc/vmcore.c
|
||||
F: include/linux/crash_core.h
|
||||
F: include/linux/crash_dump.h
|
||||
F: include/uapi/linux/vmcore.h
|
||||
F: kernel/crash_*.c
|
||||
|
||||
KEENE FM RADIO TRANSMITTER DRIVER
|
||||
M: Hans Verkuil <hverkuil@xs4all.nl>
|
||||
@ -10662,6 +10667,13 @@ L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/mediatek/
|
||||
|
||||
MEDIATEK I2C CONTROLLER DRIVER
|
||||
M: Qii Wang <qii.wang@mediatek.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
|
||||
F: drivers/i2c/busses/i2c-mt65xx.c
|
||||
|
||||
MEDIATEK JPEG DRIVER
|
||||
M: Rick Chang <rick.chang@mediatek.com>
|
||||
M: Bin Liu <bin.liu@mediatek.com>
|
||||
|
2
Makefile
2
Makefile
@ -2,7 +2,7 @@
|
||||
VERSION = 5
|
||||
PATCHLEVEL = 7
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -65,6 +65,7 @@ CONFIG_DRM_UDL=y
|
||||
CONFIG_DRM_ETNAVIV=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
|
@ -15,12 +15,14 @@
|
||||
|
||||
/* clobbers r5 register */
|
||||
.macro DSP_EARLY_INIT
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
lr r5, [ARC_AUX_DSP_BUILD]
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||||
bmsk r5, r5, 7
|
||||
breq r5, 0, 1f
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||||
mov r5, DSP_CTRL_DISABLED_ALL
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||||
sr r5, [ARC_AUX_DSP_CTRL]
|
||||
1:
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/* clobbers r10, r11 registers pair */
|
||||
|
@ -233,6 +233,8 @@
|
||||
|
||||
#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
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||||
__RESTORE_REGFILE_HARD
|
||||
|
||||
; SP points to PC/STAT32: hw restores them despite NO_AUTOSAVE
|
||||
add sp, sp, SZ_PT_REGS - 8
|
||||
#else
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||||
add sp, sp, PT_r0
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||||
|
@ -3,9 +3,6 @@
|
||||
# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
|
||||
#
|
||||
|
||||
# Pass UTS_MACHINE for user_regset definition
|
||||
CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
|
||||
|
||||
obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
|
||||
obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o
|
||||
obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
|
||||
|
@ -253,7 +253,7 @@ static const struct user_regset arc_regsets[] = {
|
||||
};
|
||||
|
||||
static const struct user_regset_view user_arc_view = {
|
||||
.name = UTS_MACHINE,
|
||||
.name = "arc",
|
||||
.e_machine = EM_ARC_INUSE,
|
||||
.regsets = arc_regsets,
|
||||
.n = ARRAY_SIZE(arc_regsets)
|
||||
|
@ -11,6 +11,7 @@
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_fdt.h>
|
||||
@ -424,12 +425,12 @@ static void arc_chk_core_config(void)
|
||||
if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
|
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panic("Linux built with incorrect DCCM Base address\n");
|
||||
|
||||
if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
|
||||
if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz)
|
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panic("Linux built with incorrect DCCM Size\n");
|
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#endif
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_ICCM
|
||||
if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
|
||||
if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz)
|
||||
panic("Linux built with incorrect ICCM Size\n");
|
||||
#endif
|
||||
|
||||
|
@ -191,10 +191,9 @@ void show_regs(struct pt_regs *regs)
|
||||
if (user_mode(regs))
|
||||
show_faulting_vma(regs->ret); /* faulting code, not data */
|
||||
|
||||
pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\n",
|
||||
regs->event, current->thread.fault_address, regs->ret);
|
||||
|
||||
pr_info("STAT32: 0x%08lx", regs->status32);
|
||||
pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\nSTAT: 0x%08lx",
|
||||
regs->event, current->thread.fault_address, regs->ret,
|
||||
regs->status32);
|
||||
|
||||
#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : ""
|
||||
|
||||
@ -210,11 +209,10 @@ void show_regs(struct pt_regs *regs)
|
||||
(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
|
||||
STS_BIT(regs, DE), STS_BIT(regs, AE));
|
||||
#endif
|
||||
pr_cont(" BTA: 0x%08lx\n", regs->bta);
|
||||
pr_info("BLK: %pS\n SP: 0x%08lx FP: 0x%08lx\n",
|
||||
(void *)regs->blink, regs->sp, regs->fp);
|
||||
pr_cont(" BTA: 0x%08lx\n SP: 0x%08lx FP: 0x%08lx BLK: %pS\n",
|
||||
regs->bta, regs->sp, regs->fp, (void *)regs->blink);
|
||||
pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
|
||||
regs->lp_start, regs->lp_end, regs->lp_count);
|
||||
regs->lp_start, regs->lp_end, regs->lp_count);
|
||||
|
||||
/* print regs->r0 thru regs->r12
|
||||
* Sequential printing was generating horrible code
|
||||
|
@ -1178,11 +1178,9 @@ int arc_unwind(struct unwind_frame_info *frame)
|
||||
#endif
|
||||
|
||||
/* update frame */
|
||||
#ifndef CONFIG_AS_CFI_SIGNAL_FRAME
|
||||
if (frame->call_frame
|
||||
&& !UNW_DEFAULT_RA(state.regs[retAddrReg], state.dataAlign))
|
||||
frame->call_frame = 0;
|
||||
#endif
|
||||
cfa = FRAME_REG(state.cfa.reg, unsigned long) + state.cfa.offs;
|
||||
startLoc = min_t(unsigned long, UNW_SP(frame), cfa);
|
||||
endLoc = max_t(unsigned long, UNW_SP(frame), cfa);
|
||||
|
@ -6,6 +6,7 @@
|
||||
|
||||
menuconfig ARC_PLAT_EZNPS
|
||||
bool "\"EZchip\" ARC dev platform"
|
||||
depends on ISA_ARCOMPACT
|
||||
select CPU_BIG_ENDIAN
|
||||
select CLKSRC_NPS if !PHYS_ADDR_T_64BIT
|
||||
select EZNPS_GIC
|
||||
|
@ -40,3 +40,7 @@
|
||||
status = "okay";
|
||||
dual_emac;
|
||||
};
|
||||
|
||||
&m_can0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -172,6 +172,7 @@
|
||||
#address-cells = <1>;
|
||||
ranges = <0x51000000 0x51000000 0x3000
|
||||
0x0 0x20000000 0x10000000>;
|
||||
dma-ranges;
|
||||
/**
|
||||
* To enable PCI endpoint mode, disable the pcie1_rc
|
||||
* node and enable pcie1_ep mode.
|
||||
@ -185,7 +186,6 @@
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x03000 0 0x00010000
|
||||
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
|
||||
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
num-lanes = <1>;
|
||||
@ -230,6 +230,7 @@
|
||||
#address-cells = <1>;
|
||||
ranges = <0x51800000 0x51800000 0x3000
|
||||
0x0 0x30000000 0x10000000>;
|
||||
dma-ranges;
|
||||
status = "disabled";
|
||||
pcie2_rc: pcie@51800000 {
|
||||
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
|
||||
@ -240,7 +241,6 @@
|
||||
device_type = "pci";
|
||||
ranges = <0x81000000 0 0 0x03000 0 0x00010000
|
||||
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
|
||||
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
num-lanes = <1>;
|
||||
|
@ -75,8 +75,8 @@
|
||||
imx27-phycard-s-rdk {
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
|
||||
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
|
||||
MX27_PAD_I2C_DATA__I2C_DATA 0x0
|
||||
MX27_PAD_I2C_CLK__I2C_CLK 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -38,7 +38,7 @@
|
||||
};
|
||||
|
||||
&switch_ports {
|
||||
/delete-node/ port@2;
|
||||
/delete-node/ port@3;
|
||||
};
|
||||
|
||||
&touchscreen {
|
||||
|
@ -72,8 +72,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -367,6 +367,8 @@
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc3_pins>;
|
||||
vmmc-supply = <&wl12xx_vmmc>;
|
||||
/* uart2_tx.sdmmc3_dat1 pad as wakeirq */
|
||||
interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
|
||||
@ -472,6 +474,37 @@
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Android uses PIN_OFF_INPUT_PULLDOWN | PIN_INPUT_PULLUP | MUX_MODE3
|
||||
* for gpio_100, but the internal pull makes wlan flakey on some
|
||||
* devices. Off mode value should be tested if we have off mode working
|
||||
* later on.
|
||||
*/
|
||||
mmc3_pins: pinmux_mmc3_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* 0x4a10008e gpmc_wait2.gpio_100 d23 */
|
||||
OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3)
|
||||
|
||||
/* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */
|
||||
OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP | MUX_MODE1)
|
||||
|
||||
/* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */
|
||||
OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP | MUX_MODE1)
|
||||
|
||||
/* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */
|
||||
OMAP4_IOPAD(0x118, PIN_INPUT | MUX_MODE1)
|
||||
|
||||
/* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */
|
||||
OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE1)
|
||||
|
||||
/* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */
|
||||
OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE1)
|
||||
|
||||
/* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */
|
||||
OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1)
|
||||
>;
|
||||
};
|
||||
|
||||
/* gpmc_ncs0.gpio_50 */
|
||||
poweroff_gpio: pinmux_poweroff_pins {
|
||||
pinctrl-single,pins = <
|
||||
@ -690,14 +723,18 @@
|
||||
};
|
||||
|
||||
/*
|
||||
* As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
|
||||
* uart1 wakeirq.
|
||||
* The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149
|
||||
* for wake-up events for both the USB PHY and the UART. We can use gpio_149
|
||||
* pad as the shared wakeirq for the UART rather than the RX or CTS pad as we
|
||||
* have gpio_149 trigger before the UART transfer starts.
|
||||
*/
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
|
||||
&omap4_pmx_core 0xfc>;
|
||||
&omap4_pmx_core 0x110>;
|
||||
uart-has-rtscts;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
|
@ -304,7 +304,6 @@
|
||||
reg = <0xe803b000 0x30>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 36>;
|
||||
clock-names = "ostm0";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -314,7 +313,6 @@
|
||||
reg = <0xe803c000 0x30>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 35>;
|
||||
clock-names = "ostm1";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -324,7 +322,6 @@
|
||||
reg = <0xe803d000 0x30>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&cpg CPG_MOD 34>;
|
||||
clock-names = "ostm2";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -131,7 +131,14 @@
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&pd_c5>;
|
||||
|
@ -479,7 +479,7 @@
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extalr_clk>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
|
@ -84,8 +84,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -364,8 +364,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -297,8 +297,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -387,8 +387,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -181,8 +181,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -289,8 +289,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -249,14 +249,12 @@
|
||||
*/
|
||||
hdmi@3d {
|
||||
compatible = "adi,adv7513";
|
||||
reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
|
||||
reg-names = "main", "cec", "edid", "packet";
|
||||
reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
|
||||
reg-names = "main", "edid", "cec", "packet";
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
@ -280,14 +278,12 @@
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7513";
|
||||
reg = <0x39>, <0x29>, <0x49>, <0x59>;
|
||||
reg-names = "main", "cec", "edid", "packet";
|
||||
reg = <0x39>, <0x49>, <0x29>, <0x59>;
|
||||
reg-names = "main", "edid", "cec", "packet";
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -366,8 +366,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -255,8 +255,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -128,7 +128,7 @@
|
||||
assigned-clocks = <&cru SCLK_GPU>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "bus", "core";
|
||||
resets = <&cru SRST_GPU>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -46,7 +46,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy: phy@0 {
|
||||
phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
clocks = <&cru SCLK_MAC_PHY>;
|
||||
|
@ -150,7 +150,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy: phy@0 {
|
||||
phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id1234.d400",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
|
@ -555,7 +555,7 @@
|
||||
"pp1",
|
||||
"ppmmu1";
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "bus", "core";
|
||||
resets = <&cru SRST_GPU_A>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1020,7 +1020,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
spi-0 {
|
||||
spi0 {
|
||||
spi0_clk: spi0-clk {
|
||||
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
|
||||
};
|
||||
@ -1038,7 +1038,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
spi-1 {
|
||||
spi1 {
|
||||
spi1_clk: spi1-clk {
|
||||
rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
|
||||
};
|
||||
|
@ -84,7 +84,7 @@
|
||||
compatible = "arm,mali-400";
|
||||
reg = <0x10090000 0x10000>;
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "bus", "core";
|
||||
assigned-clocks = <&cru ACLK_GPU>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_GPU>;
|
||||
|
@ -27,7 +27,8 @@ static void __iomem *gic_cpu_ctrl;
|
||||
#define GIC_CPU_CTRL 0x00
|
||||
#define GIC_CPU_CTRL_ENABLE 1
|
||||
|
||||
int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
static int __init ox820_boot_secondary(unsigned int cpu,
|
||||
struct task_struct *idle)
|
||||
{
|
||||
/*
|
||||
* Write the address of secondary startup into the
|
||||
|
@ -98,7 +98,7 @@
|
||||
};
|
||||
|
||||
&codec_analog {
|
||||
hpvcc-supply = <®_eldo1>;
|
||||
cpvdd-supply = <®_eldo1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -154,24 +154,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
sound_spdif {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "On-board SPDIF";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&spdif>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&spdif_out>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif_out: spdif-out {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "linux,spdif-dit";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
allwinner,erratum-unknown1;
|
||||
|
@ -2319,7 +2319,7 @@
|
||||
reg = <0x0 0xff400000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
||||
clock-names = "ddr";
|
||||
clock-names = "otg";
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "peripheral";
|
||||
|
@ -1,4 +1,3 @@
|
||||
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
|
@ -154,6 +154,10 @@
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&frddr_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&frddr_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -545,7 +545,7 @@
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
vbus-regulator = <&usb_pwr_en>;
|
||||
vbus-supply = <&usb_pwr_en>;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
|
@ -447,7 +447,7 @@
|
||||
|
||||
edma0: dma-controller@22c0000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,ls1028a-edma";
|
||||
compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
|
||||
reg = <0x0 0x22c0000 0x0 0x10000>,
|
||||
<0x0 0x22d0000 0x0 0x10000>,
|
||||
<0x0 0x22e0000 0x0 0x10000>;
|
||||
|
@ -264,7 +264,7 @@
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
@ -543,7 +543,7 @@
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x10000>;
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
@ -603,7 +603,7 @@
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x10000>;
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>,
|
||||
@ -863,7 +863,7 @@
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32df0000 0x10000>;
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x32c00000 0x32c00000 0x400000>;
|
||||
|
@ -241,7 +241,7 @@
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
@ -448,7 +448,7 @@
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x10000>;
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
@ -508,7 +508,7 @@
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x10000>;
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
@ -718,7 +718,7 @@
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA1_ROOT>;
|
||||
<&clk IMX8MN_CLK_AHB>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
@ -754,7 +754,7 @@
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32df0000 0x10000>;
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
@ -151,26 +151,26 @@
|
||||
#define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1
|
||||
#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0
|
||||
@ -291,7 +291,7 @@
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0
|
||||
@ -313,7 +313,7 @@
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0
|
||||
@ -487,27 +487,27 @@
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0
|
||||
#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0
|
||||
@ -528,22 +528,22 @@
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x3
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1
|
||||
#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0
|
||||
@ -624,7 +624,7 @@
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2
|
||||
@ -632,7 +632,7 @@
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0
|
||||
@ -641,7 +641,7 @@
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0
|
||||
@ -650,13 +650,13 @@
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0
|
||||
@ -680,7 +680,7 @@
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x4
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0
|
||||
@ -697,7 +697,7 @@
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7
|
||||
#define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0
|
||||
@ -706,7 +706,7 @@
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x5
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0
|
||||
@ -715,7 +715,7 @@
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x6
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7
|
||||
#define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0
|
||||
#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0
|
||||
|
@ -145,7 +145,7 @@
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
@ -318,7 +318,7 @@
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x400000>;
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
@ -378,7 +378,7 @@
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x400000>;
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
@ -291,7 +291,7 @@
|
||||
|
||||
bus@30000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x301f0000 0x10000>;
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30000000 0x30000000 0x400000>;
|
||||
@ -696,7 +696,7 @@
|
||||
|
||||
bus@30400000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x305f0000 0x10000>;
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30400000 0x30400000 0x400000>;
|
||||
@ -756,7 +756,7 @@
|
||||
|
||||
bus@30800000 { /* AIPS3 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x309f0000 0x10000>;
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x30800000 0x30800000 0x400000>,
|
||||
@ -1029,7 +1029,7 @@
|
||||
|
||||
bus@32c00000 { /* AIPS4 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32df0000 0x10000>;
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x32c00000 0x32c00000 0x400000>;
|
||||
|
@ -658,8 +658,8 @@
|
||||
s11 {
|
||||
qcom,saw-leader;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1230000>;
|
||||
regulator-max-microvolt = <1230000>;
|
||||
regulator-min-microvolt = <980000>;
|
||||
regulator-max-microvolt = <980000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -908,10 +908,27 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&q6asmdai {
|
||||
dai@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
dai@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
dai@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&sound {
|
||||
compatible = "qcom,apq8096-sndcard";
|
||||
model = "DB820c";
|
||||
audio-routing = "RX_BIAS", "MCLK";
|
||||
audio-routing = "RX_BIAS", "MCLK",
|
||||
"MM_DL1", "MultiMedia1 Playback",
|
||||
"MM_DL2", "MultiMedia2 Playback",
|
||||
"MultiMedia3 Capture", "MM_UL3";
|
||||
|
||||
mm1-dai-link {
|
||||
link-name = "MultiMedia1";
|
||||
|
@ -2066,6 +2066,8 @@
|
||||
reg = <APR_SVC_ASM>;
|
||||
q6asmdai: dais {
|
||||
compatible = "qcom,q6asm-dais";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#sound-dai-cells = <1>;
|
||||
iommus = <&lpass_q6_smmu 1>;
|
||||
};
|
||||
|
@ -442,17 +442,14 @@
|
||||
&q6asmdai {
|
||||
dai@0 {
|
||||
reg = <0>;
|
||||
direction = <2>;
|
||||
};
|
||||
|
||||
dai@1 {
|
||||
reg = <1>;
|
||||
direction = <2>;
|
||||
};
|
||||
|
||||
dai@2 {
|
||||
reg = <2>;
|
||||
direction = <1>;
|
||||
};
|
||||
|
||||
dai@3 {
|
||||
|
@ -359,12 +359,10 @@
|
||||
&q6asmdai {
|
||||
dai@0 {
|
||||
reg = <0>;
|
||||
direction = <2>;
|
||||
};
|
||||
|
||||
dai@1 {
|
||||
reg = <1>;
|
||||
direction = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -137,8 +137,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -150,8 +150,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -174,8 +174,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -141,8 +141,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -1318,6 +1318,7 @@
|
||||
ipmmu_vip0: mmu@e7b00000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7b00000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
@ -1325,6 +1326,7 @@
|
||||
ipmmu_vip1: mmu@e7960000 {
|
||||
compatible = "renesas,ipmmu-r8a77980";
|
||||
reg = <0 0xe7960000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 11>;
|
||||
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
@ -360,8 +360,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -272,8 +272,8 @@
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
|
||||
reg-names = "main", "edid", "packet", "cec";
|
||||
reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
|
||||
reg-names = "main", "edid", "cec", "packet";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
@ -284,8 +284,6 @@
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
@ -143,7 +143,7 @@
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
compatible = "arm,cortex-a35-pmu";
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -127,7 +127,7 @@
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
compatible = "arm,cortex-a35-pmu";
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -82,17 +82,16 @@
|
||||
&gmac2phy {
|
||||
phy-supply = <&vcc_phy>;
|
||||
clock_in_out = "output";
|
||||
assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
|
||||
assigned-clock-rate = <50000000>;
|
||||
assigned-clocks = <&cru SCLK_MAC2PHY>;
|
||||
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rk805: rk805@18 {
|
||||
rk805: pmic@18 {
|
||||
compatible = "rockchip,rk805";
|
||||
reg = <0x18>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
|
@ -170,7 +170,7 @@
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rk805: rk805@18 {
|
||||
rk805: pmic@18 {
|
||||
compatible = "rockchip,rk805";
|
||||
reg = <0x18>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
|
@ -299,8 +299,6 @@
|
||||
grf: syscon@ff100000 {
|
||||
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff100000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
io_domains: io-domains {
|
||||
compatible = "rockchip,rk3328-io-voltage-domain";
|
||||
@ -1794,10 +1792,6 @@
|
||||
};
|
||||
|
||||
gmac2phy {
|
||||
fephyled_speed100: fephyled-speed100 {
|
||||
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
fephyled_speed10: fephyled-speed10 {
|
||||
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
|
||||
};
|
||||
@ -1806,18 +1800,6 @@
|
||||
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
fephyled_rxm0: fephyled-rxm0 {
|
||||
rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
fephyled_txm0: fephyled-txm0 {
|
||||
rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
fephyled_linkm0: fephyled-linkm0 {
|
||||
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
fephyled_rxm1: fephyled-rxm1 {
|
||||
rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
@ -147,7 +147,7 @@
|
||||
"Speaker", "Speaker Amplifier OUTL",
|
||||
"Speaker", "Speaker Amplifier OUTR";
|
||||
|
||||
simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
simple-audio-card,aux-devs = <&speaker_amp>;
|
||||
simple-audio-card,pin-switches = "Speaker";
|
||||
|
||||
@ -690,7 +690,8 @@
|
||||
fusb0: fusb30x@22 {
|
||||
compatible = "fcs,fusb302";
|
||||
reg = <0x22>;
|
||||
fcs,int_n = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&fusb0_int_gpio>;
|
||||
vbus-supply = <&vbus_typec>;
|
||||
@ -788,13 +789,13 @@
|
||||
|
||||
dc-charger {
|
||||
dc_det_gpio: dc-det-gpio {
|
||||
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
es8316 {
|
||||
hp_det_gpio: hp-det-gpio {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -403,7 +403,7 @@
|
||||
reset-names = "usb3-otg";
|
||||
status = "disabled";
|
||||
|
||||
usbdrd_dwc3_0: dwc3 {
|
||||
usbdrd_dwc3_0: usb@fe800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xfe800000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
@ -439,7 +439,7 @@
|
||||
reset-names = "usb3-otg";
|
||||
status = "disabled";
|
||||
|
||||
usbdrd_dwc3_1: dwc3 {
|
||||
usbdrd_dwc3_1: usb@fe900000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xfe900000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
@ -1124,8 +1124,6 @@
|
||||
pmugrf: syscon@ff320000 {
|
||||
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff320000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pmu_io_domains: io-domains {
|
||||
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
|
||||
@ -1883,10 +1881,10 @@
|
||||
gpu: gpu@ff9a0000 {
|
||||
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
||||
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "gpu", "job", "mmu";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
#cooling-cells = <2>;
|
||||
power-domains = <&power RK3399_PD_GPU>;
|
||||
|
@ -208,7 +208,7 @@ CONFIG_PCIE_QCOM=y
|
||||
CONFIG_PCIE_ARMADA_8K=y
|
||||
CONFIG_PCIE_KIRIN=y
|
||||
CONFIG_PCIE_HISI_STB=y
|
||||
CONFIG_PCIE_TEGRA194=m
|
||||
CONFIG_PCIE_TEGRA194_HOST=m
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_FW_LOADER_USER_HELPER=y
|
||||
@ -567,6 +567,7 @@ CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
|
||||
CONFIG_MEDIA_SDR_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
CONFIG_MEDIA_PLATFORM_SUPPORT=y
|
||||
# CONFIG_DVB_NET is not set
|
||||
CONFIG_MEDIA_USB_SUPPORT=y
|
||||
CONFIG_USB_VIDEO_CLASS=m
|
||||
@ -610,8 +611,9 @@ CONFIG_DRM_MSM=m
|
||||
CONFIG_DRM_TEGRA=m
|
||||
CONFIG_DRM_PANEL_LVDS=m
|
||||
CONFIG_DRM_PANEL_SIMPLE=m
|
||||
CONFIG_DRM_DUMB_VGA_DAC=m
|
||||
CONFIG_DRM_SIMPLE_BRIDGE=m
|
||||
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
CONFIG_DRM_SII902X=m
|
||||
CONFIG_DRM_THINE_THC63LVD1024=m
|
||||
CONFIG_DRM_TI_SN65DSI86=m
|
||||
@ -848,7 +850,8 @@ CONFIG_QCOM_APR=m
|
||||
CONFIG_ARCH_R8A774A1=y
|
||||
CONFIG_ARCH_R8A774B1=y
|
||||
CONFIG_ARCH_R8A774C0=y
|
||||
CONFIG_ARCH_R8A7795=y
|
||||
CONFIG_ARCH_R8A77950=y
|
||||
CONFIG_ARCH_R8A77951=y
|
||||
CONFIG_ARCH_R8A77960=y
|
||||
CONFIG_ARCH_R8A77961=y
|
||||
CONFIG_ARCH_R8A77965=y
|
||||
|
@ -304,7 +304,7 @@ do { \
|
||||
__p = uaccess_mask_ptr(__p); \
|
||||
__raw_get_user((x), __p, (err)); \
|
||||
} else { \
|
||||
(x) = 0; (err) = -EFAULT; \
|
||||
(x) = (__force __typeof__(x))0; (err) = -EFAULT; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
@ -1829,10 +1829,11 @@ static void tracehook_report_syscall(struct pt_regs *regs,
|
||||
|
||||
int syscall_trace_enter(struct pt_regs *regs)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) ||
|
||||
test_thread_flag(TIF_SYSCALL_EMU)) {
|
||||
unsigned long flags = READ_ONCE(current_thread_info()->flags);
|
||||
|
||||
if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) {
|
||||
tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
|
||||
if (!in_syscall(regs) || test_thread_flag(TIF_SYSCALL_EMU))
|
||||
if (!in_syscall(regs) || (flags & _TIF_SYSCALL_EMU))
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
@ -8,6 +8,7 @@ config CSKY
|
||||
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
|
||||
select ARCH_USE_BUILTIN_BSWAP
|
||||
select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2
|
||||
select ARCH_WANT_FRAME_POINTERS if !CPU_CK610
|
||||
select COMMON_CLK
|
||||
select CLKSRC_MMIO
|
||||
select CSKY_MPINTC if CPU_CK860
|
||||
@ -38,6 +39,7 @@ config CSKY
|
||||
select HAVE_ARCH_TRACEHOOK
|
||||
select HAVE_ARCH_AUDITSYSCALL
|
||||
select HAVE_COPY_THREAD_TLS
|
||||
select HAVE_DEBUG_BUGVERBOSE
|
||||
select HAVE_DYNAMIC_FTRACE
|
||||
select HAVE_DYNAMIC_FTRACE_WITH_REGS
|
||||
select HAVE_FUNCTION_TRACER
|
||||
|
@ -47,7 +47,7 @@ ifeq ($(CSKYABI),abiv2)
|
||||
KBUILD_CFLAGS += -mno-stack-size
|
||||
endif
|
||||
|
||||
ifdef CONFIG_STACKTRACE
|
||||
ifdef CONFIG_FRAME_POINTER
|
||||
KBUILD_CFLAGS += -mbacktrace
|
||||
endif
|
||||
|
||||
|
@ -167,8 +167,8 @@
|
||||
* BA Reserved C D V
|
||||
*/
|
||||
cprcr r6, cpcr30
|
||||
lsri r6, 28
|
||||
lsli r6, 28
|
||||
lsri r6, 29
|
||||
lsli r6, 29
|
||||
addi r6, 0xe
|
||||
cpwcr r6, cpcr30
|
||||
|
||||
|
@ -285,8 +285,8 @@
|
||||
*/
|
||||
mfcr r6, cr<30, 15> /* Get MSA0 */
|
||||
2:
|
||||
lsri r6, 28
|
||||
lsli r6, 28
|
||||
lsri r6, 29
|
||||
lsli r6, 29
|
||||
addi r6, 0x1ce
|
||||
mtcr r6, cr<30, 15> /* Set MSA0 */
|
||||
|
||||
|
@ -103,6 +103,8 @@ ENTRY(_mcount)
|
||||
mov a0, lr
|
||||
subi a0, 4
|
||||
ldw a1, (sp, 24)
|
||||
lrw a2, function_trace_op
|
||||
ldw a2, (a2, 0)
|
||||
|
||||
jsr r26
|
||||
|
||||
|
@ -41,8 +41,7 @@ extern struct cpuinfo_csky cpu_data[];
|
||||
#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
|
||||
|
||||
struct thread_struct {
|
||||
unsigned long ksp; /* kernel stack pointer */
|
||||
unsigned long sr; /* saved status register */
|
||||
unsigned long sp; /* kernel stack pointer */
|
||||
unsigned long trap_no; /* saved status register */
|
||||
|
||||
/* FPU regs */
|
||||
@ -50,8 +49,7 @@ struct thread_struct {
|
||||
};
|
||||
|
||||
#define INIT_THREAD { \
|
||||
.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
|
||||
.sr = DEFAULT_PSR_VALUE, \
|
||||
.sp = sizeof(init_stack) + (unsigned long) &init_stack, \
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -58,6 +58,16 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
|
||||
return regs->usp;
|
||||
}
|
||||
|
||||
static inline unsigned long frame_pointer(struct pt_regs *regs)
|
||||
{
|
||||
return regs->regs[4];
|
||||
}
|
||||
static inline void frame_pointer_set(struct pt_regs *regs,
|
||||
unsigned long val)
|
||||
{
|
||||
regs->regs[4] = val;
|
||||
}
|
||||
|
||||
extern int regs_query_register_offset(const char *name);
|
||||
extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
|
||||
unsigned int n);
|
||||
|
@ -38,7 +38,13 @@ struct thread_info {
|
||||
#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
|
||||
|
||||
#define thread_saved_fp(tsk) \
|
||||
((unsigned long)(((struct switch_stack *)(tsk->thread.ksp))->r8))
|
||||
((unsigned long)(((struct switch_stack *)(tsk->thread.sp))->r8))
|
||||
|
||||
#define thread_saved_sp(tsk) \
|
||||
((unsigned long)(tsk->thread.sp))
|
||||
|
||||
#define thread_saved_lr(tsk) \
|
||||
((unsigned long)(((struct switch_stack *)(tsk->thread.sp))->r15))
|
||||
|
||||
static inline struct thread_info *current_thread_info(void)
|
||||
{
|
||||
@ -54,10 +60,10 @@ static inline struct thread_info *current_thread_info(void)
|
||||
#define TIF_SIGPENDING 0 /* signal pending */
|
||||
#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
|
||||
#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
|
||||
#define TIF_SYSCALL_TRACE 3 /* syscall trace active */
|
||||
#define TIF_SYSCALL_TRACEPOINT 4 /* syscall tracepoint instrumentation */
|
||||
#define TIF_SYSCALL_AUDIT 5 /* syscall auditing */
|
||||
#define TIF_UPROBE 6 /* uprobe breakpoint or singlestep */
|
||||
#define TIF_UPROBE 3 /* uprobe breakpoint or singlestep */
|
||||
#define TIF_SYSCALL_TRACE 4 /* syscall trace active */
|
||||
#define TIF_SYSCALL_TRACEPOINT 5 /* syscall tracepoint instrumentation */
|
||||
#define TIF_SYSCALL_AUDIT 6 /* syscall auditing */
|
||||
#define TIF_POLLING_NRFLAG 16 /* poll_idle() is TIF_NEED_RESCHED */
|
||||
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
|
||||
#define TIF_RESTORE_SIGMASK 20 /* restore signal mask in do_signal() */
|
||||
|
@ -253,7 +253,7 @@ do { \
|
||||
|
||||
extern int __get_user_bad(void);
|
||||
|
||||
#define __copy_user(to, from, n) \
|
||||
#define ___copy_to_user(to, from, n) \
|
||||
do { \
|
||||
int w0, w1, w2, w3; \
|
||||
asm volatile( \
|
||||
@ -288,31 +288,34 @@ do { \
|
||||
" subi %0, 4 \n" \
|
||||
" br 3b \n" \
|
||||
"5: cmpnei %0, 0 \n" /* 1B */ \
|
||||
" bf 8f \n" \
|
||||
" bf 13f \n" \
|
||||
" ldb %3, (%2, 0) \n" \
|
||||
"6: stb %3, (%1, 0) \n" \
|
||||
" addi %2, 1 \n" \
|
||||
" addi %1, 1 \n" \
|
||||
" subi %0, 1 \n" \
|
||||
" br 5b \n" \
|
||||
"7: br 8f \n" \
|
||||
"7: subi %0, 4 \n" \
|
||||
"8: subi %0, 4 \n" \
|
||||
"12: subi %0, 4 \n" \
|
||||
" br 13f \n" \
|
||||
".section __ex_table, \"a\" \n" \
|
||||
".align 2 \n" \
|
||||
".long 2b, 7b \n" \
|
||||
".long 9b, 7b \n" \
|
||||
".long 10b, 7b \n" \
|
||||
".long 2b, 13f \n" \
|
||||
".long 4b, 13f \n" \
|
||||
".long 6b, 13f \n" \
|
||||
".long 9b, 12b \n" \
|
||||
".long 10b, 8b \n" \
|
||||
".long 11b, 7b \n" \
|
||||
".long 4b, 7b \n" \
|
||||
".long 6b, 7b \n" \
|
||||
".previous \n" \
|
||||
"8: \n" \
|
||||
"13: \n" \
|
||||
: "=r"(n), "=r"(to), "=r"(from), "=r"(w0), \
|
||||
"=r"(w1), "=r"(w2), "=r"(w3) \
|
||||
: "0"(n), "1"(to), "2"(from) \
|
||||
: "memory"); \
|
||||
} while (0)
|
||||
|
||||
#define __copy_user_zeroing(to, from, n) \
|
||||
#define ___copy_from_user(to, from, n) \
|
||||
do { \
|
||||
int tmp; \
|
||||
int nsave; \
|
||||
@ -355,22 +358,22 @@ do { \
|
||||
" addi %1, 1 \n" \
|
||||
" subi %0, 1 \n" \
|
||||
" br 5b \n" \
|
||||
"8: mov %3, %0 \n" \
|
||||
" movi %4, 0 \n" \
|
||||
"9: stb %4, (%1, 0) \n" \
|
||||
" addi %1, 1 \n" \
|
||||
" subi %3, 1 \n" \
|
||||
" cmpnei %3, 0 \n" \
|
||||
" bt 9b \n" \
|
||||
" br 7f \n" \
|
||||
"8: stw %3, (%1, 0) \n" \
|
||||
" subi %0, 4 \n" \
|
||||
" bf 7f \n" \
|
||||
"9: subi %0, 8 \n" \
|
||||
" bf 7f \n" \
|
||||
"13: stw %3, (%1, 8) \n" \
|
||||
" subi %0, 12 \n" \
|
||||
" bf 7f \n" \
|
||||
".section __ex_table, \"a\" \n" \
|
||||
".align 2 \n" \
|
||||
".long 2b, 8b \n" \
|
||||
".long 2b, 7f \n" \
|
||||
".long 4b, 7f \n" \
|
||||
".long 6b, 7f \n" \
|
||||
".long 10b, 8b \n" \
|
||||
".long 11b, 8b \n" \
|
||||
".long 12b, 8b \n" \
|
||||
".long 4b, 8b \n" \
|
||||
".long 6b, 8b \n" \
|
||||
".long 11b, 9b \n" \
|
||||
".long 12b,13b \n" \
|
||||
".previous \n" \
|
||||
"7: \n" \
|
||||
: "=r"(n), "=r"(to), "=r"(from), "=r"(nsave), \
|
||||
|
@ -3,7 +3,7 @@ extra-y := head.o vmlinux.lds
|
||||
|
||||
obj-y += entry.o atomic.o signal.o traps.o irq.o time.o vdso.o
|
||||
obj-y += power.o syscall.o syscall_table.o setup.o
|
||||
obj-y += process.o cpu-probe.o ptrace.o dumpstack.o
|
||||
obj-y += process.o cpu-probe.o ptrace.o stacktrace.o
|
||||
obj-y += probes/
|
||||
|
||||
obj-$(CONFIG_MODULES) += module.o
|
||||
|
@ -18,8 +18,7 @@ int main(void)
|
||||
DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
|
||||
|
||||
/* offsets into the thread struct */
|
||||
DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
|
||||
DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
|
||||
DEFINE(THREAD_KSP, offsetof(struct thread_struct, sp));
|
||||
DEFINE(THREAD_FESR, offsetof(struct thread_struct, user_fp.fesr));
|
||||
DEFINE(THREAD_FCR, offsetof(struct thread_struct, user_fp.fcr));
|
||||
DEFINE(THREAD_FPREG, offsetof(struct thread_struct, user_fp.vr));
|
||||
|
@ -1,49 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
|
||||
|
||||
#include <linux/ptrace.h>
|
||||
|
||||
int kstack_depth_to_print = 48;
|
||||
|
||||
void show_trace(unsigned long *stack)
|
||||
{
|
||||
unsigned long *stack_end;
|
||||
unsigned long *stack_start;
|
||||
unsigned long *fp;
|
||||
unsigned long addr;
|
||||
|
||||
addr = (unsigned long) stack & THREAD_MASK;
|
||||
stack_start = (unsigned long *) addr;
|
||||
stack_end = (unsigned long *) (addr + THREAD_SIZE);
|
||||
|
||||
fp = stack;
|
||||
pr_info("\nCall Trace:");
|
||||
|
||||
while (fp > stack_start && fp < stack_end) {
|
||||
#ifdef CONFIG_STACKTRACE
|
||||
addr = fp[1];
|
||||
fp = (unsigned long *) fp[0];
|
||||
#else
|
||||
addr = *fp++;
|
||||
#endif
|
||||
if (__kernel_text_address(addr))
|
||||
pr_cont("\n[<%08lx>] %pS", addr, (void *)addr);
|
||||
}
|
||||
pr_cont("\n");
|
||||
}
|
||||
|
||||
void show_stack(struct task_struct *task, unsigned long *stack)
|
||||
{
|
||||
if (!stack) {
|
||||
if (task)
|
||||
stack = (unsigned long *)thread_saved_fp(task);
|
||||
else
|
||||
#ifdef CONFIG_STACKTRACE
|
||||
asm volatile("mov %0, r8\n":"=r"(stack)::"memory");
|
||||
#else
|
||||
stack = (unsigned long *)&stack;
|
||||
#endif
|
||||
}
|
||||
|
||||
show_trace(stack);
|
||||
}
|
@ -330,11 +330,6 @@ ENTRY(__switch_to)
|
||||
lrw a3, TASK_THREAD
|
||||
addu a3, a0
|
||||
|
||||
mfcr a2, psr /* Save PSR value */
|
||||
stw a2, (a3, THREAD_SR) /* Save PSR in task struct */
|
||||
bclri a2, 6 /* Disable interrupts */
|
||||
mtcr a2, psr
|
||||
|
||||
SAVE_SWITCH_STACK
|
||||
|
||||
stw sp, (a3, THREAD_KSP)
|
||||
@ -345,12 +340,9 @@ ENTRY(__switch_to)
|
||||
|
||||
ldw sp, (a3, THREAD_KSP) /* Set next kernel sp */
|
||||
|
||||
ldw a2, (a3, THREAD_SR) /* Set next PSR */
|
||||
mtcr a2, psr
|
||||
|
||||
#if defined(__CSKYABIV2__)
|
||||
addi r7, a1, TASK_THREAD_INFO
|
||||
ldw tls, (r7, TINFO_TP_VALUE)
|
||||
addi a3, a1, TASK_THREAD_INFO
|
||||
ldw tls, (a3, TINFO_TP_VALUE)
|
||||
#endif
|
||||
|
||||
RESTORE_SWITCH_STACK
|
||||
|
@ -202,6 +202,7 @@ int ftrace_disable_ftrace_graph_caller(void)
|
||||
#endif /* CONFIG_DYNAMIC_FTRACE */
|
||||
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
#ifndef CONFIG_CPU_HAS_ICACHE_INS
|
||||
struct ftrace_modify_param {
|
||||
int command;
|
||||
@ -231,6 +232,7 @@ void arch_ftrace_update_code(int command)
|
||||
stop_machine(__ftrace_modify_code, ¶m, cpu_online_mask);
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_DYNAMIC_FTRACE */
|
||||
|
||||
/* _mcount is defined in abi's mcount.S */
|
||||
EXPORT_SYMBOL(_mcount);
|
||||
|
@ -12,12 +12,17 @@ struct stackframe {
|
||||
|
||||
static int unwind_frame_kernel(struct stackframe *frame)
|
||||
{
|
||||
if (kstack_end((void *)frame->fp))
|
||||
unsigned long low = (unsigned long)task_stack_page(current);
|
||||
unsigned long high = low + THREAD_SIZE;
|
||||
|
||||
if (unlikely(frame->fp < low || frame->fp > high))
|
||||
return -EPERM;
|
||||
if (frame->fp & 0x3 || frame->fp < TASK_SIZE)
|
||||
|
||||
if (kstack_end((void *)frame->fp) || frame->fp & 0x3)
|
||||
return -EPERM;
|
||||
|
||||
*frame = *(struct stackframe *)frame->fp;
|
||||
|
||||
if (__kernel_text_address(frame->lr)) {
|
||||
int graph = 0;
|
||||
|
||||
|
@ -11,6 +11,11 @@
|
||||
|
||||
#define UPROBE_TRAP_NR UINT_MAX
|
||||
|
||||
bool is_swbp_insn(uprobe_opcode_t *insn)
|
||||
{
|
||||
return (*insn & 0xffff) == UPROBE_SWBP_INSN;
|
||||
}
|
||||
|
||||
unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
|
||||
{
|
||||
return instruction_pointer(regs);
|
||||
|
@ -35,7 +35,7 @@ void flush_thread(void){}
|
||||
*/
|
||||
unsigned long thread_saved_pc(struct task_struct *tsk)
|
||||
{
|
||||
struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
|
||||
struct switch_stack *sw = (struct switch_stack *)tsk->thread.sp;
|
||||
|
||||
return sw->r15;
|
||||
}
|
||||
@ -56,8 +56,8 @@ int copy_thread_tls(unsigned long clone_flags,
|
||||
childstack = ((struct switch_stack *) childregs) - 1;
|
||||
memset(childstack, 0, sizeof(struct switch_stack));
|
||||
|
||||
/* setup ksp for switch_to !!! */
|
||||
p->thread.ksp = (unsigned long)childstack;
|
||||
/* setup thread.sp for switch_to !!! */
|
||||
p->thread.sp = (unsigned long)childstack;
|
||||
|
||||
if (unlikely(p->flags & PF_KTHREAD)) {
|
||||
memset(childregs, 0, sizeof(struct pt_regs));
|
||||
@ -98,37 +98,6 @@ int dump_task_regs(struct task_struct *tsk, elf_gregset_t *pr_regs)
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned long get_wchan(struct task_struct *p)
|
||||
{
|
||||
unsigned long lr;
|
||||
unsigned long *fp, *stack_start, *stack_end;
|
||||
int count = 0;
|
||||
|
||||
if (!p || p == current || p->state == TASK_RUNNING)
|
||||
return 0;
|
||||
|
||||
stack_start = (unsigned long *)end_of_stack(p);
|
||||
stack_end = (unsigned long *)(task_stack_page(p) + THREAD_SIZE);
|
||||
|
||||
fp = (unsigned long *) thread_saved_fp(p);
|
||||
do {
|
||||
if (fp < stack_start || fp > stack_end)
|
||||
return 0;
|
||||
#ifdef CONFIG_STACKTRACE
|
||||
lr = fp[1];
|
||||
fp = (unsigned long *)fp[0];
|
||||
#else
|
||||
lr = *fp++;
|
||||
#endif
|
||||
if (!in_sched_functions(lr) &&
|
||||
__kernel_text_address(lr))
|
||||
return lr;
|
||||
} while (count++ < 16);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(get_wchan);
|
||||
|
||||
#ifndef CONFIG_CPU_PM_NONE
|
||||
void arch_cpu_idle(void)
|
||||
{
|
||||
|
@ -41,6 +41,9 @@ static void singlestep_disable(struct task_struct *tsk)
|
||||
|
||||
regs = task_pt_regs(tsk);
|
||||
regs->sr = (regs->sr & TRACE_MODE_MASK) | TRACE_MODE_RUN;
|
||||
|
||||
/* Enable irq */
|
||||
regs->sr |= BIT(6);
|
||||
}
|
||||
|
||||
static void singlestep_enable(struct task_struct *tsk)
|
||||
@ -49,6 +52,9 @@ static void singlestep_enable(struct task_struct *tsk)
|
||||
|
||||
regs = task_pt_regs(tsk);
|
||||
regs->sr = (regs->sr & TRACE_MODE_MASK) | TRACE_MODE_SI;
|
||||
|
||||
/* Disable irq */
|
||||
regs->sr &= ~BIT(6);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1,57 +1,159 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. */
|
||||
|
||||
#include <linux/sched/debug.h>
|
||||
#include <linux/sched/task_stack.h>
|
||||
#include <linux/stacktrace.h>
|
||||
#include <linux/ftrace.h>
|
||||
#include <linux/ptrace.h>
|
||||
|
||||
#ifdef CONFIG_FRAME_POINTER
|
||||
|
||||
struct stackframe {
|
||||
unsigned long fp;
|
||||
unsigned long ra;
|
||||
};
|
||||
|
||||
void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
|
||||
bool (*fn)(unsigned long, void *), void *arg)
|
||||
{
|
||||
unsigned long fp, sp, pc;
|
||||
|
||||
if (regs) {
|
||||
fp = frame_pointer(regs);
|
||||
sp = user_stack_pointer(regs);
|
||||
pc = instruction_pointer(regs);
|
||||
} else if (task == NULL || task == current) {
|
||||
const register unsigned long current_sp __asm__ ("sp");
|
||||
const register unsigned long current_fp __asm__ ("r8");
|
||||
fp = current_fp;
|
||||
sp = current_sp;
|
||||
pc = (unsigned long)walk_stackframe;
|
||||
} else {
|
||||
/* task blocked in __switch_to */
|
||||
fp = thread_saved_fp(task);
|
||||
sp = thread_saved_sp(task);
|
||||
pc = thread_saved_lr(task);
|
||||
}
|
||||
|
||||
for (;;) {
|
||||
unsigned long low, high;
|
||||
struct stackframe *frame;
|
||||
|
||||
if (unlikely(!__kernel_text_address(pc) || fn(pc, arg)))
|
||||
break;
|
||||
|
||||
/* Validate frame pointer */
|
||||
low = sp;
|
||||
high = ALIGN(sp, THREAD_SIZE);
|
||||
if (unlikely(fp < low || fp > high || fp & 0x3))
|
||||
break;
|
||||
/* Unwind stack frame */
|
||||
frame = (struct stackframe *)fp;
|
||||
sp = fp;
|
||||
fp = frame->fp;
|
||||
pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
|
||||
(unsigned long *)(fp - 8));
|
||||
}
|
||||
}
|
||||
|
||||
#else /* !CONFIG_FRAME_POINTER */
|
||||
|
||||
static void notrace walk_stackframe(struct task_struct *task,
|
||||
struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
|
||||
{
|
||||
unsigned long sp, pc;
|
||||
unsigned long *ksp;
|
||||
|
||||
if (regs) {
|
||||
sp = user_stack_pointer(regs);
|
||||
pc = instruction_pointer(regs);
|
||||
} else if (task == NULL || task == current) {
|
||||
const register unsigned long current_sp __asm__ ("sp");
|
||||
sp = current_sp;
|
||||
pc = (unsigned long)walk_stackframe;
|
||||
} else {
|
||||
/* task blocked in __switch_to */
|
||||
sp = thread_saved_sp(task);
|
||||
pc = thread_saved_lr(task);
|
||||
}
|
||||
|
||||
if (unlikely(sp & 0x3))
|
||||
return;
|
||||
|
||||
ksp = (unsigned long *)sp;
|
||||
while (!kstack_end(ksp)) {
|
||||
if (__kernel_text_address(pc) && unlikely(fn(pc, arg)))
|
||||
break;
|
||||
pc = (*ksp++) - 0x4;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_FRAME_POINTER */
|
||||
|
||||
static bool print_trace_address(unsigned long pc, void *arg)
|
||||
{
|
||||
print_ip_sym(pc);
|
||||
return false;
|
||||
}
|
||||
|
||||
void show_stack(struct task_struct *task, unsigned long *sp)
|
||||
{
|
||||
pr_cont("Call Trace:\n");
|
||||
walk_stackframe(task, NULL, print_trace_address, NULL);
|
||||
}
|
||||
|
||||
static bool save_wchan(unsigned long pc, void *arg)
|
||||
{
|
||||
if (!in_sched_functions(pc)) {
|
||||
unsigned long *p = arg;
|
||||
*p = pc;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned long get_wchan(struct task_struct *task)
|
||||
{
|
||||
unsigned long pc = 0;
|
||||
|
||||
if (likely(task && task != current && task->state != TASK_RUNNING))
|
||||
walk_stackframe(task, NULL, save_wchan, &pc);
|
||||
return pc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STACKTRACE
|
||||
static bool __save_trace(unsigned long pc, void *arg, bool nosched)
|
||||
{
|
||||
struct stack_trace *trace = arg;
|
||||
|
||||
if (unlikely(nosched && in_sched_functions(pc)))
|
||||
return false;
|
||||
if (unlikely(trace->skip > 0)) {
|
||||
trace->skip--;
|
||||
return false;
|
||||
}
|
||||
|
||||
trace->entries[trace->nr_entries++] = pc;
|
||||
return (trace->nr_entries >= trace->max_entries);
|
||||
}
|
||||
|
||||
static bool save_trace(unsigned long pc, void *arg)
|
||||
{
|
||||
return __save_trace(pc, arg, false);
|
||||
}
|
||||
|
||||
/*
|
||||
* Save stack-backtrace addresses into a stack_trace buffer.
|
||||
*/
|
||||
void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
|
||||
{
|
||||
walk_stackframe(tsk, NULL, save_trace, trace);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
|
||||
|
||||
void save_stack_trace(struct stack_trace *trace)
|
||||
{
|
||||
save_stack_trace_tsk(current, trace);
|
||||
save_stack_trace_tsk(NULL, trace);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(save_stack_trace);
|
||||
|
||||
void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
|
||||
{
|
||||
unsigned long *fp, *stack_start, *stack_end;
|
||||
unsigned long addr;
|
||||
int skip = trace->skip;
|
||||
int savesched;
|
||||
int graph_idx = 0;
|
||||
|
||||
if (tsk == current) {
|
||||
asm volatile("mov %0, r8\n":"=r"(fp));
|
||||
savesched = 1;
|
||||
} else {
|
||||
fp = (unsigned long *)thread_saved_fp(tsk);
|
||||
savesched = 0;
|
||||
}
|
||||
|
||||
addr = (unsigned long) fp & THREAD_MASK;
|
||||
stack_start = (unsigned long *) addr;
|
||||
stack_end = (unsigned long *) (addr + THREAD_SIZE);
|
||||
|
||||
while (fp > stack_start && fp < stack_end) {
|
||||
unsigned long lpp, fpp;
|
||||
|
||||
fpp = fp[0];
|
||||
lpp = fp[1];
|
||||
if (!__kernel_text_address(lpp))
|
||||
break;
|
||||
else
|
||||
lpp = ftrace_graph_ret_addr(tsk, &graph_idx, lpp, NULL);
|
||||
|
||||
if (savesched || !in_sched_functions(lpp)) {
|
||||
if (skip) {
|
||||
skip--;
|
||||
} else {
|
||||
trace->entries[trace->nr_entries++] = lpp;
|
||||
if (trace->nr_entries >= trace->max_entries)
|
||||
break;
|
||||
}
|
||||
}
|
||||
fp = (unsigned long *)fpp;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
|
||||
#endif /* CONFIG_STACKTRACE */
|
||||
|
@ -7,10 +7,7 @@
|
||||
unsigned long raw_copy_from_user(void *to, const void *from,
|
||||
unsigned long n)
|
||||
{
|
||||
if (access_ok(from, n))
|
||||
__copy_user_zeroing(to, from, n);
|
||||
else
|
||||
memset(to, 0, n);
|
||||
___copy_from_user(to, from, n);
|
||||
return n;
|
||||
}
|
||||
EXPORT_SYMBOL(raw_copy_from_user);
|
||||
@ -18,8 +15,7 @@ EXPORT_SYMBOL(raw_copy_from_user);
|
||||
unsigned long raw_copy_to_user(void *to, const void *from,
|
||||
unsigned long n)
|
||||
{
|
||||
if (access_ok(to, n))
|
||||
__copy_user(to, from, n);
|
||||
___copy_to_user(to, from, n);
|
||||
return n;
|
||||
}
|
||||
EXPORT_SYMBOL(raw_copy_to_user);
|
||||
|
@ -130,7 +130,7 @@ config PPC
|
||||
select ARCH_HAS_PTE_SPECIAL
|
||||
select ARCH_HAS_MEMBARRIER_CALLBACKS
|
||||
select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64
|
||||
select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION)
|
||||
select ARCH_HAS_STRICT_KERNEL_RWX if (PPC32 && !HIBERNATION)
|
||||
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
|
||||
select ARCH_HAS_UACCESS_FLUSHCACHE
|
||||
select ARCH_HAS_UACCESS_MCSAFE if PPC64
|
||||
|
@ -17,9 +17,9 @@
|
||||
* updating the accessed and modified bits in the page table tree.
|
||||
*/
|
||||
|
||||
#define _PAGE_USER 0x001 /* usermode access allowed */
|
||||
#define _PAGE_RW 0x002 /* software: user write access allowed */
|
||||
#define _PAGE_PRESENT 0x004 /* software: pte contains a translation */
|
||||
#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
|
||||
#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
|
||||
#define _PAGE_USER 0x004 /* usermode access allowed */
|
||||
#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
|
||||
#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
|
||||
#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
|
||||
@ -27,7 +27,7 @@
|
||||
#define _PAGE_DIRTY 0x080 /* C: page changed */
|
||||
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
|
||||
#define _PAGE_EXEC 0x200 /* software: exec allowed */
|
||||
#define _PAGE_HASHPTE 0x400 /* hash_page has made an HPTE for this pte */
|
||||
#define _PAGE_RW 0x400 /* software: user write access allowed */
|
||||
#define _PAGE_SPECIAL 0x800 /* software: Special page */
|
||||
|
||||
#ifdef CONFIG_PTE_64BIT
|
||||
|
@ -75,7 +75,7 @@
|
||||
|
||||
.macro kuap_check current, gpr
|
||||
#ifdef CONFIG_PPC_KUAP_DEBUG
|
||||
lwz \gpr2, KUAP(thread)
|
||||
lwz \gpr, KUAP(thread)
|
||||
999: twnei \gpr, 0
|
||||
EMIT_BUG_ENTRY 999b, __FILE__, __LINE__, (BUGFLAG_WARNING | BUGFLAG_ONCE)
|
||||
#endif
|
||||
|
@ -250,9 +250,27 @@ static inline bool arch_irqs_disabled(void)
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
static inline bool __lazy_irq_pending(u8 irq_happened)
|
||||
{
|
||||
return !!(irq_happened & ~PACA_IRQ_HARD_DIS);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if a lazy IRQ is pending. Should be called with IRQs hard disabled.
|
||||
*/
|
||||
static inline bool lazy_irq_pending(void)
|
||||
{
|
||||
return !!(get_paca()->irq_happened & ~PACA_IRQ_HARD_DIS);
|
||||
return __lazy_irq_pending(get_paca()->irq_happened);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if a lazy IRQ is pending, with no debugging checks.
|
||||
* Should be called with IRQs hard disabled.
|
||||
* For use in RI disabled code or other constrained situations.
|
||||
*/
|
||||
static inline bool lazy_irq_pending_nocheck(void)
|
||||
{
|
||||
return __lazy_irq_pending(local_paca->irq_happened);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -166,13 +166,17 @@ do { \
|
||||
({ \
|
||||
long __pu_err; \
|
||||
__typeof__(*(ptr)) __user *__pu_addr = (ptr); \
|
||||
__typeof__(*(ptr)) __pu_val = (x); \
|
||||
__typeof__(size) __pu_size = (size); \
|
||||
\
|
||||
if (!is_kernel_addr((unsigned long)__pu_addr)) \
|
||||
might_fault(); \
|
||||
__chk_user_ptr(ptr); \
|
||||
__chk_user_ptr(__pu_addr); \
|
||||
if (do_allow) \
|
||||
__put_user_size((x), __pu_addr, (size), __pu_err); \
|
||||
__put_user_size(__pu_val, __pu_addr, __pu_size, __pu_err); \
|
||||
else \
|
||||
__put_user_size_allowed((x), __pu_addr, (size), __pu_err); \
|
||||
__put_user_size_allowed(__pu_val, __pu_addr, __pu_size, __pu_err); \
|
||||
\
|
||||
__pu_err; \
|
||||
})
|
||||
|
||||
@ -180,9 +184,13 @@ do { \
|
||||
({ \
|
||||
long __pu_err = -EFAULT; \
|
||||
__typeof__(*(ptr)) __user *__pu_addr = (ptr); \
|
||||
__typeof__(*(ptr)) __pu_val = (x); \
|
||||
__typeof__(size) __pu_size = (size); \
|
||||
\
|
||||
might_fault(); \
|
||||
if (access_ok(__pu_addr, size)) \
|
||||
__put_user_size((x), __pu_addr, (size), __pu_err); \
|
||||
if (access_ok(__pu_addr, __pu_size)) \
|
||||
__put_user_size(__pu_val, __pu_addr, __pu_size, __pu_err); \
|
||||
\
|
||||
__pu_err; \
|
||||
})
|
||||
|
||||
@ -190,8 +198,12 @@ do { \
|
||||
({ \
|
||||
long __pu_err; \
|
||||
__typeof__(*(ptr)) __user *__pu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
__put_user_size((x), __pu_addr, (size), __pu_err); \
|
||||
__typeof__(*(ptr)) __pu_val = (x); \
|
||||
__typeof__(size) __pu_size = (size); \
|
||||
\
|
||||
__chk_user_ptr(__pu_addr); \
|
||||
__put_user_size(__pu_val, __pu_addr, __pu_size, __pu_err); \
|
||||
\
|
||||
__pu_err; \
|
||||
})
|
||||
|
||||
@ -283,15 +295,18 @@ do { \
|
||||
long __gu_err; \
|
||||
__long_type(*(ptr)) __gu_val; \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
__typeof__(size) __gu_size = (size); \
|
||||
\
|
||||
__chk_user_ptr(__gu_addr); \
|
||||
if (!is_kernel_addr((unsigned long)__gu_addr)) \
|
||||
might_fault(); \
|
||||
barrier_nospec(); \
|
||||
if (do_allow) \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
__get_user_size(__gu_val, __gu_addr, __gu_size, __gu_err); \
|
||||
else \
|
||||
__get_user_size_allowed(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
__get_user_size_allowed(__gu_val, __gu_addr, __gu_size, __gu_err); \
|
||||
(x) = (__typeof__(*(ptr)))__gu_val; \
|
||||
\
|
||||
__gu_err; \
|
||||
})
|
||||
|
||||
@ -300,12 +315,15 @@ do { \
|
||||
long __gu_err = -EFAULT; \
|
||||
__long_type(*(ptr)) __gu_val = 0; \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__typeof__(size) __gu_size = (size); \
|
||||
\
|
||||
might_fault(); \
|
||||
if (access_ok(__gu_addr, (size))) { \
|
||||
if (access_ok(__gu_addr, __gu_size)) { \
|
||||
barrier_nospec(); \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
__get_user_size(__gu_val, __gu_addr, __gu_size, __gu_err); \
|
||||
} \
|
||||
(x) = (__force __typeof__(*(ptr)))__gu_val; \
|
||||
\
|
||||
__gu_err; \
|
||||
})
|
||||
|
||||
@ -314,10 +332,13 @@ do { \
|
||||
long __gu_err; \
|
||||
__long_type(*(ptr)) __gu_val; \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
__typeof__(size) __gu_size = (size); \
|
||||
\
|
||||
__chk_user_ptr(__gu_addr); \
|
||||
barrier_nospec(); \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
__get_user_size(__gu_val, __gu_addr, __gu_size, __gu_err); \
|
||||
(x) = (__force __typeof__(*(ptr)))__gu_val; \
|
||||
\
|
||||
__gu_err; \
|
||||
})
|
||||
|
||||
|
@ -472,15 +472,17 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
|
||||
#ifdef CONFIG_PPC_BOOK3S
|
||||
/*
|
||||
* If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not
|
||||
* touched, AMR not set, no exit work created, then this can be used.
|
||||
* touched, no exit work created, then this can be used.
|
||||
*/
|
||||
.balign IFETCH_ALIGN_BYTES
|
||||
.globl fast_interrupt_return
|
||||
fast_interrupt_return:
|
||||
_ASM_NOKPROBE_SYMBOL(fast_interrupt_return)
|
||||
kuap_check_amr r3, r4
|
||||
ld r4,_MSR(r1)
|
||||
andi. r0,r4,MSR_PR
|
||||
bne .Lfast_user_interrupt_return
|
||||
kuap_restore_amr r3
|
||||
andi. r0,r4,MSR_RI
|
||||
li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
|
||||
bne+ .Lfast_kernel_interrupt_return
|
||||
|
@ -971,6 +971,7 @@ EXC_COMMON_BEGIN(system_reset_common)
|
||||
ld r10,SOFTE(r1)
|
||||
stb r10,PACAIRQSOFTMASK(r13)
|
||||
|
||||
kuap_restore_amr r10
|
||||
EXCEPTION_RESTORE_REGS
|
||||
RFI_TO_USER_OR_KERNEL
|
||||
|
||||
|
@ -348,7 +348,7 @@ BEGIN_MMU_FTR_SECTION
|
||||
andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
|
||||
#endif
|
||||
bne handle_page_fault_tramp_2 /* if not, try to put a PTE */
|
||||
rlwinm r3, r5, 32 - 24, 30, 30 /* DSISR_STORE -> _PAGE_RW */
|
||||
rlwinm r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */
|
||||
bl hash_page
|
||||
b handle_page_fault_tramp_1
|
||||
FTR_SECTION_ELSE
|
||||
@ -497,6 +497,7 @@ InstructionTLBMiss:
|
||||
andc. r1,r1,r0 /* check access & ~permission */
|
||||
bne- InstructionAddressInvalid /* return if access not permitted */
|
||||
/* Convert linux-style PTE to low word of PPC-style PTE */
|
||||
rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
|
||||
ori r1, r1, 0xe06 /* clear out reserved bits */
|
||||
andc r1, r0, r1 /* PP = user? 1 : 0 */
|
||||
BEGIN_FTR_SECTION
|
||||
@ -564,8 +565,9 @@ DataLoadTLBMiss:
|
||||
* we would need to update the pte atomically with lwarx/stwcx.
|
||||
*/
|
||||
/* Convert linux-style PTE to low word of PPC-style PTE */
|
||||
rlwinm r1,r0,0,30,30 /* _PAGE_RW -> PP msb */
|
||||
rlwimi r0,r0,1,30,30 /* _PAGE_USER -> PP msb */
|
||||
rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
|
||||
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
|
||||
rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
|
||||
ori r1,r1,0xe04 /* clear out reserved bits */
|
||||
andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
|
||||
BEGIN_FTR_SECTION
|
||||
@ -643,6 +645,7 @@ DataStoreTLBMiss:
|
||||
* we would need to update the pte atomically with lwarx/stwcx.
|
||||
*/
|
||||
/* Convert linux-style PTE to low word of PPC-style PTE */
|
||||
rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
|
||||
li r1,0xe06 /* clear out reserved bits & PP msb */
|
||||
andc r1,r0,r1 /* PP = user? 1: 0 */
|
||||
BEGIN_FTR_SECTION
|
||||
|
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Reference in New Issue
Block a user