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Merge branch 'hns3-error-handling'
Salil Mehta says:
====================
net: hns3: Additions/optimizations related to HNS3 H/W err handling
This patch set primarily does following addtions and optimizations
related to error handling in HNS3 Ethernet driver:
1. Name changes for enable and process functions and minor loop
optimizations. [PATCH 1-6]
2. Modify query and clearing of RAS errors using new set of commands
because modules specific commands for clearing RCB PPP PF, SSU are
obselete. [PATCH 7]
3. Deletes logging 1-bit errors for RAS in HNS3 driver as these never
get reported to the driver. [PATCH 8]
4. Add handling of NIC hw errors reported through MSIx rather than
PCIe AER channel. [PATCH 9]
5. Add handling for the HW RAS and MSIx errors in the modules MAC, PPP
PF, MSIx SRAM, RCB and SSU. [PATCH 10-13]
6. Add handling of RoCEE RAS errors. [PATCH 14]
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
12edfdfc79
@ -136,6 +136,7 @@ enum hnae3_reset_type {
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HNAE3_CORE_RESET,
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HNAE3_GLOBAL_RESET,
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HNAE3_IMP_RESET,
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HNAE3_UNKNOWN_RESET,
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HNAE3_NONE_RESET,
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};
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@ -454,7 +455,7 @@ struct hnae3_ae_ops {
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int (*restore_fd_rules)(struct hnae3_handle *handle);
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void (*enable_fd)(struct hnae3_handle *handle, bool enable);
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int (*dbg_run_cmd)(struct hnae3_handle *handle, char *cmd_buf);
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pci_ers_result_t (*process_hw_error)(struct hnae3_ae_dev *ae_dev);
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pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
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bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
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bool (*ae_dev_resetting)(struct hnae3_handle *handle);
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unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
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@ -1828,8 +1828,8 @@ static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
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return PCI_ERS_RESULT_NONE;
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}
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if (ae_dev->ops->process_hw_error)
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ret = ae_dev->ops->process_hw_error(ae_dev);
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if (ae_dev->ops->handle_hw_ras_error)
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ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
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else
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return PCI_ERS_RESULT_NONE;
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@ -215,26 +215,29 @@ enum hclge_opcode_type {
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HCLGE_OPC_SFP_GET_SPEED = 0x7104,
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/* Error INT commands */
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HCLGE_MAC_COMMON_INT_EN = 0x030E,
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HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
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HCLGE_TM_SCH_ECC_ERR_RINT_CMD = 0x082d,
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HCLGE_TM_SCH_ECC_ERR_RINT_CE = 0x082f,
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HCLGE_TM_SCH_ECC_ERR_RINT_NFE = 0x0830,
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HCLGE_TM_SCH_ECC_ERR_RINT_FE = 0x0831,
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HCLGE_TM_SCH_MBIT_ECC_INFO_CMD = 0x0833,
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HCLGE_SSU_ECC_INT_CMD = 0x0989,
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HCLGE_SSU_COMMON_INT_CMD = 0x098C,
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HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
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HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
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HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
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HCLGE_COMMON_ECC_INT_CFG = 0x1505,
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HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802,
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HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
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HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
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HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
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HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
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HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
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HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
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HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
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HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
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HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
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HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
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HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804,
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HCLGE_IGU_COMMON_INT_QUERY = 0x1805,
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HCLGE_IGU_COMMON_INT_EN = 0x1806,
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HCLGE_IGU_COMMON_INT_CLR = 0x1807,
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HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
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HCLGE_TM_QCN_MEM_INT_INFO_CMD = 0x1A17,
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HCLGE_PPP_CMD0_INT_CMD = 0x2100,
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HCLGE_PPP_CMD1_INT_CMD = 0x2101,
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HCLGE_NCSI_INT_QUERY = 0x2400,
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HCLGE_NCSI_INT_EN = 0x2401,
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HCLGE_NCSI_INT_CLR = 0x2402,
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};
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#define HCLGE_TQP_REG_OFFSET 0x80000
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File diff suppressed because it is too large
Load Diff
@ -7,9 +7,11 @@
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#include "hclge_main.h"
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#define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
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#define HCLGE_RAS_REG_FE_MASK 0xFF
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#define HCLGE_RAS_REG_NFE_MASK 0xFF00
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#define HCLGE_RAS_REG_NFE_SHIFT 8
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#define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
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#define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG 0x20800
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#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
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#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
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#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
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@ -23,6 +25,8 @@
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#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
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#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
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#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
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#define HCLGE_IGU_ERR_INT_EN 0x0000066F
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#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
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#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
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@ -41,21 +45,55 @@
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#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
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#define HCLGE_NCSI_ERR_INT_EN 0x3
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#define HCLGE_NCSI_ERR_INT_TYPE 0x9
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#define HCLGE_MAC_COMMON_ERR_INT_EN GENMASK(7, 0)
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#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK GENMASK(7, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
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#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
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#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
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#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
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#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
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#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
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#define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
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#define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
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#define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
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#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
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#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
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#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
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#define HCLGE_IMP_TCM_ECC_INT_MASK 0xFFFF
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#define HCLGE_IMP_ITCM4_ECC_INT_MASK 0x3
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#define HCLGE_CMDQ_ECC_INT_MASK 0xFFFF
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#define HCLGE_CMDQ_ROC_ECC_INT_SHIFT 16
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#define HCLGE_TQP_ECC_INT_MASK 0xFFF
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#define HCLGE_TQP_ECC_INT_SHIFT 16
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#define HCLGE_IMP_TCM_ECC_CLR_MASK 0xFFFF
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#define HCLGE_IMP_ITCM4_ECC_CLR_MASK 0x3
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#define HCLGE_CMDQ_NIC_ECC_CLR_MASK 0xFFFF
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#define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK 0xFFFF0000
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#define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001
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#define HCLGE_IGU_COM_INT_MASK 0xF
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#define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F
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#define HCLGE_PPP_PF_INT_MASK 0x100
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#define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
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#define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
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#define HCLGE_IGU_INT_MASK GENMASK(3, 0)
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#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
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#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
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#define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
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#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28)
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#define HCLGE_PPU_PF_INT_MSIX_MASK 0x27
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#define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
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#define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
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#define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
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#define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
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#define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
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#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
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#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
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#define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
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#define HCLGE_ROCEE_BERR_INT_MASK BIT(1)
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#define HCLGE_ROCEE_ECC_INT_MASK BIT(2)
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#define HCLGE_ROCEE_OVF_INT_MASK BIT(3)
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#define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
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#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
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enum hclge_err_int_type {
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HCLGE_ERR_INT_MSIX = 0,
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@ -67,9 +105,7 @@ enum hclge_err_int_type {
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struct hclge_hw_blk {
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u32 msk;
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const char *name;
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int (*enable_error)(struct hclge_dev *hdev, bool en);
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void (*process_error)(struct hclge_dev *hdev,
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enum hclge_err_int_type type);
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int (*config_err_int)(struct hclge_dev *hdev, bool en);
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};
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struct hclge_hw_error {
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@ -78,6 +114,7 @@ struct hclge_hw_error {
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};
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int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
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int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en);
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pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
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pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
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int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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unsigned long *reset_requests);
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#endif
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@ -2200,12 +2200,13 @@ static void hclge_service_complete(struct hclge_dev *hdev)
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static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
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{
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u32 rst_src_reg;
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u32 cmdq_src_reg;
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u32 rst_src_reg, cmdq_src_reg, msix_src_reg;
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/* fetch the events from their corresponding regs */
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rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
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cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
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msix_src_reg = hclge_read_dev(&hdev->hw,
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HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
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/* Assumption: If by any chance reset and mailbox events are reported
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* together then we will only process reset event in this go and will
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@ -2239,6 +2240,10 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
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return HCLGE_VECTOR0_EVENT_RST;
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}
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/* check for vector0 msix event source */
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if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK)
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return HCLGE_VECTOR0_EVENT_ERR;
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/* check for vector0 mailbox(=CMDQ RX) event source */
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if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
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cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
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@ -2289,6 +2294,19 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
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/* vector 0 interrupt is shared with reset and mailbox source events.*/
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switch (event_cause) {
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case HCLGE_VECTOR0_EVENT_ERR:
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/* we do not know what type of reset is required now. This could
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* only be decided after we fetch the type of errors which
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* caused this event. Therefore, we will do below for now:
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* 1. Assert HNAE3_UNKNOWN_RESET type of reset. This means we
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* have defered type of reset to be used.
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* 2. Schedule the reset serivce task.
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* 3. When service task receives HNAE3_UNKNOWN_RESET type it
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* will fetch the correct type of reset. This would be done
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* by first decoding the types of errors.
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*/
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set_bit(HNAE3_UNKNOWN_RESET, &hdev->reset_request);
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/* fall through */
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case HCLGE_VECTOR0_EVENT_RST:
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hclge_reset_task_schedule(hdev);
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break;
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@ -2593,6 +2611,23 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
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{
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enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
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/* first, resolve any unknown reset type to the known type(s) */
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if (test_bit(HNAE3_UNKNOWN_RESET, addr)) {
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/* we will intentionally ignore any errors from this function
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* as we will end up in *some* reset request in any case
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*/
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hclge_handle_hw_msix_error(hdev, addr);
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clear_bit(HNAE3_UNKNOWN_RESET, addr);
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/* We defered the clearing of the error event which caused
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* interrupt since it was not posssible to do that in
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* interrupt context (and this is the reason we introduced
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* new UNKNOWN reset type). Now, the errors have been
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* handled and cleared in hardware we can safely enable
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* interrupts. This is an exception to the norm.
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*/
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hclge_enable_vector(&hdev->misc_vector, true);
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}
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/* return the highest priority reset level amongst all */
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if (test_bit(HNAE3_IMP_RESET, addr)) {
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rst_level = HNAE3_IMP_RESET;
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@ -7269,7 +7304,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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ret = hclge_hw_error_set_state(hdev, true);
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if (ret) {
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dev_err(&pdev->dev,
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"hw error interrupts enable failed, ret =%d\n", ret);
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"fail(%d) to enable hw error interrupts\n", ret);
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goto err_mdiobus_unreg;
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}
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@ -7405,11 +7440,15 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
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return ret;
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}
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/* Re-enable the TM hw error interrupts because
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* they get disabled on core/global reset.
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/* Re-enable the hw error interrupts because
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* the interrupts get disabled on core/global reset.
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*/
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if (hclge_enable_tm_hw_error(hdev, true))
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dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
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ret = hclge_hw_error_set_state(hdev, true);
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if (ret) {
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dev_err(&pdev->dev,
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"fail(%d) to re-enable HNS hw error interrupts\n", ret);
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return ret;
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}
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hclge_reset_vport_state(hdev);
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@ -7931,7 +7970,7 @@ static const struct hnae3_ae_ops hclge_ops = {
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.restore_fd_rules = hclge_restore_fd_entries,
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.enable_fd = hclge_enable_fd,
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.dbg_run_cmd = hclge_dbg_run_cmd,
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.process_hw_error = hclge_process_ras_hw_error,
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.handle_hw_ras_error = hclge_handle_hw_ras_error,
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.get_hw_reset_stat = hclge_get_hw_reset_stat,
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.ae_dev_resetting = hclge_ae_dev_resetting,
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.ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
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@ -205,6 +205,7 @@ enum HCLGE_DEV_STATE {
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enum hclge_evt_cause {
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HCLGE_VECTOR0_EVENT_RST,
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HCLGE_VECTOR0_EVENT_MBX,
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HCLGE_VECTOR0_EVENT_ERR,
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HCLGE_VECTOR0_EVENT_OTHER,
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};
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