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drm: bridge/dw_hdmi: add rockchip rk3288 support
Rockchip RK3288 hdmi is compatible with dw_hdmi Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Andy Yan
Philipp Zabel
parent
74af9e4d03
commit
12b9f204e8
@ -852,6 +852,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
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dw_hdmi_phy_gen2_txpwron(hdmi, 1);
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dw_hdmi_phy_gen2_pddq(hdmi, 0);
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if (hdmi->dev_type == RK3288_HDMI)
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dw_hdmi_phy_enable_spare(hdmi, 1);
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/*Wait for PHY PLL lock */
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msec = 5;
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do {
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@ -15,3 +15,13 @@ config DRM_ROCKCHIP
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management to userspace. This driver does not provide
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2D or 3D acceleration; acceleration is performed by other
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IP found on the SoC.
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config ROCKCHIP_DW_HDMI
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tristate "Rockchip specific extensions for Synopsys DW HDMI"
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depends on DRM_ROCKCHIP
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select DRM_DW_HDMI
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help
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This selects support for Rockchip SoC specific extensions
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for the Synopsys DesignWare HDMI driver. If you want to
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enable HDMI on RK3288 based SoC, you should selet this
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option.
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@ -5,4 +5,6 @@
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rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
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rockchip_drm_gem.o
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obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
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obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
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341
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
Normal file
341
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
Normal file
@ -0,0 +1,341 @@
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <drm/drm_of.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder_slave.h>
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#include <drm/bridge/dw_hdmi.h>
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#include "rockchip_drm_drv.h"
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#include "rockchip_drm_vop.h"
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#define GRF_SOC_CON6 0x025c
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#define HDMI_SEL_VOP_LIT (1 << 4)
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struct rockchip_hdmi {
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struct device *dev;
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struct regmap *regmap;
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struct drm_encoder encoder;
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};
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#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
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static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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27000000, {
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{ 0x00b3, 0x0000},
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{ 0x2153, 0x0000},
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{ 0x40f3, 0x0000}
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},
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}, {
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36000000, {
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{ 0x00b3, 0x0000},
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{ 0x2153, 0x0000},
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{ 0x40f3, 0x0000}
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},
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}, {
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40000000, {
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{ 0x00b3, 0x0000},
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{ 0x2153, 0x0000},
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{ 0x40f3, 0x0000}
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},
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}, {
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54000000, {
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{ 0x0072, 0x0001},
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{ 0x2142, 0x0001},
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{ 0x40a2, 0x0001},
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},
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}, {
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65000000, {
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{ 0x0072, 0x0001},
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{ 0x2142, 0x0001},
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{ 0x40a2, 0x0001},
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},
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}, {
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66000000, {
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{ 0x013e, 0x0003},
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{ 0x217e, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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74250000, {
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{ 0x0072, 0x0001},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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83500000, {
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{ 0x0072, 0x0001},
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},
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}, {
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108000000, {
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{ 0x0051, 0x0002},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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106500000, {
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{ 0x0051, 0x0002},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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146250000, {
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{ 0x0051, 0x0002},
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{ 0x2145, 0x0002},
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{ 0x4061, 0x0002}
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},
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}, {
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148500000, {
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{ 0x0051, 0x0003},
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{ 0x214c, 0x0003},
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{ 0x4064, 0x0003}
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},
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}, {
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~0UL, {
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{ 0x00a0, 0x000a },
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{ 0x2001, 0x000f },
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{ 0x4002, 0x000f },
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},
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}
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};
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static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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40000000, { 0x0018, 0x0018, 0x0018 },
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}, {
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65000000, { 0x0028, 0x0028, 0x0028 },
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}, {
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66000000, { 0x0038, 0x0038, 0x0038 },
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}, {
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74250000, { 0x0028, 0x0038, 0x0038 },
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}, {
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83500000, { 0x0028, 0x0038, 0x0038 },
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}, {
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146250000, { 0x0038, 0x0038, 0x0038 },
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}, {
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148500000, { 0x0000, 0x0038, 0x0038 },
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}, {
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~0UL, { 0x0000, 0x0000, 0x0000},
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}
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};
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static const struct dw_hdmi_sym_term rockchip_sym_term[] = {
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/*pixelclk symbol term*/
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{ 74250000, 0x8009, 0x0004 },
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{ 148500000, 0x8029, 0x0004 },
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{ 297000000, 0x8039, 0x0005 },
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{ ~0UL, 0x0000, 0x0000 }
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};
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static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
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{
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struct device_node *np = hdmi->dev->of_node;
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hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
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if (IS_ERR(hdmi->regmap)) {
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dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
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return PTR_ERR(hdmi->regmap);
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}
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return 0;
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}
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static enum drm_mode_status
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dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
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int pclk = mode->clock * 1000;
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bool valid = false;
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int i;
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for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
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if (pclk == mpll_cfg[i].mpixelclock) {
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valid = true;
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break;
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}
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}
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return (valid) ? MODE_OK : MODE_BAD;
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}
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static struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
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.destroy = drm_encoder_cleanup,
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};
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static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
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{
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}
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static bool
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dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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return true;
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}
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static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adj_mode)
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{
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}
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static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
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{
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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u32 val;
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int mux;
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mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
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if (mux)
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val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
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else
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val = HDMI_SEL_VOP_LIT << 16;
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regmap_write(hdmi->regmap, GRF_SOC_CON6, val);
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dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
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(mux) ? "LIT" : "BIG");
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}
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static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
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{
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rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
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ROCKCHIP_OUT_MODE_AAAA);
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}
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static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
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.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
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.mode_set = dw_hdmi_rockchip_encoder_mode_set,
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.prepare = dw_hdmi_rockchip_encoder_prepare,
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.commit = dw_hdmi_rockchip_encoder_commit,
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.disable = dw_hdmi_rockchip_encoder_disable,
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};
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static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.sym_term = rockchip_sym_term,
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.dev_type = RK3288_HDMI,
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};
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static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-hdmi",
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.data = &rockchip_hdmi_drv_data
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
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static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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const struct dw_hdmi_plat_data *plat_data;
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const struct of_device_id *match;
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struct drm_device *drm = data;
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struct drm_encoder *encoder;
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struct rockchip_hdmi *hdmi;
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struct resource *iores;
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int irq;
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int ret;
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if (!pdev->dev.of_node)
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return -ENODEV;
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hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
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if (!hdmi)
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return -ENOMEM;
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match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
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plat_data = match->data;
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hdmi->dev = &pdev->dev;
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encoder = &hdmi->encoder;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!iores)
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return -ENXIO;
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platform_set_drvdata(pdev, hdmi);
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encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
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/*
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* If we failed to find the CRTC(s) which this encoder is
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* supposed to be connected to, it's because the CRTC has
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* not been registered yet. Defer probing, and hope that
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* the required CRTC is added later.
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*/
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if (encoder->possible_crtcs == 0)
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return -EPROBE_DEFER;
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ret = rockchip_hdmi_parse_dt(hdmi);
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if (ret) {
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dev_err(hdmi->dev, "Unable to parse OF data\n");
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return ret;
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}
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drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
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drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
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DRM_MODE_ENCODER_TMDS);
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return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
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}
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static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
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void *data)
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{
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return dw_hdmi_unbind(dev, master, data);
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}
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static const struct component_ops dw_hdmi_rockchip_ops = {
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.bind = dw_hdmi_rockchip_bind,
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.unbind = dw_hdmi_rockchip_unbind,
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};
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static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
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}
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static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
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return 0;
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}
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static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
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.probe = dw_hdmi_rockchip_probe,
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.remove = dw_hdmi_rockchip_remove,
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.driver = {
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.name = "dwhdmi-rockchip",
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.of_match_table = dw_hdmi_rockchip_dt_ids,
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},
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};
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module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
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MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
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MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:dwhdmi-rockchip");
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@ -22,6 +22,7 @@ enum {
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enum dw_hdmi_devtype {
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IMX6Q_HDMI,
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IMX6DL_HDMI,
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RK3288_HDMI,
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};
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struct dw_hdmi_mpll_config {
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