korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-29 15:14:18 +08:00
Code Issues Packages Projects Releases Wiki Activity

staging: r8188eu: make odm_ConfigRF_RadioA_8188E() static

Browse Source 
The function odm_ConfigRF_RadioA_8188E() is only used in
HalHWImg8188E_RF.c. Make it static.

Signed-off-by: Michael Straube <straube.linux@gmail.com>
Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> # Edimax N150
Link: https://lore.kernel.org/r/20220926173243.8767-3-straube.linux@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Michael Straube 2022-09-26 19:32:42 +02:00 committed by Greg Kroah-Hartman
parent 0061a2a955
commit 1254b194f8
3 changed files with 30 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/staging/r8188eu/hal/HalHWImg8188E_RF.c
View File

@ -130,6 +130,36 @@ static u32 Array_RadioA_1T_8188E[] = {
0x000, 0x00033E60, 0x000, 0x00033E60,
}; };
static void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
u32 Data, u32 RegAddr)
{
if (Addr == 0xffe) {
msleep(50);
} else if (Addr == 0xfd) {
mdelay(5);
} else if (Addr == 0xfc) {
mdelay(1);
} else if (Addr == 0xfb) {
udelay(50);
} else if (Addr == 0xfa) {
udelay(5);
} else if (Addr == 0xf9) {
udelay(1);
} else {
rtl8188e_PHY_SetRFReg(pDM_Odm->Adapter, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
}
}
static void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskforPhySet = (u32)(content & 0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, Addr | maskforPhySet);
}
enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *pDM_Odm) enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *pDM_Odm)
{ {
#define READ_NEXT_PAIR(v1, v2, i) do \ #define READ_NEXT_PAIR(v1, v2, i) do \

30
drivers/staging/r8188eu/hal/odm_RegConfig8188E.c
View File

@ -3,36 +3,6 @@
#include "../include/drv_types.h" #include "../include/drv_types.h"
static void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
u32 Data, u32 RegAddr)
{
if (Addr == 0xffe) {
msleep(50);
} else if (Addr == 0xfd) {
mdelay(5);
} else if (Addr == 0xfc) {
mdelay(1);
} else if (Addr == 0xfb) {
udelay(50);
} else if (Addr == 0xfa) {
udelay(5);
} else if (Addr == 0xf9) {
udelay(1);
} else {
rtl8188e_PHY_SetRFReg(pDM_Odm->Adapter, RegAddr, bRFRegOffsetMask, Data);
/* Add 1us delay between BB/RF register setting. */
udelay(1);
}
}
void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskforPhySet = (u32)(content & 0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, Addr | maskforPhySet);
}
void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
{ {
rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);

3
drivers/staging/r8188eu/include/odm_RegConfig8188E.h
View File

@ -4,9 +4,6 @@
#ifndef __INC_ODM_REGCONFIG_H_8188E #ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E #define __INC_ODM_REGCONFIG_H_8188E
void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm,
u32 Addr, u32 Data);
void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
u32 Bitmask, u32 Data); u32 Bitmask, u32 Data);