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clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x
Commit7dd3376448("ARM: davinci: Delete DM644x board files") and commitb4aed01de4("ARM: davinci: Delete DM646x board files") removes the support for DaVinci DM644x and DM646x boards. Hence, remove the PLL and PSC clock descriptions for those boards as well. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220720082934.17741-1-lukas.bulwahn@gmail.com Reviewed-by: David Lechner <david@lechnology.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lukas Bulwahn
Stephen Boyd
parent
568035b01c
commit
12198d9179
@ -8,14 +8,10 @@ obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
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obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
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obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
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obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
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obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o
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obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
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obj-y += psc.o
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obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
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obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
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obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
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obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o
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obj-$(CONFIG_ARCH_DAVINCI_DM644x) += psc-dm644x.o
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obj-$(CONFIG_ARCH_DAVINCI_DM646x) += psc-dm646x.o
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endif
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@ -1,81 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock descriptions for TI DM644X
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/bitops.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include "pll.h"
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static const struct davinci_pll_clk_info dm644x_pll1_info = {
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.name = "pll1",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 1,
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.pllm_max = 32,
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.pllout_min_rate = 400000000,
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.pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */
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.flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,
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};
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SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
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clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
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clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
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clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");
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clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
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clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");
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davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
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return 0;
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}
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static const struct davinci_pll_clk_info dm644x_pll2_info = {
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.name = "pll2",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 1,
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.pllm_max = 32,
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.pllout_min_rate = 400000000,
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.pllout_max_rate = 900000000,
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.flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,
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};
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
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SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
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int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
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davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
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return 0;
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}
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@ -1,85 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock descriptions for TI DM646X
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include "pll.h"
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static const struct davinci_pll_clk_info dm646x_pll1_info = {
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.name = "pll1",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 14,
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.pllm_max = 32,
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.flags = PLL_HAS_CLKMODE,
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};
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SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(4, pll1_sysclk4, pll1_pllen, 4, 0);
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SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, 0);
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SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);
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SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);
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SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);
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int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
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clk_register_clkdev(clk, "pll1_sysclk2", "dm646x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
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clk_register_clkdev(clk, "pll1_sysclk3", "dm646x-psc");
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clk_register_clkdev(clk, NULL, "davinci-wdt");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
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clk_register_clkdev(clk, "pll1_sysclk4", "dm646x-psc");
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
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clk_register_clkdev(clk, "pll1_sysclk5", "dm646x-psc");
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davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
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davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
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davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
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davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
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davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
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return 0;
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}
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static const struct davinci_pll_clk_info dm646x_pll2_info = {
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.name = "pll2",
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 14,
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.pllm_max = 32,
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.flags = 0,
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};
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
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int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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return 0;
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}
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@ -889,14 +889,6 @@ static const struct platform_device_id davinci_pll_id_table[] = {
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#ifdef CONFIG_ARCH_DAVINCI_DM365
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{ .name = "dm365-pll1", .driver_data = (kernel_ulong_t)dm365_pll1_init },
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{ .name = "dm365-pll2", .driver_data = (kernel_ulong_t)dm365_pll2_init },
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM644x
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{ .name = "dm644x-pll1", .driver_data = (kernel_ulong_t)dm644x_pll1_init },
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{ .name = "dm644x-pll2", .driver_data = (kernel_ulong_t)dm644x_pll2_init },
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM646x
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{ .name = "dm646x-pll1", .driver_data = (kernel_ulong_t)dm646x_pll1_init },
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{ .name = "dm646x-pll2", .driver_data = (kernel_ulong_t)dm646x_pll2_init },
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#endif
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{ }
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};
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@ -130,11 +130,5 @@ int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cf
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#ifdef CONFIG_ARCH_DAVINCI_DM355
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int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM644x
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int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM646x
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int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#endif /* __CLK_DAVINCI_PLL_H___ */
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@ -1,85 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PSC clock descriptions for TI DaVinci DM644x
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include "psc.h"
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LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss");
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LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss");
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LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
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"fck", "davinci_mdio.0");
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LPSC_CLKDEV1(usb_clkdev, "usb", NULL);
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LPSC_CLKDEV1(ide_clkdev, NULL, "palm_bk3710");
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LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL,
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NULL, "ti-aemif");
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LPSC_CLKDEV1(mmcsd_clkdev, NULL, "dm6441-mmc.0");
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LPSC_CLKDEV1(asp0_clkdev, NULL, "davinci-mcbsp");
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LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
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LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
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LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
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LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
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/* REVISIT: gpio-davinci.c should be modified to drop con_id */
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LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
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LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
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LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt");
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static const struct davinci_lpsc_clk_info dm644x_psc_info[] = {
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LPSC(0, 0, vpss_master, pll1_sysclk3, vpss_master_clkdev, 0),
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LPSC(1, 0, vpss_slave, pll1_sysclk3, vpss_slave_clkdev, 0),
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LPSC(6, 0, emac, pll1_sysclk5, emac_clkdev, 0),
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LPSC(9, 0, usb, pll1_sysclk5, usb_clkdev, 0),
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LPSC(10, 0, ide, pll1_sysclk5, ide_clkdev, 0),
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LPSC(11, 0, vlynq, pll1_sysclk5, NULL, 0),
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LPSC(14, 0, aemif, pll1_sysclk5, aemif_clkdev, 0),
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LPSC(15, 0, mmcsd, pll1_sysclk5, mmcsd_clkdev, 0),
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LPSC(17, 0, asp0, pll1_sysclk5, asp0_clkdev, 0),
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LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0),
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LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0),
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LPSC(20, 0, uart1, pll1_auxclk, uart1_clkdev, 0),
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LPSC(21, 0, uart2, pll1_auxclk, uart2_clkdev, 0),
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LPSC(22, 0, spi, pll1_sysclk5, NULL, 0),
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LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0),
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LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0),
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LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0),
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LPSC(26, 0, gpio, pll1_sysclk5, gpio_clkdev, 0),
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LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
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LPSC(28, 0, timer1, pll1_auxclk, NULL, 0),
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/* REVISIT: why can't this be disabled? */
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LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED),
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LPSC(31, 0, arm, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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/* REVISIT how to disable? */
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LPSC(39, 1, dsp, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
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/* REVISIT how to disable? */
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LPSC(40, 1, vicp, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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{ }
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};
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int dm644x_psc_init(struct device *dev, void __iomem *base)
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{
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return davinci_psc_register_clocks(dev, dm644x_psc_info, 41, base);
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}
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static struct clk_bulk_data dm644x_psc_parent_clks[] = {
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{ .id = "pll1_sysclk1" },
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{ .id = "pll1_sysclk2" },
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{ .id = "pll1_sysclk3" },
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{ .id = "pll1_sysclk5" },
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{ .id = "pll1_auxclk" },
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};
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const struct davinci_psc_init_data dm644x_psc_init_data = {
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.parent_clks = dm644x_psc_parent_clks,
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.num_parent_clks = ARRAY_SIZE(dm644x_psc_parent_clks),
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.psc_init = &dm644x_psc_init,
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};
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@ -1,82 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PSC clock descriptions for TI DaVinci DM646x
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include "psc.h"
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LPSC_CLKDEV1(ide_clkdev, NULL, "palm_bk3710");
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LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
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"fck", "davinci_mdio.0");
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LPSC_CLKDEV2(aemif_clkdev, "aemif", NULL,
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NULL, "ti-aemif");
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LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
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LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1");
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LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
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LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
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LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
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LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1");
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/* REVISIT: gpio-davinci.c should be modified to drop con_id */
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LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
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LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
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static const struct davinci_lpsc_clk_info dm646x_psc_info[] = {
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LPSC(0, 0, arm, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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/* REVISIT how to disable? */
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LPSC(1, 0, dsp, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(4, 0, edma_cc, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(5, 0, edma_tc0, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(6, 0, edma_tc1, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(7, 0, edma_tc2, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(8, 0, edma_tc3, pll1_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
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LPSC(10, 0, ide, pll1_sysclk4, ide_clkdev, 0),
|
||||
LPSC(14, 0, emac, pll1_sysclk3, emac_clkdev, 0),
|
||||
LPSC(16, 0, vpif0, ref_clk, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(17, 0, vpif1, ref_clk, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(21, 0, aemif, pll1_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(22, 0, mcasp0, pll1_sysclk3, mcasp0_clkdev, 0),
|
||||
LPSC(23, 0, mcasp1, pll1_sysclk3, mcasp1_clkdev, 0),
|
||||
LPSC(26, 0, uart0, aux_clkin, uart0_clkdev, 0),
|
||||
LPSC(27, 0, uart1, aux_clkin, uart1_clkdev, 0),
|
||||
LPSC(28, 0, uart2, aux_clkin, uart2_clkdev, 0),
|
||||
/* REVIST: disabling hangs system */
|
||||
LPSC(29, 0, pwm0, pll1_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
|
||||
/* REVIST: disabling hangs system */
|
||||
LPSC(30, 0, pwm1, pll1_sysclk3, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(31, 0, i2c, pll1_sysclk3, i2c_clkdev, 0),
|
||||
LPSC(33, 0, gpio, pll1_sysclk3, gpio_clkdev, 0),
|
||||
LPSC(34, 0, timer0, pll1_sysclk3, timer0_clkdev, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(35, 0, timer1, pll1_sysclk3, NULL, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
int dm646x_psc_init(struct device *dev, void __iomem *base)
|
||||
{
|
||||
return davinci_psc_register_clocks(dev, dm646x_psc_info, 46, base);
|
||||
}
|
||||
|
||||
static struct clk_bulk_data dm646x_psc_parent_clks[] = {
|
||||
{ .id = "ref_clk" },
|
||||
{ .id = "aux_clkin" },
|
||||
{ .id = "pll1_sysclk1" },
|
||||
{ .id = "pll1_sysclk2" },
|
||||
{ .id = "pll1_sysclk3" },
|
||||
{ .id = "pll1_sysclk4" },
|
||||
{ .id = "pll1_sysclk5" },
|
||||
};
|
||||
|
||||
const struct davinci_psc_init_data dm646x_psc_init_data = {
|
||||
.parent_clks = dm646x_psc_parent_clks,
|
||||
.num_parent_clks = ARRAY_SIZE(dm646x_psc_parent_clks),
|
||||
.psc_init = &dm646x_psc_init,
|
||||
};
|
||||
@ -516,12 +516,6 @@ static const struct platform_device_id davinci_psc_id_table[] = {
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM365
|
||||
{ .name = "dm365-psc", .driver_data = (kernel_ulong_t)&dm365_psc_init_data },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM644x
|
||||
{ .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM646x
|
||||
{ .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
@ -110,11 +110,5 @@ extern const struct davinci_psc_init_data dm355_psc_init_data;
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM365
|
||||
extern const struct davinci_psc_init_data dm365_psc_init_data;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM644x
|
||||
extern const struct davinci_psc_init_data dm644x_psc_init_data;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM646x
|
||||
extern const struct davinci_psc_init_data dm646x_psc_init_data;
|
||||
#endif
|
||||
|
||||
#endif /* __CLK_DAVINCI_PSC_H__ */
|
||||
|
||||
@ -28,13 +28,5 @@ int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgch
|
||||
int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm365_psc_init(struct device *dev, void __iomem *base);
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM644x
|
||||
int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm644x_psc_init(struct device *dev, void __iomem *base);
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DM646x
|
||||
int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm646x_psc_init(struct device *dev, void __iomem *base);
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user