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drm/i915/skl+: Check for supported plane configuration in Interlace mode
In Gen9 platform Interlaced fetch mode doesn't support following plane configuration: - Y/Yf tiling - 90/270 rotation - YUV420 hybrid planar source pixel formats. This patch adds check to fail the flip if any of the above configuration is requested. Changes since V1: - handle checks in intel_plane_atomic_check_with_state (ville) - takeout plane scaler checks combile with pipe scaler in next patch Changes since V2: - No need to check for NV12 as it need scaling, so it will be rejected by scaling check (ville) Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170630121100.20159-2-mahesh1.kumar@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90238 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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@ -114,6 +114,8 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
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struct drm_i915_private *dev_priv = to_i915(plane->dev);
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struct drm_plane_state *state = &intel_state->base;
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struct intel_plane *intel_plane = to_intel_plane(plane);
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->base.adjusted_mode;
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int ret;
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/*
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@ -173,6 +175,19 @@ int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
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if (ret)
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return ret;
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/*
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* Y-tiling is not supported in IF-ID Interlace mode in
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* GEN9 and above.
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*/
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if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
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adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
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state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
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DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
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return -EINVAL;
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}
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}
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/* FIXME pre-g4x don't work like this */
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if (intel_state->base.visible)
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crtc_state->active_planes |= BIT(intel_plane->id);
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