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mailbox: imx: add i.MX8 SECO MU support
i.MX8/8X SECO firmware IPC is an implementation of passing messages.
But current imx-mailbox driver only support one word message,
i.MX8/8X linux side firmware has to request four TX, four RX and a
TXDB to support IPC to SECO firmware. This is low efficent and
more interrupts triggered compared with one TX and one RX.
To make SECO MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg of any size, limited by hardcoded value
of 30.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Franck LENORMAND
Jassi Brar
parent
315d2e5624
commit
11dac1d3fa
@ -9,6 +9,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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@ -24,6 +25,9 @@
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#define IMX_MU_S4_CHANS 2
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#define IMX_MU_CHAN_NAME_SIZE 20
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#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
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#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
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enum imx_mu_chan_type {
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IMX_MU_TYPE_TX, /* Tx */
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IMX_MU_TYPE_RX, /* Rx */
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@ -48,7 +52,7 @@ enum imx_mu_xsr {
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struct imx_sc_rpc_msg_max {
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struct imx_sc_rpc_msg hdr;
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u32 data[7];
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u32 data[30];
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};
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struct imx_s4_rpc_msg_max {
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@ -131,6 +135,55 @@ static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
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return ioread32(priv->base + offs);
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}
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static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
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{
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u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
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u32 status;
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u32 can_write;
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dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
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can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
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} while (!can_write && time_is_after_jiffies64(timeout_time));
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if (!can_write) {
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dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
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val, idx, status);
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return -ETIME;
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}
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imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
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return 0;
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}
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static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
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{
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u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
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u32 status;
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u32 can_read;
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dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
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can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
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} while (!can_read && time_is_after_jiffies64(timeout_time));
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if (!can_read) {
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dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
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idx, status);
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return -ETIME;
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}
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*val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
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dev_dbg(priv->dev, "Read %.8x\n", *val);
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return 0;
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}
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static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
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{
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unsigned long flags;
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@ -289,6 +342,125 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
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return 0;
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}
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static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
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void *data)
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{
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struct imx_sc_rpc_msg_max *msg = data;
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u32 *arg = data;
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u32 byte_size;
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int err;
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int i;
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dev_dbg(priv->dev, "Sending message\n");
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switch (cp->type) {
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case IMX_MU_TYPE_TXDB:
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byte_size = msg->hdr.size * sizeof(u32);
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if (byte_size > sizeof(*msg)) {
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/*
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* The real message size can be different to
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* struct imx_sc_rpc_msg_max size
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*/
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dev_err(priv->dev,
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"Exceed max msg size (%zu) on TX, got: %i\n",
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sizeof(*msg), byte_size);
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return -EINVAL;
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}
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print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
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data, byte_size, false);
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/* Send first word */
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dev_dbg(priv->dev, "Sending header\n");
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imx_mu_write(priv, *arg++, priv->dcfg->xTR);
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/* Send signaling */
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dev_dbg(priv->dev, "Sending signaling\n");
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imx_mu_xcr_rmw(priv, IMX_MU_GCR,
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IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
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/* Send words to fill the mailbox */
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for (i = 1; i < 4 && i < msg->hdr.size; i++) {
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dev_dbg(priv->dev, "Sending word %d\n", i);
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imx_mu_write(priv, *arg++,
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priv->dcfg->xTR + (i % 4) * 4);
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}
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/* Send rest of message waiting for remote read */
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for (; i < msg->hdr.size; i++) {
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dev_dbg(priv->dev, "Sending word %d\n", i);
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err = imx_mu_tx_waiting_write(priv, *arg++, i);
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if (err) {
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dev_err(priv->dev, "Timeout tx %d\n", i);
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return err;
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}
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}
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/* Simulate hack for mbox framework */
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev,
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"Send data on wrong channel type: %d\n",
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cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
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{
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struct imx_sc_rpc_msg_max msg;
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u32 *data = (u32 *)&msg;
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u32 byte_size;
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int err = 0;
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int i;
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dev_dbg(priv->dev, "Receiving message\n");
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/* Read header */
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dev_dbg(priv->dev, "Receiving header\n");
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*data++ = imx_mu_read(priv, priv->dcfg->xRR);
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byte_size = msg.hdr.size * sizeof(u32);
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if (byte_size > sizeof(msg)) {
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dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
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sizeof(msg), byte_size);
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err = -EINVAL;
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goto error;
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}
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/* Read message waiting they are written */
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for (i = 1; i < msg.hdr.size; i++) {
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dev_dbg(priv->dev, "Receiving word %d\n", i);
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err = imx_mu_rx_waiting_read(priv, data++, i);
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if (err) {
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dev_err(priv->dev, "Timeout rx %d\n", i);
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goto error;
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}
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}
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/* Clear GIP */
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imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
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priv->dcfg->xSR[IMX_MU_GSR]);
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print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
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&msg, byte_size, false);
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/* send data to client */
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dev_dbg(priv->dev, "Sending message to client\n");
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mbox_chan_received_data(cp->chan, (void *)&msg);
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goto exit;
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error:
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mbox_chan_received_data(cp->chan, ERR_PTR(err));
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exit:
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return err;
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}
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static void imx_mu_txdb_tasklet(unsigned long data)
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{
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struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
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@ -494,6 +666,27 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
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return &mbox->chans[chan];
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}
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static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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{
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u32 type;
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if (sp->args_count < 1) {
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dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
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return ERR_PTR(-EINVAL);
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}
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type = sp->args[0]; /* channel type */
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/* Only supports TXDB and RXDB */
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if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
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dev_err(mbox->dev, "Invalid type: %d\n", type);
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return ERR_PTR(-EINVAL);
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}
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return imx_mu_xlate(mbox, sp);
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}
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static void imx_mu_init_generic(struct imx_mu_priv *priv)
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{
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unsigned int i;
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@ -544,6 +737,12 @@ static void imx_mu_init_specific(struct imx_mu_priv *priv)
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imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
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}
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static void imx_mu_init_seco(struct imx_mu_priv *priv)
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{
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imx_mu_init_generic(priv);
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priv->mbox.of_xlate = imx_mu_seco_xlate;
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}
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static int imx_mu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -702,12 +901,24 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
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.xCR = {0x24, 0x24, 0x24, 0x24},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
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.tx = imx_mu_seco_tx,
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.rx = imx_mu_generic_rx,
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.rxdb = imx_mu_seco_rxdb,
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.init = imx_mu_init_seco,
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.xTR = 0x0,
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.xRR = 0x10,
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.xSR = {0x20, 0x20, 0x20, 0x20},
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.xCR = {0x24, 0x24, 0x24, 0x24},
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};
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
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{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
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{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
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{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
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