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i2c: qup: New bus driver for the Qualcomm QUP I2C controller
This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs. The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path engine with input/output FIFOs and an embedded i2c mini-core. The driver supports FIFO mode (for low bandwidth applications) and block mode (interrupt generated for each block-size data transfer). Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Andy Gross <agross@codeaurora.org> Tested-by: Philip Elcan <pelcan@codeaurora.org> [wsa: removed needless IS_ERR_VALUE] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Bjorn Andersson
Wolfram Sang
parent
6128440502
commit
10c5a84259
@ -656,6 +656,16 @@ config I2C_PXA_SLAVE
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is necessary for systems where the PXA may be a target on the
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I2C bus.
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config I2C_QUP
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tristate "Qualcomm QUP based I2C controller"
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depends on ARCH_QCOM
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help
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If you say yes to this option, support will be included for the
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built-in I2C interface on the Qualcomm SoCs.
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This driver can also be built as a module. If so, the module
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will be called i2c-qup.
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config I2C_RIIC
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tristate "Renesas RIIC adapter"
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depends on ARCH_SHMOBILE || COMPILE_TEST
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@ -64,6 +64,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
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obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
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obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
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obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
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obj-$(CONFIG_I2C_QUP) += i2c-qup.o
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obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
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obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
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obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
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768
drivers/i2c/busses/i2c-qup.c
Normal file
768
drivers/i2c/busses/i2c-qup.c
Normal file
@ -0,0 +1,768 @@
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/*
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* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014, Sony Mobile Communications AB.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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/* QUP Registers */
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#define QUP_CONFIG 0x000
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#define QUP_STATE 0x004
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#define QUP_IO_MODE 0x008
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#define QUP_SW_RESET 0x00c
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#define QUP_OPERATIONAL 0x018
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#define QUP_ERROR_FLAGS 0x01c
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#define QUP_ERROR_FLAGS_EN 0x020
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#define QUP_HW_VERSION 0x030
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#define QUP_MX_OUTPUT_CNT 0x100
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#define QUP_OUT_FIFO_BASE 0x110
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#define QUP_MX_WRITE_CNT 0x150
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#define QUP_MX_INPUT_CNT 0x200
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#define QUP_MX_READ_CNT 0x208
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#define QUP_IN_FIFO_BASE 0x218
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#define QUP_I2C_CLK_CTL 0x400
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#define QUP_I2C_STATUS 0x404
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/* QUP States and reset values */
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#define QUP_RESET_STATE 0
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#define QUP_RUN_STATE 1
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#define QUP_PAUSE_STATE 3
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#define QUP_STATE_MASK 3
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#define QUP_STATE_VALID BIT(2)
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#define QUP_I2C_MAST_GEN BIT(4)
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#define QUP_OPERATIONAL_RESET 0x000ff0
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#define QUP_I2C_STATUS_RESET 0xfffffc
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/* QUP OPERATIONAL FLAGS */
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#define QUP_I2C_NACK_FLAG BIT(3)
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#define QUP_OUT_NOT_EMPTY BIT(4)
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#define QUP_IN_NOT_EMPTY BIT(5)
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#define QUP_OUT_FULL BIT(6)
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#define QUP_OUT_SVC_FLAG BIT(8)
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#define QUP_IN_SVC_FLAG BIT(9)
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#define QUP_MX_OUTPUT_DONE BIT(10)
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#define QUP_MX_INPUT_DONE BIT(11)
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/* I2C mini core related values */
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#define QUP_CLOCK_AUTO_GATE BIT(13)
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#define I2C_MINI_CORE (2 << 8)
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#define I2C_N_VAL 15
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/* Most significant word offset in FIFO port */
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#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
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/* Packing/Unpacking words in FIFOs, and IO modes */
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#define QUP_OUTPUT_BLK_MODE (1 << 10)
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#define QUP_INPUT_BLK_MODE (1 << 12)
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#define QUP_UNPACK_EN BIT(14)
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#define QUP_PACK_EN BIT(15)
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#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
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#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
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#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
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#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
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#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
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/* QUP tags */
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#define QUP_TAG_START (1 << 8)
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#define QUP_TAG_DATA (2 << 8)
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#define QUP_TAG_STOP (3 << 8)
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#define QUP_TAG_REC (4 << 8)
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/* Status, Error flags */
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#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
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#define I2C_STATUS_BUS_ACTIVE BIT(8)
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#define I2C_STATUS_ERROR_MASK 0x38000fc
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#define QUP_STATUS_ERROR_FLAGS 0x7c
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#define QUP_READ_LIMIT 256
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struct qup_i2c_dev {
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struct device *dev;
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void __iomem *base;
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int irq;
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struct clk *clk;
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struct clk *pclk;
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struct i2c_adapter adap;
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int clk_ctl;
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int out_fifo_sz;
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int in_fifo_sz;
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int out_blk_sz;
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int in_blk_sz;
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unsigned long one_byte_t;
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struct i2c_msg *msg;
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/* Current posion in user message buffer */
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int pos;
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/* I2C protocol errors */
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u32 bus_err;
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/* QUP core errors */
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u32 qup_err;
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struct completion xfer;
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};
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static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
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{
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struct qup_i2c_dev *qup = dev;
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u32 bus_err;
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u32 qup_err;
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u32 opflags;
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bus_err = readl(qup->base + QUP_I2C_STATUS);
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qup_err = readl(qup->base + QUP_ERROR_FLAGS);
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opflags = readl(qup->base + QUP_OPERATIONAL);
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if (!qup->msg) {
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/* Clear Error interrupt */
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writel(QUP_RESET_STATE, qup->base + QUP_STATE);
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return IRQ_HANDLED;
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}
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bus_err &= I2C_STATUS_ERROR_MASK;
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qup_err &= QUP_STATUS_ERROR_FLAGS;
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if (qup_err) {
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/* Clear Error interrupt */
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writel(qup_err, qup->base + QUP_ERROR_FLAGS);
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goto done;
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}
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if (bus_err) {
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/* Clear Error interrupt */
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writel(QUP_RESET_STATE, qup->base + QUP_STATE);
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goto done;
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}
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if (opflags & QUP_IN_SVC_FLAG)
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writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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if (opflags & QUP_OUT_SVC_FLAG)
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writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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done:
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qup->qup_err = qup_err;
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qup->bus_err = bus_err;
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complete(&qup->xfer);
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return IRQ_HANDLED;
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}
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static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
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u32 req_state, u32 req_mask)
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{
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int retries = 1;
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u32 state;
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/*
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* State transition takes 3 AHB clocks cycles + 3 I2C master clock
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* cycles. So retry once after a 1uS delay.
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*/
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do {
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state = readl(qup->base + QUP_STATE);
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if (state & QUP_STATE_VALID &&
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(state & req_mask) == req_state)
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return 0;
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udelay(1);
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} while (retries--);
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return -ETIMEDOUT;
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}
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static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
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{
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return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
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}
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static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
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{
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return qup_i2c_poll_state_mask(qup, 0, 0);
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}
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static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
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{
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return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
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}
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static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
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{
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if (qup_i2c_poll_state_valid(qup) != 0)
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return -EIO;
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writel(state, qup->base + QUP_STATE);
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if (qup_i2c_poll_state(qup, state) != 0)
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return -EIO;
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return 0;
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}
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static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)
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{
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unsigned long timeout;
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u32 opflags;
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u32 status;
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timeout = jiffies + HZ;
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for (;;) {
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opflags = readl(qup->base + QUP_OPERATIONAL);
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status = readl(qup->base + QUP_I2C_STATUS);
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if (!(opflags & QUP_OUT_NOT_EMPTY) &&
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!(status & I2C_STATUS_BUS_ACTIVE))
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return 0;
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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usleep_range(qup->one_byte_t, qup->one_byte_t * 2);
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}
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}
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static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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/* Number of entries to shift out, including the start */
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int total = msg->len + 1;
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if (total < qup->out_fifo_sz) {
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/* FIFO mode */
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writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
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writel(total, qup->base + QUP_MX_WRITE_CNT);
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} else {
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/* BLOCK mode (transfer data on chunks) */
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writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
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qup->base + QUP_IO_MODE);
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writel(total, qup->base + QUP_MX_OUTPUT_CNT);
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}
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}
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static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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u32 addr = msg->addr << 1;
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u32 qup_tag;
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u32 opflags;
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int idx;
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u32 val;
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if (qup->pos == 0) {
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val = QUP_TAG_START | addr;
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idx = 1;
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} else {
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val = 0;
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idx = 0;
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}
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while (qup->pos < msg->len) {
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/* Check that there's space in the FIFO for our pair */
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opflags = readl(qup->base + QUP_OPERATIONAL);
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if (opflags & QUP_OUT_FULL)
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break;
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if (qup->pos == msg->len - 1)
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qup_tag = QUP_TAG_STOP;
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else
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qup_tag = QUP_TAG_DATA;
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if (idx & 1)
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val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
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else
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val = qup_tag | msg->buf[qup->pos];
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/* Write out the pair and the last odd value */
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if (idx & 1 || qup->pos == msg->len - 1)
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writel(val, qup->base + QUP_OUT_FIFO_BASE);
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qup->pos++;
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idx++;
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}
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}
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static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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unsigned long left;
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int ret;
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qup->msg = msg;
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qup->pos = 0;
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enable_irq(qup->irq);
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qup_i2c_set_write_mode(qup, msg);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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goto err;
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writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
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do {
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ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
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if (ret)
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goto err;
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qup_i2c_issue_write(qup, msg);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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goto err;
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left = wait_for_completion_timeout(&qup->xfer, HZ);
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if (!left) {
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writel(1, qup->base + QUP_SW_RESET);
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ret = -ETIMEDOUT;
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goto err;
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}
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if (qup->bus_err || qup->qup_err) {
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if (qup->bus_err & QUP_I2C_NACK_FLAG)
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dev_err(qup->dev, "NACK from %x\n", msg->addr);
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ret = -EIO;
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goto err;
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}
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} while (qup->pos < msg->len);
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/* Wait for the outstanding data in the fifo to drain */
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ret = qup_i2c_wait_writeready(qup);
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err:
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disable_irq(qup->irq);
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qup->msg = NULL;
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return ret;
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}
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static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
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{
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if (len < qup->in_fifo_sz) {
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/* FIFO mode */
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writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
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writel(len, qup->base + QUP_MX_READ_CNT);
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} else {
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/* BLOCK mode (transfer data on chunks) */
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writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
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qup->base + QUP_IO_MODE);
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writel(len, qup->base + QUP_MX_INPUT_CNT);
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}
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}
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static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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u32 addr, len, val;
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addr = (msg->addr << 1) | 1;
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/* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
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len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
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val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
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writel(val, qup->base + QUP_OUT_FIFO_BASE);
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}
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static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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u32 opflags;
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u32 val = 0;
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int idx;
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for (idx = 0; qup->pos < msg->len; idx++) {
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if ((idx & 1) == 0) {
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/* Check that FIFO have data */
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opflags = readl(qup->base + QUP_OPERATIONAL);
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if (!(opflags & QUP_IN_NOT_EMPTY))
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break;
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/* Reading 2 words at time */
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val = readl(qup->base + QUP_IN_FIFO_BASE);
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msg->buf[qup->pos++] = val & 0xFF;
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} else {
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msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
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}
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}
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}
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static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
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{
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unsigned long left;
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int ret;
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/*
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* The QUP block will issue a NACK and STOP on the bus when reaching
|
||||
* the end of the read, the length of the read is specified as one byte
|
||||
* which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
|
||||
*/
|
||||
if (msg->len > QUP_READ_LIMIT) {
|
||||
dev_err(qup->dev, "HW not capable of reads over %d bytes\n",
|
||||
QUP_READ_LIMIT);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
qup->msg = msg;
|
||||
qup->pos = 0;
|
||||
|
||||
enable_irq(qup->irq);
|
||||
|
||||
qup_i2c_set_read_mode(qup, msg->len);
|
||||
|
||||
ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
|
||||
|
||||
ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
qup_i2c_issue_read(qup, msg);
|
||||
|
||||
ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
do {
|
||||
left = wait_for_completion_timeout(&qup->xfer, HZ);
|
||||
if (!left) {
|
||||
writel(1, qup->base + QUP_SW_RESET);
|
||||
ret = -ETIMEDOUT;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (qup->bus_err || qup->qup_err) {
|
||||
if (qup->bus_err & QUP_I2C_NACK_FLAG)
|
||||
dev_err(qup->dev, "NACK from %x\n", msg->addr);
|
||||
ret = -EIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
qup_i2c_read_fifo(qup, msg);
|
||||
} while (qup->pos < msg->len);
|
||||
|
||||
err:
|
||||
disable_irq(qup->irq);
|
||||
qup->msg = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qup_i2c_xfer(struct i2c_adapter *adap,
|
||||
struct i2c_msg msgs[],
|
||||
int num)
|
||||
{
|
||||
struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
|
||||
int ret, idx;
|
||||
|
||||
ret = pm_runtime_get_sync(qup->dev);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
writel(1, qup->base + QUP_SW_RESET);
|
||||
ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Configure QUP as I2C mini core */
|
||||
writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
|
||||
|
||||
for (idx = 0; idx < num; idx++) {
|
||||
if (msgs[idx].len == 0) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (qup_i2c_poll_state_i2c_master(qup)) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (msgs[idx].flags & I2C_M_RD)
|
||||
ret = qup_i2c_read_one(qup, &msgs[idx]);
|
||||
else
|
||||
ret = qup_i2c_write_one(qup, &msgs[idx]);
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret == 0)
|
||||
ret = num;
|
||||
out:
|
||||
|
||||
pm_runtime_mark_last_busy(qup->dev);
|
||||
pm_runtime_put_autosuspend(qup->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 qup_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm qup_i2c_algo = {
|
||||
.master_xfer = qup_i2c_xfer,
|
||||
.functionality = qup_i2c_func,
|
||||
};
|
||||
|
||||
static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
|
||||
{
|
||||
clk_prepare_enable(qup->clk);
|
||||
clk_prepare_enable(qup->pclk);
|
||||
}
|
||||
|
||||
static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
|
||||
{
|
||||
u32 config;
|
||||
|
||||
qup_i2c_change_state(qup, QUP_RESET_STATE);
|
||||
clk_disable_unprepare(qup->clk);
|
||||
config = readl(qup->base + QUP_CONFIG);
|
||||
config |= QUP_CLOCK_AUTO_GATE;
|
||||
writel(config, qup->base + QUP_CONFIG);
|
||||
clk_disable_unprepare(qup->pclk);
|
||||
}
|
||||
|
||||
static int qup_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
static const int blk_sizes[] = {4, 16, 32};
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct qup_i2c_dev *qup;
|
||||
unsigned long one_bit_t;
|
||||
struct resource *res;
|
||||
u32 io_mode, hw_ver, size;
|
||||
int ret, fs_div, hs_div;
|
||||
int src_clk_freq;
|
||||
int clk_freq = 100000;
|
||||
|
||||
qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
|
||||
if (!qup)
|
||||
return -ENOMEM;
|
||||
|
||||
qup->dev = &pdev->dev;
|
||||
init_completion(&qup->xfer);
|
||||
platform_set_drvdata(pdev, qup);
|
||||
|
||||
of_property_read_u32(node, "clock-frequency", &clk_freq);
|
||||
|
||||
/* We support frequencies up to FAST Mode (400KHz) */
|
||||
if (!clk_freq || clk_freq > 400000) {
|
||||
dev_err(qup->dev, "clock frequency not supported %d\n",
|
||||
clk_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
qup->base = devm_ioremap_resource(qup->dev, res);
|
||||
if (IS_ERR(qup->base))
|
||||
return PTR_ERR(qup->base);
|
||||
|
||||
qup->irq = platform_get_irq(pdev, 0);
|
||||
if (qup->irq < 0) {
|
||||
dev_err(qup->dev, "No IRQ defined\n");
|
||||
return qup->irq;
|
||||
}
|
||||
|
||||
qup->clk = devm_clk_get(qup->dev, "core");
|
||||
if (IS_ERR(qup->clk)) {
|
||||
dev_err(qup->dev, "Could not get core clock\n");
|
||||
return PTR_ERR(qup->clk);
|
||||
}
|
||||
|
||||
qup->pclk = devm_clk_get(qup->dev, "iface");
|
||||
if (IS_ERR(qup->pclk)) {
|
||||
dev_err(qup->dev, "Could not get iface clock\n");
|
||||
return PTR_ERR(qup->pclk);
|
||||
}
|
||||
|
||||
qup_i2c_enable_clocks(qup);
|
||||
|
||||
/*
|
||||
* Bootloaders might leave a pending interrupt on certain QUP's,
|
||||
* so we reset the core before registering for interrupts.
|
||||
*/
|
||||
writel(1, qup->base + QUP_SW_RESET);
|
||||
ret = qup_i2c_poll_state_valid(qup);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
|
||||
IRQF_TRIGGER_HIGH, "i2c_qup", qup);
|
||||
if (ret) {
|
||||
dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
|
||||
goto fail;
|
||||
}
|
||||
disable_irq(qup->irq);
|
||||
|
||||
hw_ver = readl(qup->base + QUP_HW_VERSION);
|
||||
dev_dbg(qup->dev, "Revision %x\n", hw_ver);
|
||||
|
||||
io_mode = readl(qup->base + QUP_IO_MODE);
|
||||
|
||||
/*
|
||||
* The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
|
||||
* associated with each byte written/received
|
||||
*/
|
||||
size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
|
||||
if (size > ARRAY_SIZE(blk_sizes))
|
||||
return -EIO;
|
||||
qup->out_blk_sz = blk_sizes[size] / 2;
|
||||
|
||||
size = QUP_INPUT_BLOCK_SIZE(io_mode);
|
||||
if (size > ARRAY_SIZE(blk_sizes))
|
||||
return -EIO;
|
||||
qup->in_blk_sz = blk_sizes[size] / 2;
|
||||
|
||||
size = QUP_OUTPUT_FIFO_SIZE(io_mode);
|
||||
qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
|
||||
|
||||
size = QUP_INPUT_FIFO_SIZE(io_mode);
|
||||
qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
|
||||
|
||||
src_clk_freq = clk_get_rate(qup->clk);
|
||||
fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
|
||||
hs_div = 3;
|
||||
qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
|
||||
|
||||
/*
|
||||
* Time it takes for a byte to be clocked out on the bus.
|
||||
* Each byte takes 9 clock cycles (8 bits + 1 ack).
|
||||
*/
|
||||
one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
|
||||
qup->one_byte_t = one_bit_t * 9;
|
||||
|
||||
dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
|
||||
qup->in_blk_sz, qup->in_fifo_sz,
|
||||
qup->out_blk_sz, qup->out_fifo_sz);
|
||||
|
||||
i2c_set_adapdata(&qup->adap, qup);
|
||||
qup->adap.algo = &qup_i2c_algo;
|
||||
qup->adap.dev.parent = qup->dev;
|
||||
qup->adap.dev.of_node = pdev->dev.of_node;
|
||||
strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
|
||||
|
||||
ret = i2c_add_adapter(&qup->adap);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
|
||||
pm_runtime_use_autosuspend(qup->dev);
|
||||
pm_runtime_set_active(qup->dev);
|
||||
pm_runtime_enable(qup->dev);
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
qup_i2c_disable_clocks(qup);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qup_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
|
||||
|
||||
disable_irq(qup->irq);
|
||||
qup_i2c_disable_clocks(qup);
|
||||
i2c_del_adapter(&qup->adap);
|
||||
pm_runtime_disable(qup->dev);
|
||||
pm_runtime_set_suspended(qup->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int qup_i2c_pm_suspend_runtime(struct device *device)
|
||||
{
|
||||
struct qup_i2c_dev *qup = dev_get_drvdata(device);
|
||||
|
||||
dev_dbg(device, "pm_runtime: suspending...\n");
|
||||
qup_i2c_disable_clocks(qup);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qup_i2c_pm_resume_runtime(struct device *device)
|
||||
{
|
||||
struct qup_i2c_dev *qup = dev_get_drvdata(device);
|
||||
|
||||
dev_dbg(device, "pm_runtime: resuming...\n");
|
||||
qup_i2c_enable_clocks(qup);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int qup_i2c_suspend(struct device *device)
|
||||
{
|
||||
qup_i2c_pm_suspend_runtime(device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qup_i2c_resume(struct device *device)
|
||||
{
|
||||
qup_i2c_pm_resume_runtime(device);
|
||||
pm_runtime_mark_last_busy(device);
|
||||
pm_request_autosuspend(device);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(
|
||||
qup_i2c_suspend,
|
||||
qup_i2c_resume)
|
||||
SET_RUNTIME_PM_OPS(
|
||||
qup_i2c_pm_suspend_runtime,
|
||||
qup_i2c_pm_resume_runtime,
|
||||
NULL)
|
||||
};
|
||||
|
||||
static const struct of_device_id qup_i2c_dt_match[] = {
|
||||
{ .compatible = "qcom,i2c-qup-v1.1.1" },
|
||||
{ .compatible = "qcom,i2c-qup-v2.1.1" },
|
||||
{ .compatible = "qcom,i2c-qup-v2.2.1" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
|
||||
|
||||
static struct platform_driver qup_i2c_driver = {
|
||||
.probe = qup_i2c_probe,
|
||||
.remove = qup_i2c_remove,
|
||||
.driver = {
|
||||
.name = "i2c_qup",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &qup_i2c_qup_pm_ops,
|
||||
.of_match_table = qup_i2c_dt_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(qup_i2c_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:i2c_qup");
|
||||
Loading…
Reference in New Issue
Block a user