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Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued

Browse Source 
Backmerge drm-next for the reworked device register/unregistering.
Chris Wilson needs that to be able to land his i915 load/unload
demidlayering.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter 2016-06-24 08:29:45 +02:00
commit 10bb667223
134 changed files with 10228 additions and 4868 deletions
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2
Documentation/DocBook/Makefile
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@ -14,7 +14,7 @@ DOCBOOKS := z8530book.xml device-drivers.xml \
genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \
80211.xml debugobjects.xml sh.xml regulator.xml \
alsa-driver-api.xml writing-an-alsa-driver.xml \
tracepoint.xml gpu.xml media_api.xml w1.xml \
tracepoint.xml media_api.xml w1.xml \
writing_musb_glue_layer.xml crypto-API.xml iio.xml
include Documentation/DocBook/media/Makefile

3528
Documentation/DocBook/gpu.tmpl
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65
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ARM Mali-DP
The following bindings apply to a family of Display Processors sold as
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
DP650 processors that offer multiple composition layers, support for
rotation and scaling output.
Required properties:
- compatible: should be one of
"arm,mali-dp500"
"arm,mali-dp550"
"arm,mali-dp650"
depending on the particular implementation present in the hardware
- reg: Physical base address and size of the block of registers used by
the processor.
- interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
interrupt client nodes.
- interrupt-names: name of the engine inside the processor that will
use the corresponding interrupt. Should be one of "DE" or "SE".
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "pclk": for the APB interface clock
- "aclk": for the AXI interface clock
- "mclk": for the main processor clock
- "pxlclk": for the pixel clock feeding the output PLL of the processor.
- arm,malidp-output-port-lines: Array of u8 values describing the number
of output lines per channel (R, G and B).
Required sub-nodes:
- port: The Mali DP connection to an encoder input port. The connection
is modelled using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
Example:
/ {
...
dp0: malidp@6f200000 {
compatible = "arm,mali-dp650";
reg = <0 0x6f200000 0 0x20000>;
memory-region = <&display_reserved>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
<0 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;
};
};
};
...
};

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sii902x HDMI bridge bindings
Required properties:
- compatible: "sil,sii9022"
- reg: i2c address of the bridge
Optional properties:
- interrupts-extended or interrupt-parent + interrupts: describe
the interrupt line used to inform the host about hotplug events.
- reset-gpios: OF device-tree gpio specification for RST_N pin.
Optional subnodes:
- video input: this subnode can contain a video input port node
to connect the bridge to a display controller output (See this
documentation [1]).
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
hdmi-bridge@39 {
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&pioA 1 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&dc_out>;
};
};
};
};

1
Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
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@ -8,6 +8,7 @@ Required properties:
Optional properties:
- label: a symbolic name for the connector
- hpd-gpios: HPD GPIO number
- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
Required nodes:
- Video port for HDMI input

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Mediatek HDMI Encoder
=====================
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
its parallel input.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
- phys: phandle link to the HDMI PHY node.
See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
- phy-names: must contain "hdmi"
- mediatek,syscon-hdmi: phandle link and register offset to the system
configuration registers. For mt8173 this must be offset 0x900 into the
MMSYS_CONFIG region: <&mmsys 0x900>.
- ports: A node containing input and output port nodes with endpoint
definitions as documented in Documentation/devicetree/bindings/graph.txt.
- port@0: The input port in the ports node should be connected to a DPI output
port.
- port@1: The output port in the ports node should be connected to the input
port of a connector node that contains a ddc-i2c-bus property, or to the
input port of an attached bridge chip, such as a SlimPort transmitter.
HDMI CEC
========
The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties:
- compatible: Should be "mediatek,<chip>-cec"
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
HDMI DDC
========
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
HDMI PHY
========
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
- clock-output-names: must be "hdmitx_dig_cts" on mt8173
- #phy-cells: must be <0>
- #clock-cells: must be <0>
Optional properties:
- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
Example:
cec: cec@10013000 {
compatible = "mediatek,mt8173-cec";
reg = <0 0x10013000 0 0xbc>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_CEC>;
};
hdmi_phy: hdmi-phy@10209100 {
compatible = "mediatek,mt8173-hdmi-phy";
reg = <0 0x10209100 0 0x24>;
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
clock-output-names = "hdmitx_dig_cts";
mediatek,ibias = <0xa>;
mediatek,ibias_up = <0x1c>;
#clock-cells = <0>;
#phy-cells = <0>;
};
hdmi_ddc0: i2c@11012000 {
compatible = "mediatek,mt8173-hdmi-ddc";
reg = <0 0x11012000 0 0x1c>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_I2C5>;
clock-names = "ddc-i2c";
};
hdmi0: hdmi@14025000 {
compatible = "mediatek,mt8173-hdmi";
reg = <0 0x14025000 0 0x400>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
<&mmsys CLK_MM_HDMI_PLLCK>,
<&mmsys CLK_MM_HDMI_AUDIO>,
<&mmsys CLK_MM_HDMI_SPDIF>;
clock-names = "pixel", "pll", "bclk", "spdif";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pin>;
phys = <&hdmi_phy>;
phy-names = "hdmi";
mediatek,syscon-hdmi = <&mmsys 0x900>;
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
assigned-clock-parents = <&hdmi_phy>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
port@1 {
reg = <1>;
hdmi0_out: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
};
};
connector {
compatible = "hdmi-connector";
type = "a";
ddc-i2c-bus = <&hdmiddc0>;
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi0_out>;
};
};
};

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=============
DRM Internals
=============
This chapter documents DRM internals relevant to driver authors and
developers working to add support for the latest features to existing
drivers.
First, we go over some typical driver initialization requirements, like
setting up command buffers, creating an initial output configuration,
and initializing core services. Subsequent sections cover core internals
in more detail, providing implementation notes and examples.
The DRM layer provides several services to graphics drivers, many of
them driven by the application interfaces it provides through libdrm,
the library that wraps most of the DRM ioctls. These include vblank
event handling, memory management, output management, framebuffer
management, command submission & fencing, suspend/resume support, and
DMA services.
Driver Initialization
=====================
At the core of every DRM driver is a :c:type:`struct drm_driver
<drm_driver>` structure. Drivers typically statically initialize
a drm_driver structure, and then pass it to
:c:func:`drm_dev_alloc()` to allocate a device instance. After the
device instance is fully initialized it can be registered (which makes
it accessible from userspace) using :c:func:`drm_dev_register()`.
The :c:type:`struct drm_driver <drm_driver>` structure
contains static information that describes the driver and features it
supports, and pointers to methods that the DRM core will call to
implement the DRM API. We will first go through the :c:type:`struct
drm_driver <drm_driver>` static information fields, and will
then describe individual operations in details as they get used in later
sections.
Driver Information
------------------
Driver Features
~~~~~~~~~~~~~~~
Drivers inform the DRM core about their requirements and supported
features by setting appropriate flags in the driver_features field.
Since those flags influence the DRM core behaviour since registration
time, most of them must be set to registering the :c:type:`struct
drm_driver <drm_driver>` instance.
u32 driver_features;
DRIVER_USE_AGP
Driver uses AGP interface, the DRM core will manage AGP resources.
DRIVER_REQUIRE_AGP
Driver needs AGP interface to function. AGP initialization failure
will become a fatal error.
DRIVER_PCI_DMA
Driver is capable of PCI DMA, mapping of PCI DMA buffers to
userspace will be enabled. Deprecated.
DRIVER_SG
Driver can perform scatter/gather DMA, allocation and mapping of
scatter/gather buffers will be enabled. Deprecated.
DRIVER_HAVE_DMA
Driver supports DMA, the userspace DMA API will be supported.
Deprecated.
DRIVER_HAVE_IRQ; DRIVER_IRQ_SHARED
DRIVER_HAVE_IRQ indicates whether the driver has an IRQ handler
managed by the DRM Core. The core will support simple IRQ handler
installation when the flag is set. The installation process is
described in ?.
DRIVER_IRQ_SHARED indicates whether the device & handler support
shared IRQs (note that this is required of PCI drivers).
DRIVER_GEM
Driver use the GEM memory manager.
DRIVER_MODESET
Driver supports mode setting interfaces (KMS).
DRIVER_PRIME
Driver implements DRM PRIME buffer sharing.
DRIVER_RENDER
Driver supports dedicated render nodes.
DRIVER_ATOMIC
Driver supports atomic properties. In this case the driver must
implement appropriate obj->atomic_get_property() vfuncs for any
modeset objects with driver specific properties.
Major, Minor and Patchlevel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
int major; int minor; int patchlevel;
The DRM core identifies driver versions by a major, minor and patch
level triplet. The information is printed to the kernel log at
initialization time and passed to userspace through the
DRM_IOCTL_VERSION ioctl.
The major and minor numbers are also used to verify the requested driver
API version passed to DRM_IOCTL_SET_VERSION. When the driver API
changes between minor versions, applications can call
DRM_IOCTL_SET_VERSION to select a specific version of the API. If the
requested major isn't equal to the driver major, or the requested minor
is larger than the driver minor, the DRM_IOCTL_SET_VERSION call will
return an error. Otherwise the driver's set_version() method will be
called with the requested version.
Name, Description and Date
~~~~~~~~~~~~~~~~~~~~~~~~~~
char \*name; char \*desc; char \*date;
The driver name is printed to the kernel log at initialization time,
used for IRQ registration and passed to userspace through
DRM_IOCTL_VERSION.
The driver description is a purely informative string passed to
userspace through the DRM_IOCTL_VERSION ioctl and otherwise unused by
the kernel.
The driver date, formatted as YYYYMMDD, is meant to identify the date of
the latest modification to the driver. However, as most drivers fail to
update it, its value is mostly useless. The DRM core prints it to the
kernel log at initialization time and passes it to userspace through the
DRM_IOCTL_VERSION ioctl.
Device Instance and Driver Handling
-----------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_drv.c
:doc: driver instance overview
.. kernel-doc:: drivers/gpu/drm/drm_drv.c
:export:
Driver Load
-----------
IRQ Registration
~~~~~~~~~~~~~~~~
The DRM core tries to facilitate IRQ handler registration and
unregistration by providing :c:func:`drm_irq_install()` and
:c:func:`drm_irq_uninstall()` functions. Those functions only
support a single interrupt per device, devices that use more than one
IRQs need to be handled manually.
Managed IRQ Registration
''''''''''''''''''''''''
:c:func:`drm_irq_install()` starts by calling the irq_preinstall
driver operation. The operation is optional and must make sure that the
interrupt will not get fired by clearing all pending interrupt flags or
disabling the interrupt.
The passed-in IRQ will then be requested by a call to
:c:func:`request_irq()`. If the DRIVER_IRQ_SHARED driver feature
flag is set, a shared (IRQF_SHARED) IRQ handler will be requested.
The IRQ handler function must be provided as the mandatory irq_handler
driver operation. It will get passed directly to
:c:func:`request_irq()` and thus has the same prototype as all IRQ
handlers. It will get called with a pointer to the DRM device as the
second argument.
Finally the function calls the optional irq_postinstall driver
operation. The operation usually enables interrupts (excluding the
vblank interrupt, which is enabled separately), but drivers may choose
to enable/disable interrupts at a different time.
:c:func:`drm_irq_uninstall()` is similarly used to uninstall an
IRQ handler. It starts by waking up all processes waiting on a vblank
interrupt to make sure they don't hang, and then calls the optional
irq_uninstall driver operation. The operation must disable all hardware
interrupts. Finally the function frees the IRQ by calling
:c:func:`free_irq()`.
Manual IRQ Registration
'''''''''''''''''''''''
Drivers that require multiple interrupt handlers can't use the managed
IRQ registration functions. In that case IRQs must be registered and
unregistered manually (usually with the :c:func:`request_irq()` and
:c:func:`free_irq()` functions, or their devm_\* equivalent).
When manually registering IRQs, drivers must not set the
DRIVER_HAVE_IRQ driver feature flag, and must not provide the
irq_handler driver operation. They must set the :c:type:`struct
drm_device <drm_device>` irq_enabled field to 1 upon
registration of the IRQs, and clear it to 0 after unregistering the
IRQs.
Memory Manager Initialization
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Every DRM driver requires a memory manager which must be initialized at
load time. DRM currently contains two memory managers, the Translation
Table Manager (TTM) and the Graphics Execution Manager (GEM). This
document describes the use of the GEM memory manager only. See ? for
details.
Miscellaneous Device Configuration
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Another task that may be necessary for PCI devices during configuration
is mapping the video BIOS. On many devices, the VBIOS describes device
configuration, LCD panel timings (if any), and contains flags indicating
device state. Mapping the BIOS can be done using the pci_map_rom()
call, a convenience function that takes care of mapping the actual ROM,
whether it has been shadowed into memory (typically at address 0xc0000)
or exists on the PCI device in the ROM BAR. Note that after the ROM has
been mapped and any necessary information has been extracted, it should
be unmapped; on many devices, the ROM address decoder is shared with
other BARs, so leaving it mapped could cause undesired behaviour like
hangs or memory corruption.
Bus-specific Device Registration and PCI Support
------------------------------------------------
A number of functions are provided to help with device registration. The
functions deal with PCI and platform devices respectively and are only
provided for historical reasons. These are all deprecated and shouldn't
be used in new drivers. Besides that there's a few helpers for pci
drivers.
.. kernel-doc:: drivers/gpu/drm/drm_pci.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_platform.c
:export:
Open/Close, File Operations and IOCTLs
======================================
Open and Close
--------------
int (\*firstopen) (struct drm_device \*); void (\*lastclose) (struct
drm_device \*); int (\*open) (struct drm_device \*, struct drm_file
\*); void (\*preclose) (struct drm_device \*, struct drm_file \*);
void (\*postclose) (struct drm_device \*, struct drm_file \*);
Open and close handlers. None of those methods are mandatory.
The firstopen method is called by the DRM core for legacy UMS (User Mode
Setting) drivers only when an application opens a device that has no
other opened file handle. UMS drivers can implement it to acquire device
resources. KMS drivers can't use the method and must acquire resources
in the load method instead.
Similarly the lastclose method is called when the last application
holding a file handle opened on the device closes it, for both UMS and
KMS drivers. Additionally, the method is also called at module unload
time or, for hot-pluggable devices, when the device is unplugged. The
firstopen and lastclose calls can thus be unbalanced.
The open method is called every time the device is opened by an
application. Drivers can allocate per-file private data in this method
and store them in the struct :c:type:`struct drm_file
<drm_file>` driver_priv field. Note that the open method is
called before firstopen.
The close operation is split into preclose and postclose methods.
Drivers must stop and cleanup all per-file operations in the preclose
method. For instance pending vertical blanking and page flip events must
be cancelled. No per-file operation is allowed on the file handle after
returning from the preclose method.
Finally the postclose method is called as the last step of the close
operation, right before calling the lastclose method if no other open
file handle exists for the device. Drivers that have allocated per-file
private data in the open method should free it here.
The lastclose method should restore CRTC and plane properties to default
value, so that a subsequent open of the device will not inherit state
from the previous user. It can also be used to execute delayed power
switching state changes, e.g. in conjunction with the vga_switcheroo
infrastructure (see ?). Beyond that KMS drivers should not do any
further cleanup. Only legacy UMS drivers might need to clean up device
state so that the vga console or an independent fbdev driver could take
over.
File Operations
---------------
.. kernel-doc:: drivers/gpu/drm/drm_fops.c
:doc: file operations
.. kernel-doc:: drivers/gpu/drm/drm_fops.c
:export:
IOCTLs
------
struct drm_ioctl_desc \*ioctls; int num_ioctls;
Driver-specific ioctls descriptors table.
Driver-specific ioctls numbers start at DRM_COMMAND_BASE. The ioctls
descriptors table is indexed by the ioctl number offset from the base
value. Drivers can use the DRM_IOCTL_DEF_DRV() macro to initialize
the table entries.
::
DRM_IOCTL_DEF_DRV(ioctl, func, flags)
``ioctl`` is the ioctl name. Drivers must define the DRM_##ioctl and
DRM_IOCTL_##ioctl macros to the ioctl number offset from
DRM_COMMAND_BASE and the ioctl number respectively. The first macro is
private to the device while the second must be exposed to userspace in a
public header.
``func`` is a pointer to the ioctl handler function compatible with the
``drm_ioctl_t`` type.
::
typedef int drm_ioctl_t(struct drm_device *dev, void *data,
struct drm_file *file_priv);
``flags`` is a bitmask combination of the following values. It restricts
how the ioctl is allowed to be called.
- DRM_AUTH - Only authenticated callers allowed
- DRM_MASTER - The ioctl can only be called on the master file handle
- DRM_ROOT_ONLY - Only callers with the SYSADMIN capability allowed
- DRM_CONTROL_ALLOW - The ioctl can only be called on a control
device
- DRM_UNLOCKED - The ioctl handler will be called without locking the
DRM global mutex. This is the enforced default for kms drivers (i.e.
using the DRIVER_MODESET flag) and hence shouldn't be used any more
for new drivers.
.. kernel-doc:: drivers/gpu/drm/drm_ioctl.c
:export:
Legacy Support Code
===================
The section very briefly covers some of the old legacy support code
which is only used by old DRM drivers which have done a so-called
shadow-attach to the underlying device instead of registering as a real
driver. This also includes some of the old generic buffer management and
command submission code. Do not use any of this in new and modern
drivers.
Legacy Suspend/Resume
---------------------
The DRM core provides some suspend/resume code, but drivers wanting full
suspend/resume support should provide save() and restore() functions.
These are called at suspend, hibernate, or resume time, and should
perform any state save or restore required by your device across suspend
or hibernate states.
int (\*suspend) (struct drm_device \*, pm_message_t state); int
(\*resume) (struct drm_device \*);
Those are legacy suspend and resume methods which *only* work with the
legacy shadow-attach driver registration functions. New driver should
use the power management interface provided by their bus type (usually
through the :c:type:`struct device_driver <device_driver>`
dev_pm_ops) and set these methods to NULL.
Legacy DMA Services
-------------------
This should cover how DMA mapping etc. is supported by the core. These
functions are deprecated and should not be used.

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=============================
Mode Setting Helper Functions
=============================
The plane, CRTC, encoder and connector functions provided by the drivers
implement the DRM API. They're called by the DRM core and ioctl handlers
to handle device state changes and configuration request. As
implementing those functions often requires logic not specific to
drivers, mid-layer helper functions are available to avoid duplicating
boilerplate code.
The DRM core contains one mid-layer implementation. The mid-layer
provides implementations of several plane, CRTC, encoder and connector
functions (called from the top of the mid-layer) that pre-process
requests and call lower-level functions provided by the driver (at the
bottom of the mid-layer). For instance, the
:c:func:`drm_crtc_helper_set_config()` function can be used to
fill the :c:type:`struct drm_crtc_funcs <drm_crtc_funcs>`
set_config field. When called, it will split the set_config operation
in smaller, simpler operations and call the driver to handle them.
To use the mid-layer, drivers call
:c:func:`drm_crtc_helper_add()`,
:c:func:`drm_encoder_helper_add()` and
:c:func:`drm_connector_helper_add()` functions to install their
mid-layer bottom operations handlers, and fill the :c:type:`struct
drm_crtc_funcs <drm_crtc_funcs>`, :c:type:`struct
drm_encoder_funcs <drm_encoder_funcs>` and :c:type:`struct
drm_connector_funcs <drm_connector_funcs>` structures with
pointers to the mid-layer top API functions. Installing the mid-layer
bottom operation handlers is best done right after registering the
corresponding KMS object.
The mid-layer is not split between CRTC, encoder and connector
operations. To use it, a driver must provide bottom functions for all of
the three KMS entities.
Atomic Modeset Helper Functions Reference
=========================================
Overview
--------
.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
:doc: overview
Implementing Asynchronous Atomic Commit
---------------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
:doc: implementing nonblocking commit
Atomic State Reset and Initialization
-------------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
:doc: atomic state reset and initialization
.. kernel-doc:: include/drm/drm_atomic_helper.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
:export:
Modeset Helper Reference for Common Vtables
===========================================
.. kernel-doc:: include/drm/drm_modeset_helper_vtables.h
:internal:
.. kernel-doc:: include/drm/drm_modeset_helper_vtables.h
:doc: overview
Legacy CRTC/Modeset Helper Functions Reference
==============================================
.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c
:doc: overview
Output Probing Helper Functions Reference
=========================================
.. kernel-doc:: drivers/gpu/drm/drm_probe_helper.c
:doc: output probing helper overview
.. kernel-doc:: drivers/gpu/drm/drm_probe_helper.c
:export:
fbdev Helper Functions Reference
================================
.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
:doc: fbdev helpers
.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
:export:
.. kernel-doc:: include/drm/drm_fb_helper.h
:internal:
Framebuffer CMA Helper Functions Reference
==========================================
.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c
:doc: framebuffer cma helper functions
.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c
:export:
Display Port Helper Functions Reference
=======================================
.. kernel-doc:: drivers/gpu/drm/drm_dp_helper.c
:doc: dp helpers
.. kernel-doc:: include/drm/drm_dp_helper.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_dp_helper.c
:export:
Display Port Dual Mode Adaptor Helper Functions Reference
=========================================================
.. kernel-doc:: drivers/gpu/drm/drm_dp_dual_mode_helper.c
:doc: dp dual mode helpers
.. kernel-doc:: include/drm/drm_dp_dual_mode_helper.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_dp_dual_mode_helper.c
:export:
Display Port MST Helper Functions Reference
===========================================
.. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c
:doc: dp mst helper
.. kernel-doc:: include/drm/drm_dp_mst_helper.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c
:export:
MIPI DSI Helper Functions Reference
===================================
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:doc: dsi helpers
.. kernel-doc:: include/drm/drm_mipi_dsi.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
EDID Helper Functions Reference
===============================
.. kernel-doc:: drivers/gpu/drm/drm_edid.c
:export:
Rectangle Utilities Reference
=============================
.. kernel-doc:: include/drm/drm_rect.h
:doc: rect utils
.. kernel-doc:: include/drm/drm_rect.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_rect.c
:export:
Flip-work Helper Reference
==========================
.. kernel-doc:: include/drm/drm_flip_work.h
:doc: flip utils
.. kernel-doc:: include/drm/drm_flip_work.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_flip_work.c
:export:
HDMI Infoframes Helper Reference
================================
Strictly speaking this is not a DRM helper library but generally useable
by any driver interfacing with HDMI outputs like v4l or alsa drivers.
But it nicely fits into the overall topic of mode setting helper
libraries and hence is also included here.
.. kernel-doc:: include/linux/hdmi.h
:internal:
.. kernel-doc:: drivers/video/hdmi.c
:export:
Plane Helper Reference
======================
.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c
:doc: overview
Tile group
----------
.. kernel-doc:: drivers/gpu/drm/drm_crtc.c
:doc: Tile group
Bridges
=======
Overview
--------
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c
:doc: overview
Default bridge callback sequence
--------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c
:doc: bridge callbacks
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c
:export:
Panel Helper Reference
======================
.. kernel-doc:: include/drm/drm_panel.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_panel.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_panel.c
:doc: drm panel
Simple KMS Helper Reference
===========================
.. kernel-doc:: include/drm/drm_simple_kms_helper.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
:doc: overview

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=========================
Kernel Mode Setting (KMS)
=========================
Mode Setting
============
Drivers must initialize the mode setting core by calling
:c:func:`drm_mode_config_init()` on the DRM device. The function
initializes the :c:type:`struct drm_device <drm_device>`
mode_config field and never fails. Once done, mode configuration must
be setup by initializing the following fields.
- int min_width, min_height; int max_width, max_height;
Minimum and maximum width and height of the frame buffers in pixel
units.
- struct drm_mode_config_funcs \*funcs;
Mode setting functions.
Display Modes Function Reference
--------------------------------
.. kernel-doc:: include/drm/drm_modes.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_modes.c
:export:
Atomic Mode Setting Function Reference
--------------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
:export:
.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
:internal:
Frame Buffer Abstraction
------------------------
Frame buffers are abstract memory objects that provide a source of
pixels to scanout to a CRTC. Applications explicitly request the
creation of frame buffers through the DRM_IOCTL_MODE_ADDFB(2) ioctls
and receive an opaque handle that can be passed to the KMS CRTC control,
plane configuration and page flip functions.
Frame buffers rely on the underneath memory manager for low-level memory
operations. When creating a frame buffer applications pass a memory
handle (or a list of memory handles for multi-planar formats) through
the ``drm_mode_fb_cmd2`` argument. For drivers using GEM as their
userspace buffer management interface this would be a GEM handle.
Drivers are however free to use their own backing storage object
handles, e.g. vmwgfx directly exposes special TTM handles to userspace
and so expects TTM handles in the create ioctl and not GEM handles.
The lifetime of a drm framebuffer is controlled with a reference count,
drivers can grab additional references with
:c:func:`drm_framebuffer_reference()`and drop them again with
:c:func:`drm_framebuffer_unreference()`. For driver-private
framebuffers for which the last reference is never dropped (e.g. for the
fbdev framebuffer when the struct :c:type:`struct drm_framebuffer
<drm_framebuffer>` is embedded into the fbdev helper struct)
drivers can manually clean up a framebuffer at module unload time with
:c:func:`drm_framebuffer_unregister_private()`.
DRM Format Handling
-------------------
.. kernel-doc:: include/drm/drm_fourcc.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_fourcc.c
:export:
Dumb Buffer Objects
-------------------
The KMS API doesn't standardize backing storage object creation and
leaves it to driver-specific ioctls. Furthermore actually creating a
buffer object even for GEM-based drivers is done through a
driver-specific ioctl - GEM only has a common userspace interface for
sharing and destroying objects. While not an issue for full-fledged
graphics stacks that include device-specific userspace components (in
libdrm for instance), this limit makes DRM-based early boot graphics
unnecessarily complex.
Dumb objects partly alleviate the problem by providing a standard API to
create dumb buffers suitable for scanout, which can then be used to
create KMS frame buffers.
To support dumb objects drivers must implement the dumb_create,
dumb_destroy and dumb_map_offset operations.
- int (\*dumb_create)(struct drm_file \*file_priv, struct
drm_device \*dev, struct drm_mode_create_dumb \*args);
The dumb_create operation creates a driver object (GEM or TTM
handle) suitable for scanout based on the width, height and depth
from the struct :c:type:`struct drm_mode_create_dumb
<drm_mode_create_dumb>` argument. It fills the argument's
handle, pitch and size fields with a handle for the newly created
object and its line pitch and size in bytes.
- int (\*dumb_destroy)(struct drm_file \*file_priv, struct
drm_device \*dev, uint32_t handle);
The dumb_destroy operation destroys a dumb object created by
dumb_create.
- int (\*dumb_map_offset)(struct drm_file \*file_priv, struct
drm_device \*dev, uint32_t handle, uint64_t \*offset);
The dumb_map_offset operation associates an mmap fake offset with
the object given by the handle and returns it. Drivers must use the
:c:func:`drm_gem_create_mmap_offset()` function to associate
the fake offset as described in ?.
Note that dumb objects may not be used for gpu acceleration, as has been
attempted on some ARM embedded platforms. Such drivers really must have
a hardware-specific ioctl to allocate suitable buffer objects.
Output Polling
--------------
void (\*output_poll_changed)(struct drm_device \*dev);
This operation notifies the driver that the status of one or more
connectors has changed. Drivers that use the fb helper can just call the
:c:func:`drm_fb_helper_hotplug_event()` function to handle this
operation.
KMS Initialization and Cleanup
==============================
A KMS device is abstracted and exposed as a set of planes, CRTCs,
encoders and connectors. KMS drivers must thus create and initialize all
those objects at load time after initializing mode setting.
CRTCs (:c:type:`struct drm_crtc <drm_crtc>`)
--------------------------------------------
A CRTC is an abstraction representing a part of the chip that contains a
pointer to a scanout buffer. Therefore, the number of CRTCs available
determines how many independent scanout buffers can be active at any
given time. The CRTC structure contains several fields to support this:
a pointer to some video memory (abstracted as a frame buffer object), a
display mode, and an (x, y) offset into the video memory to support
panning or configurations where one piece of video memory spans multiple
CRTCs.
CRTC Initialization
~~~~~~~~~~~~~~~~~~~
A KMS device must create and register at least one struct
:c:type:`struct drm_crtc <drm_crtc>` instance. The instance is
allocated and zeroed by the driver, possibly as part of a larger
structure, and registered with a call to :c:func:`drm_crtc_init()`
with a pointer to CRTC functions.
Planes (:c:type:`struct drm_plane <drm_plane>`)
-----------------------------------------------
A plane represents an image source that can be blended with or overlayed
on top of a CRTC during the scanout process. Planes are associated with
a frame buffer to crop a portion of the image memory (source) and
optionally scale it to a destination size. The result is then blended
with or overlayed on top of a CRTC.
The DRM core recognizes three types of planes:
- DRM_PLANE_TYPE_PRIMARY represents a "main" plane for a CRTC.
Primary planes are the planes operated upon by CRTC modesetting and
flipping operations described in the page_flip hook in
:c:type:`struct drm_crtc_funcs <drm_crtc_funcs>`.
- DRM_PLANE_TYPE_CURSOR represents a "cursor" plane for a CRTC.
Cursor planes are the planes operated upon by the
DRM_IOCTL_MODE_CURSOR and DRM_IOCTL_MODE_CURSOR2 ioctls.
- DRM_PLANE_TYPE_OVERLAY represents all non-primary, non-cursor
planes. Some drivers refer to these types of planes as "sprites"
internally.
For compatibility with legacy userspace, only overlay planes are made
available to userspace by default. Userspace clients may set the
DRM_CLIENT_CAP_UNIVERSAL_PLANES client capability bit to indicate
that they wish to receive a universal plane list containing all plane
types.
Plane Initialization
~~~~~~~~~~~~~~~~~~~~
To create a plane, a KMS drivers allocates and zeroes an instances of
:c:type:`struct drm_plane <drm_plane>` (possibly as part of a
larger structure) and registers it with a call to
:c:func:`drm_universal_plane_init()`. The function takes a
bitmask of the CRTCs that can be associated with the plane, a pointer to
the plane functions, a list of format supported formats, and the type of
plane (primary, cursor, or overlay) being initialized.
Cursor and overlay planes are optional. All drivers should provide one
primary plane per CRTC (although this requirement may change in the
future); drivers that do not wish to provide special handling for
primary planes may make use of the helper functions described in ? to
create and register a primary plane with standard capabilities.
Encoders (:c:type:`struct drm_encoder <drm_encoder>`)
-----------------------------------------------------
An encoder takes pixel data from a CRTC and converts it to a format
suitable for any attached connectors. On some devices, it may be
possible to have a CRTC send data to more than one encoder. In that
case, both encoders would receive data from the same scanout buffer,
resulting in a "cloned" display configuration across the connectors
attached to each encoder.
Encoder Initialization
~~~~~~~~~~~~~~~~~~~~~~
As for CRTCs, a KMS driver must create, initialize and register at least
one :c:type:`struct drm_encoder <drm_encoder>` instance. The
instance is allocated and zeroed by the driver, possibly as part of a
larger structure.
Drivers must initialize the :c:type:`struct drm_encoder
<drm_encoder>` possible_crtcs and possible_clones fields before
registering the encoder. Both fields are bitmasks of respectively the
CRTCs that the encoder can be connected to, and sibling encoders
candidate for cloning.
After being initialized, the encoder must be registered with a call to
:c:func:`drm_encoder_init()`. The function takes a pointer to the
encoder functions and an encoder type. Supported types are
- DRM_MODE_ENCODER_DAC for VGA and analog on DVI-I/DVI-A
- DRM_MODE_ENCODER_TMDS for DVI, HDMI and (embedded) DisplayPort
- DRM_MODE_ENCODER_LVDS for display panels
- DRM_MODE_ENCODER_TVDAC for TV output (Composite, S-Video,
Component, SCART)
- DRM_MODE_ENCODER_VIRTUAL for virtual machine displays
Encoders must be attached to a CRTC to be used. DRM drivers leave
encoders unattached at initialization time. Applications (or the fbdev
compatibility layer when implemented) are responsible for attaching the
encoders they want to use to a CRTC.
Connectors (:c:type:`struct drm_connector <drm_connector>`)
-----------------------------------------------------------
A connector is the final destination for pixel data on a device, and
usually connects directly to an external display device like a monitor
or laptop panel. A connector can only be attached to one encoder at a
time. The connector is also the structure where information about the
attached display is kept, so it contains fields for display data, EDID
data, DPMS & connection status, and information about modes supported on
the attached displays.
Connector Initialization
~~~~~~~~~~~~~~~~~~~~~~~~
Finally a KMS driver must create, initialize, register and attach at
least one :c:type:`struct drm_connector <drm_connector>`
instance. The instance is created as other KMS objects and initialized
by setting the following fields.
interlace_allowed
Whether the connector can handle interlaced modes.
doublescan_allowed
Whether the connector can handle doublescan.
display_info
Display information is filled from EDID information when a display
is detected. For non hot-pluggable displays such as flat panels in
embedded systems, the driver should initialize the
display_info.width_mm and display_info.height_mm fields with the
physical size of the display.
polled
Connector polling mode, a combination of
DRM_CONNECTOR_POLL_HPD
The connector generates hotplug events and doesn't need to be
periodically polled. The CONNECT and DISCONNECT flags must not
be set together with the HPD flag.
DRM_CONNECTOR_POLL_CONNECT
Periodically poll the connector for connection.
DRM_CONNECTOR_POLL_DISCONNECT
Periodically poll the connector for disconnection.
Set to 0 for connectors that don't support connection status
discovery.
The connector is then registered with a call to
:c:func:`drm_connector_init()` with a pointer to the connector
functions and a connector type, and exposed through sysfs with a call to
:c:func:`drm_connector_register()`.
Supported connector types are
- DRM_MODE_CONNECTOR_VGA
- DRM_MODE_CONNECTOR_DVII
- DRM_MODE_CONNECTOR_DVID
- DRM_MODE_CONNECTOR_DVIA
- DRM_MODE_CONNECTOR_Composite
- DRM_MODE_CONNECTOR_SVIDEO
- DRM_MODE_CONNECTOR_LVDS
- DRM_MODE_CONNECTOR_Component
- DRM_MODE_CONNECTOR_9PinDIN
- DRM_MODE_CONNECTOR_DisplayPort
- DRM_MODE_CONNECTOR_HDMIA
- DRM_MODE_CONNECTOR_HDMIB
- DRM_MODE_CONNECTOR_TV
- DRM_MODE_CONNECTOR_eDP
- DRM_MODE_CONNECTOR_VIRTUAL
Connectors must be attached to an encoder to be used. For devices that
map connectors to encoders 1:1, the connector should be attached at
initialization time with a call to
:c:func:`drm_mode_connector_attach_encoder()`. The driver must
also set the :c:type:`struct drm_connector <drm_connector>`
encoder field to point to the attached encoder.
Finally, drivers must initialize the connectors state change detection
with a call to :c:func:`drm_kms_helper_poll_init()`. If at least
one connector is pollable but can't generate hotplug interrupts
(indicated by the DRM_CONNECTOR_POLL_CONNECT and
DRM_CONNECTOR_POLL_DISCONNECT connector flags), a delayed work will
automatically be queued to periodically poll for changes. Connectors
that can generate hotplug interrupts must be marked with the
DRM_CONNECTOR_POLL_HPD flag instead, and their interrupt handler must
call :c:func:`drm_helper_hpd_irq_event()`. The function will
queue a delayed work to check the state of all connectors, but no
periodic polling will be done.
Connector Operations
~~~~~~~~~~~~~~~~~~~~
**Note**
Unless otherwise state, all operations are mandatory.
DPMS
''''
void (\*dpms)(struct drm_connector \*connector, int mode);
The DPMS operation sets the power state of a connector. The mode
argument is one of
- DRM_MODE_DPMS_ON
- DRM_MODE_DPMS_STANDBY
- DRM_MODE_DPMS_SUSPEND
- DRM_MODE_DPMS_OFF
In all but DPMS_ON mode the encoder to which the connector is attached
should put the display in low-power mode by driving its signals
appropriately. If more than one connector is attached to the encoder
care should be taken not to change the power state of other displays as
a side effect. Low-power mode should be propagated to the encoders and
CRTCs when all related connectors are put in low-power mode.
Modes
'''''
int (\*fill_modes)(struct drm_connector \*connector, uint32_t
max_width, uint32_t max_height);
Fill the mode list with all supported modes for the connector. If the
``max_width`` and ``max_height`` arguments are non-zero, the
implementation must ignore all modes wider than ``max_width`` or higher
than ``max_height``.
The connector must also fill in this operation its display_info
width_mm and height_mm fields with the connected display physical size
in millimeters. The fields should be set to 0 if the value isn't known
or is not applicable (for instance for projector devices).
Connection Status
'''''''''''''''''
The connection status is updated through polling or hotplug events when
supported (see ?). The status value is reported to userspace through
ioctls and must not be used inside the driver, as it only gets
initialized by a call to :c:func:`drm_mode_getconnector()` from
userspace.
enum drm_connector_status (\*detect)(struct drm_connector
\*connector, bool force);
Check to see if anything is attached to the connector. The ``force``
parameter is set to false whilst polling or to true when checking the
connector due to user request. ``force`` can be used by the driver to
avoid expensive, destructive operations during automated probing.
Return connector_status_connected if something is connected to the
connector, connector_status_disconnected if nothing is connected and
connector_status_unknown if the connection state isn't known.
Drivers should only return connector_status_connected if the
connection status has really been probed as connected. Connectors that
can't detect the connection status, or failed connection status probes,
should return connector_status_unknown.
Cleanup
-------
The DRM core manages its objects' lifetime. When an object is not needed
anymore the core calls its destroy function, which must clean up and
free every resource allocated for the object. Every
:c:func:`drm_\*_init()` call must be matched with a corresponding
:c:func:`drm_\*_cleanup()` call to cleanup CRTCs
(:c:func:`drm_crtc_cleanup()`), planes
(:c:func:`drm_plane_cleanup()`), encoders
(:c:func:`drm_encoder_cleanup()`) and connectors
(:c:func:`drm_connector_cleanup()`). Furthermore, connectors that
have been added to sysfs must be removed by a call to
:c:func:`drm_connector_unregister()` before calling
:c:func:`drm_connector_cleanup()`.
Connectors state change detection must be cleanup up with a call to
:c:func:`drm_kms_helper_poll_fini()`.
Output discovery and initialization example
-------------------------------------------
::
void intel_crt_init(struct drm_device *dev)
{
struct drm_connector *connector;
struct intel_output *intel_output;
intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
if (!intel_output)
return;
connector = &intel_output->base;
drm_connector_init(dev, &intel_output->base,
&intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
drm_encoder_init(dev, &intel_output->enc, &intel_crt_enc_funcs,
DRM_MODE_ENCODER_DAC);
drm_mode_connector_attach_encoder(&intel_output->base,
&intel_output->enc);
/* Set up the DDC bus. */
intel_output->ddc_bus = intel_i2c_create(dev, GPIOA, "CRTDDC_A");
if (!intel_output->ddc_bus) {
dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
"failed.\n");
return;
}
intel_output->type = INTEL_OUTPUT_ANALOG;
connector->interlace_allowed = 0;
connector->doublescan_allowed = 0;
drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs);
drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
drm_connector_register(connector);
}
In the example above (taken from the i915 driver), a CRTC, connector and
encoder combination is created. A device-specific i2c bus is also
created for fetching EDID data and performing monitor detection. Once
the process is complete, the new connector is registered with sysfs to
make its properties available to applications.
KMS API Functions
-----------------
.. kernel-doc:: drivers/gpu/drm/drm_crtc.c
:export:
KMS Data Structures
-------------------
.. kernel-doc:: include/drm/drm_crtc.h
:internal:
KMS Locking
-----------
.. kernel-doc:: drivers/gpu/drm/drm_modeset_lock.c
:doc: kms locking
.. kernel-doc:: include/drm/drm_modeset_lock.h
:internal:
.. kernel-doc:: drivers/gpu/drm/drm_modeset_lock.c
:export:
KMS Properties
==============
Drivers may need to expose additional parameters to applications than
those described in the previous sections. KMS supports attaching
properties to CRTCs, connectors and planes and offers a userspace API to
list, get and set the property values.
Properties are identified by a name that uniquely defines the property
purpose, and store an associated value. For all property types except
blob properties the value is a 64-bit unsigned integer.
KMS differentiates between properties and property instances. Drivers
first create properties and then create and associate individual
instances of those properties to objects. A property can be instantiated
multiple times and associated with different objects. Values are stored
in property instances, and all other property information are stored in
the property and shared between all instances of the property.
Every property is created with a type that influences how the KMS core
handles the property. Supported property types are
DRM_MODE_PROP_RANGE
Range properties report their minimum and maximum admissible values.
The KMS core verifies that values set by application fit in that
range.
DRM_MODE_PROP_ENUM
Enumerated properties take a numerical value that ranges from 0 to
the number of enumerated values defined by the property minus one,
and associate a free-formed string name to each value. Applications
can retrieve the list of defined value-name pairs and use the
numerical value to get and set property instance values.
DRM_MODE_PROP_BITMASK
Bitmask properties are enumeration properties that additionally
restrict all enumerated values to the 0..63 range. Bitmask property
instance values combine one or more of the enumerated bits defined
by the property.
DRM_MODE_PROP_BLOB
Blob properties store a binary blob without any format restriction.
The binary blobs are created as KMS standalone objects, and blob
property instance values store the ID of their associated blob
object.
Blob properties are only used for the connector EDID property and
cannot be created by drivers.
To create a property drivers call one of the following functions
depending on the property type. All property creation functions take
property flags and name, as well as type-specific arguments.
- struct drm_property \*drm_property_create_range(struct
drm_device \*dev, int flags, const char \*name, uint64_t min,
uint64_t max);
Create a range property with the given minimum and maximum values.
- struct drm_property \*drm_property_create_enum(struct drm_device
\*dev, int flags, const char \*name, const struct
drm_prop_enum_list \*props, int num_values);
Create an enumerated property. The ``props`` argument points to an
array of ``num_values`` value-name pairs.
- struct drm_property \*drm_property_create_bitmask(struct
drm_device \*dev, int flags, const char \*name, const struct
drm_prop_enum_list \*props, int num_values);
Create a bitmask property. The ``props`` argument points to an array
of ``num_values`` value-name pairs.
Properties can additionally be created as immutable, in which case they
will be read-only for applications but can be modified by the driver. To
create an immutable property drivers must set the
DRM_MODE_PROP_IMMUTABLE flag at property creation time.
When no array of value-name pairs is readily available at property
creation time for enumerated or range properties, drivers can create the
property using the :c:func:`drm_property_create()` function and
manually add enumeration value-name pairs by calling the
:c:func:`drm_property_add_enum()` function. Care must be taken to
properly specify the property type through the ``flags`` argument.
After creating properties drivers can attach property instances to CRTC,
connector and plane objects by calling the
:c:func:`drm_object_attach_property()`. The function takes a
pointer to the target object, a pointer to the previously created
property and an initial instance value.
Existing KMS Properties
-----------------------
The following table gives description of drm properties exposed by
various modules/drivers.
.. csv-table::
:header-rows: 1
:file: kms-properties.csv
Vertical Blanking
=================
Vertical blanking plays a major role in graphics rendering. To achieve
tear-free display, users must synchronize page flips and/or rendering to
vertical blanking. The DRM API offers ioctls to perform page flips
synchronized to vertical blanking and wait for vertical blanking.
The DRM core handles most of the vertical blanking management logic,
which involves filtering out spurious interrupts, keeping race-free
blanking counters, coping with counter wrap-around and resets and
keeping use counts. It relies on the driver to generate vertical
blanking interrupts and optionally provide a hardware vertical blanking
counter. Drivers must implement the following operations.
- int (\*enable_vblank) (struct drm_device \*dev, int crtc); void
(\*disable_vblank) (struct drm_device \*dev, int crtc);
Enable or disable vertical blanking interrupts for the given CRTC.
- u32 (\*get_vblank_counter) (struct drm_device \*dev, int crtc);
Retrieve the value of the vertical blanking counter for the given
CRTC. If the hardware maintains a vertical blanking counter its value
should be returned. Otherwise drivers can use the
:c:func:`drm_vblank_count()` helper function to handle this
operation.
Drivers must initialize the vertical blanking handling core with a call
to :c:func:`drm_vblank_init()` in their load operation.
Vertical blanking interrupts can be enabled by the DRM core or by
drivers themselves (for instance to handle page flipping operations).
The DRM core maintains a vertical blanking use count to ensure that the
interrupts are not disabled while a user still needs them. To increment
the use count, drivers call :c:func:`drm_vblank_get()`. Upon
return vertical blanking interrupts are guaranteed to be enabled.
To decrement the use count drivers call
:c:func:`drm_vblank_put()`. Only when the use count drops to zero
will the DRM core disable the vertical blanking interrupts after a delay
by scheduling a timer. The delay is accessible through the
vblankoffdelay module parameter or the ``drm_vblank_offdelay`` global
variable and expressed in milliseconds. Its default value is 5000 ms.
Zero means never disable, and a negative value means disable
immediately. Drivers may override the behaviour by setting the
:c:type:`struct drm_device <drm_device>`
vblank_disable_immediate flag, which when set causes vblank interrupts
to be disabled immediately regardless of the drm_vblank_offdelay
value. The flag should only be set if there's a properly working
hardware vblank counter present.
When a vertical blanking interrupt occurs drivers only need to call the
:c:func:`drm_handle_vblank()` function to account for the
interrupt.
Resources allocated by :c:func:`drm_vblank_init()` must be freed
with a call to :c:func:`drm_vblank_cleanup()` in the driver unload
operation handler.
Vertical Blanking and Interrupt Handling Functions Reference
------------------------------------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_irq.c
:export:
.. kernel-doc:: include/drm/drmP.h
:functions: drm_crtc_vblank_waitqueue

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=====================
DRM Memory Management
=====================
Modern Linux systems require large amount of graphics memory to store
frame buffers, textures, vertices and other graphics-related data. Given
the very dynamic nature of many of that data, managing graphics memory
efficiently is thus crucial for the graphics stack and plays a central
role in the DRM infrastructure.
The DRM core includes two memory managers, namely Translation Table Maps
(TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory
manager to be developed and tried to be a one-size-fits-them all
solution. It provides a single userspace API to accommodate the need of
all hardware, supporting both Unified Memory Architecture (UMA) devices
and devices with dedicated video RAM (i.e. most discrete video cards).
This resulted in a large, complex piece of code that turned out to be
hard to use for driver development.
GEM started as an Intel-sponsored project in reaction to TTM's
complexity. Its design philosophy is completely different: instead of
providing a solution to every graphics memory-related problems, GEM
identified common code between drivers and created a support library to
share it. GEM has simpler initialization and execution requirements than
TTM, but has no video RAM management capabilities and is thus limited to
UMA devices.
The Translation Table Manager (TTM)
-----------------------------------
TTM design background and information belongs here.
TTM initialization
~~~~~~~~~~~~~~~~~~
**Warning**
This section is outdated.
Drivers wishing to support TTM must fill out a drm_bo_driver
structure. The structure contains several fields with function pointers
for initializing the TTM, allocating and freeing memory, waiting for
command completion and fence synchronization, and memory migration. See
the radeon_ttm.c file for an example of usage.
The ttm_global_reference structure is made up of several fields:
::
struct ttm_global_reference {
enum ttm_global_types global_type;
size_t size;
void *object;
int (*init) (struct ttm_global_reference *);
void (*release) (struct ttm_global_reference *);
};
There should be one global reference structure for your memory manager
as a whole, and there will be others for each object created by the
memory manager at runtime. Your global TTM should have a type of
TTM_GLOBAL_TTM_MEM. The size field for the global object should be
sizeof(struct ttm_mem_global), and the init and release hooks should
point at your driver-specific init and release routines, which probably
eventually call ttm_mem_global_init and ttm_mem_global_release,
respectively.
Once your global TTM accounting structure is set up and initialized by
calling ttm_global_item_ref() on it, you need to create a buffer
object TTM to provide a pool for buffer object allocation by clients and
the kernel itself. The type of this object should be
TTM_GLOBAL_TTM_BO, and its size should be sizeof(struct
ttm_bo_global). Again, driver-specific init and release functions may
be provided, likely eventually calling ttm_bo_global_init() and
ttm_bo_global_release(), respectively. Also, like the previous
object, ttm_global_item_ref() is used to create an initial reference
count for the TTM, which will call your initialization function.
The Graphics Execution Manager (GEM)
------------------------------------
The GEM design approach has resulted in a memory manager that doesn't
provide full coverage of all (or even all common) use cases in its
userspace or kernel API. GEM exposes a set of standard memory-related
operations to userspace and a set of helper functions to drivers, and
let drivers implement hardware-specific operations with their own
private API.
The GEM userspace API is described in the `GEM - the Graphics Execution
Manager <http://lwn.net/Articles/283798/>`__ article on LWN. While
slightly outdated, the document provides a good overview of the GEM API
principles. Buffer allocation and read and write operations, described
as part of the common GEM API, are currently implemented using
driver-specific ioctls.
GEM is data-agnostic. It manages abstract buffer objects without knowing
what individual buffers contain. APIs that require knowledge of buffer
contents or purpose, such as buffer allocation or synchronization
primitives, are thus outside of the scope of GEM and must be implemented
using driver-specific ioctls.
On a fundamental level, GEM involves several operations:
- Memory allocation and freeing
- Command execution
- Aperture management at command execution time
Buffer object allocation is relatively straightforward and largely
provided by Linux's shmem layer, which provides memory to back each
object.
Device-specific operations, such as command execution, pinning, buffer
read & write, mapping, and domain ownership transfers are left to
driver-specific ioctls.
GEM Initialization
~~~~~~~~~~~~~~~~~~
Drivers that use GEM must set the DRIVER_GEM bit in the struct
:c:type:`struct drm_driver <drm_driver>` driver_features
field. The DRM core will then automatically initialize the GEM core
before calling the load operation. Behind the scene, this will create a
DRM Memory Manager object which provides an address space pool for
object allocation.
In a KMS configuration, drivers need to allocate and initialize a
command ring buffer following core GEM initialization if required by the
hardware. UMA devices usually have what is called a "stolen" memory
region, which provides space for the initial framebuffer and large,
contiguous memory regions required by the device. This space is
typically not managed by GEM, and must be initialized separately into
its own DRM MM object.
GEM Objects Creation
~~~~~~~~~~~~~~~~~~~~
GEM splits creation of GEM objects and allocation of the memory that
backs them in two distinct operations.
GEM objects are represented by an instance of struct :c:type:`struct
drm_gem_object <drm_gem_object>`. Drivers usually need to
extend GEM objects with private information and thus create a
driver-specific GEM object structure type that embeds an instance of
struct :c:type:`struct drm_gem_object <drm_gem_object>`.
To create a GEM object, a driver allocates memory for an instance of its
specific GEM object type and initializes the embedded struct
:c:type:`struct drm_gem_object <drm_gem_object>` with a call
to :c:func:`drm_gem_object_init()`. The function takes a pointer
to the DRM device, a pointer to the GEM object and the buffer object
size in bytes.
GEM uses shmem to allocate anonymous pageable memory.
:c:func:`drm_gem_object_init()` will create an shmfs file of the
requested size and store it into the struct :c:type:`struct
drm_gem_object <drm_gem_object>` filp field. The memory is
used as either main storage for the object when the graphics hardware
uses system memory directly or as a backing store otherwise.
Drivers are responsible for the actual physical pages allocation by
calling :c:func:`shmem_read_mapping_page_gfp()` for each page.
Note that they can decide to allocate pages when initializing the GEM
object, or to delay allocation until the memory is needed (for instance
when a page fault occurs as a result of a userspace memory access or
when the driver needs to start a DMA transfer involving the memory).
Anonymous pageable memory allocation is not always desired, for instance
when the hardware requires physically contiguous system memory as is
often the case in embedded devices. Drivers can create GEM objects with
no shmfs backing (called private GEM objects) by initializing them with
a call to :c:func:`drm_gem_private_object_init()` instead of
:c:func:`drm_gem_object_init()`. Storage for private GEM objects
must be managed by drivers.
GEM Objects Lifetime
~~~~~~~~~~~~~~~~~~~~
All GEM objects are reference-counted by the GEM core. References can be
acquired and release by :c:func:`calling
drm_gem_object_reference()` and
:c:func:`drm_gem_object_unreference()` respectively. The caller
must hold the :c:type:`struct drm_device <drm_device>`
struct_mutex lock when calling
:c:func:`drm_gem_object_reference()`. As a convenience, GEM
provides :c:func:`drm_gem_object_unreference_unlocked()`
functions that can be called without holding the lock.
When the last reference to a GEM object is released the GEM core calls
the :c:type:`struct drm_driver <drm_driver>` gem_free_object
operation. That operation is mandatory for GEM-enabled drivers and must
free the GEM object and all associated resources.
void (\*gem_free_object) (struct drm_gem_object \*obj); Drivers are
responsible for freeing all GEM object resources. This includes the
resources created by the GEM core, which need to be released with
:c:func:`drm_gem_object_release()`.
GEM Objects Naming
~~~~~~~~~~~~~~~~~~
Communication between userspace and the kernel refers to GEM objects
using local handles, global names or, more recently, file descriptors.
All of those are 32-bit integer values; the usual Linux kernel limits
apply to the file descriptors.
GEM handles are local to a DRM file. Applications get a handle to a GEM
object through a driver-specific ioctl, and can use that handle to refer
to the GEM object in other standard or driver-specific ioctls. Closing a
DRM file handle frees all its GEM handles and dereferences the
associated GEM objects.
To create a handle for a GEM object drivers call
:c:func:`drm_gem_handle_create()`. The function takes a pointer
to the DRM file and the GEM object and returns a locally unique handle.
When the handle is no longer needed drivers delete it with a call to
:c:func:`drm_gem_handle_delete()`. Finally the GEM object
associated with a handle can be retrieved by a call to
:c:func:`drm_gem_object_lookup()`.
Handles don't take ownership of GEM objects, they only take a reference
to the object that will be dropped when the handle is destroyed. To
avoid leaking GEM objects, drivers must make sure they drop the
reference(s) they own (such as the initial reference taken at object
creation time) as appropriate, without any special consideration for the
handle. For example, in the particular case of combined GEM object and
handle creation in the implementation of the dumb_create operation,
drivers must drop the initial reference to the GEM object before
returning the handle.
GEM names are similar in purpose to handles but are not local to DRM
files. They can be passed between processes to reference a GEM object
globally. Names can't be used directly to refer to objects in the DRM
API, applications must convert handles to names and names to handles
using the DRM_IOCTL_GEM_FLINK and DRM_IOCTL_GEM_OPEN ioctls
respectively. The conversion is handled by the DRM core without any
driver-specific support.
GEM also supports buffer sharing with dma-buf file descriptors through
PRIME. GEM-based drivers must use the provided helpers functions to
implement the exporting and importing correctly. See ?. Since sharing
file descriptors is inherently more secure than the easily guessable and
global GEM names it is the preferred buffer sharing mechanism. Sharing
buffers through GEM names is only supported for legacy userspace.
Furthermore PRIME also allows cross-device buffer sharing since it is
based on dma-bufs.
GEM Objects Mapping
~~~~~~~~~~~~~~~~~~~
Because mapping operations are fairly heavyweight GEM favours
read/write-like access to buffers, implemented through driver-specific
ioctls, over mapping buffers to userspace. However, when random access
to the buffer is needed (to perform software rendering for instance),
direct access to the object can be more efficient.
The mmap system call can't be used directly to map GEM objects, as they
don't have their own file handle. Two alternative methods currently
co-exist to map GEM objects to userspace. The first method uses a
driver-specific ioctl to perform the mapping operation, calling
:c:func:`do_mmap()` under the hood. This is often considered
dubious, seems to be discouraged for new GEM-enabled drivers, and will
thus not be described here.
The second method uses the mmap system call on the DRM file handle. void
\*mmap(void \*addr, size_t length, int prot, int flags, int fd, off_t
offset); DRM identifies the GEM object to be mapped by a fake offset
passed through the mmap offset argument. Prior to being mapped, a GEM
object must thus be associated with a fake offset. To do so, drivers
must call :c:func:`drm_gem_create_mmap_offset()` on the object.
Once allocated, the fake offset value must be passed to the application
in a driver-specific way and can then be used as the mmap offset
argument.
The GEM core provides a helper method :c:func:`drm_gem_mmap()` to
handle object mapping. The method can be set directly as the mmap file
operation handler. It will look up the GEM object based on the offset
value and set the VMA operations to the :c:type:`struct drm_driver
<drm_driver>` gem_vm_ops field. Note that
:c:func:`drm_gem_mmap()` doesn't map memory to userspace, but
relies on the driver-provided fault handler to map pages individually.
To use :c:func:`drm_gem_mmap()`, drivers must fill the struct
:c:type:`struct drm_driver <drm_driver>` gem_vm_ops field
with a pointer to VM operations.
struct vm_operations_struct \*gem_vm_ops struct
vm_operations_struct { void (\*open)(struct vm_area_struct \* area);
void (\*close)(struct vm_area_struct \* area); int (\*fault)(struct
vm_area_struct \*vma, struct vm_fault \*vmf); };
The open and close operations must update the GEM object reference
count. Drivers can use the :c:func:`drm_gem_vm_open()` and
:c:func:`drm_gem_vm_close()` helper functions directly as open
and close handlers.
The fault operation handler is responsible for mapping individual pages
to userspace when a page fault occurs. Depending on the memory
allocation scheme, drivers can allocate pages at fault time, or can
decide to allocate memory for the GEM object at the time the object is
created.
Drivers that want to map the GEM object upfront instead of handling page
faults can implement their own mmap file operation handler.
Memory Coherency
~~~~~~~~~~~~~~~~
When mapped to the device or used in a command buffer, backing pages for
an object are flushed to memory and marked write combined so as to be
coherent with the GPU. Likewise, if the CPU accesses an object after the
GPU has finished rendering to the object, then the object must be made
coherent with the CPU's view of memory, usually involving GPU cache
flushing of various kinds. This core CPU<->GPU coherency management is
provided by a device-specific ioctl, which evaluates an object's current
domain and performs any necessary flushing or synchronization to put the
object into the desired coherency domain (note that the object may be
busy, i.e. an active render target; in that case, setting the domain
blocks the client and waits for rendering to complete before performing
any necessary flushing operations).
Command Execution
~~~~~~~~~~~~~~~~~
Perhaps the most important GEM function for GPU devices is providing a
command execution interface to clients. Client programs construct
command buffers containing references to previously allocated memory
objects, and then submit them to GEM. At that point, GEM takes care to
bind all the objects into the GTT, execute the buffer, and provide
necessary synchronization between clients accessing the same buffers.
This often involves evicting some objects from the GTT and re-binding
others (a fairly expensive operation), and providing relocation support
which hides fixed GTT offsets from clients. Clients must take care not
to submit command buffers that reference more objects than can fit in
the GTT; otherwise, GEM will reject them and no rendering will occur.
Similarly, if several objects in the buffer require fence registers to
be allocated for correct rendering (e.g. 2D blits on pre-965 chips),
care must be taken not to require more fence registers than are
available to the client. Such resource management should be abstracted
from the client in libdrm.
GEM Function Reference
----------------------
.. kernel-doc:: drivers/gpu/drm/drm_gem.c
:export:
.. kernel-doc:: include/drm/drm_gem.h
:internal:
VMA Offset Manager
------------------
.. kernel-doc:: drivers/gpu/drm/drm_vma_manager.c
:doc: vma offset manager
.. kernel-doc:: drivers/gpu/drm/drm_vma_manager.c
:export:
.. kernel-doc:: include/drm/drm_vma_manager.h
:internal:
PRIME Buffer Sharing
--------------------
PRIME is the cross device buffer sharing framework in drm, originally
created for the OPTIMUS range of multi-gpu platforms. To userspace PRIME
buffers are dma-buf based file descriptors.
Overview and Driver Interface
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Similar to GEM global names, PRIME file descriptors are also used to
share buffer objects across processes. They offer additional security:
as file descriptors must be explicitly sent over UNIX domain sockets to
be shared between applications, they can't be guessed like the globally
unique GEM names.
Drivers that support the PRIME API must set the DRIVER_PRIME bit in the
struct :c:type:`struct drm_driver <drm_driver>`
driver_features field, and implement the prime_handle_to_fd and
prime_fd_to_handle operations.
int (\*prime_handle_to_fd)(struct drm_device \*dev, struct drm_file
\*file_priv, uint32_t handle, uint32_t flags, int \*prime_fd); int
(\*prime_fd_to_handle)(struct drm_device \*dev, struct drm_file
\*file_priv, int prime_fd, uint32_t \*handle); Those two operations
convert a handle to a PRIME file descriptor and vice versa. Drivers must
use the kernel dma-buf buffer sharing framework to manage the PRIME file
descriptors. Similar to the mode setting API PRIME is agnostic to the
underlying buffer object manager, as long as handles are 32bit unsigned
integers.
While non-GEM drivers must implement the operations themselves, GEM
drivers must use the :c:func:`drm_gem_prime_handle_to_fd()` and
:c:func:`drm_gem_prime_fd_to_handle()` helper functions. Those
helpers rely on the driver gem_prime_export and gem_prime_import
operations to create a dma-buf instance from a GEM object (dma-buf
exporter role) and to create a GEM object from a dma-buf instance
(dma-buf importer role).
struct dma_buf \* (\*gem_prime_export)(struct drm_device \*dev,
struct drm_gem_object \*obj, int flags); struct drm_gem_object \*
(\*gem_prime_import)(struct drm_device \*dev, struct dma_buf
\*dma_buf); These two operations are mandatory for GEM drivers that
support PRIME.
PRIME Helper Functions
~~~~~~~~~~~~~~~~~~~~~~
.. kernel-doc:: drivers/gpu/drm/drm_prime.c
:doc: PRIME Helpers
PRIME Function References
-------------------------
.. kernel-doc:: drivers/gpu/drm/drm_prime.c
:export:
DRM MM Range Allocator
----------------------
Overview
~~~~~~~~
.. kernel-doc:: drivers/gpu/drm/drm_mm.c
:doc: Overview
LRU Scan/Eviction Support
~~~~~~~~~~~~~~~~~~~~~~~~~
.. kernel-doc:: drivers/gpu/drm/drm_mm.c
:doc: lru scan roaster
DRM MM Range Allocator Function References
------------------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_mm.c
:export:
.. kernel-doc:: include/drm/drm_mm.h
:internal:
CMA Helper Functions Reference
------------------------------
.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c
:doc: cma helpers
.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c
:export:
.. kernel-doc:: include/drm/drm_gem_cma_helper.h
:internal:

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===================
Userland interfaces
===================
The DRM core exports several interfaces to applications, generally
intended to be used through corresponding libdrm wrapper functions. In
addition, drivers export device-specific interfaces for use by userspace
drivers & device-aware applications through ioctls and sysfs files.
External interfaces include: memory mapping, context management, DMA
operations, AGP management, vblank control, fence management, memory
management, and output management.
Cover generic ioctls and sysfs layout here. We only need high-level
info, since man pages should cover the rest.
libdrm Device Lookup
====================
.. kernel-doc:: drivers/gpu/drm/drm_ioctl.c
:doc: getunique and setversion story
Primary Nodes, DRM Master and Authentication
============================================
.. kernel-doc:: drivers/gpu/drm/drm_auth.c
:doc: master and authentication
.. kernel-doc:: drivers/gpu/drm/drm_auth.c
:export:
.. kernel-doc:: include/drm/drm_auth.h
:internal:
Render nodes
============
DRM core provides multiple character-devices for user-space to use.
Depending on which device is opened, user-space can perform a different
set of operations (mainly ioctls). The primary node is always created
and called card<num>. Additionally, a currently unused control node,
called controlD<num> is also created. The primary node provides all
legacy operations and historically was the only interface used by
userspace. With KMS, the control node was introduced. However, the
planned KMS control interface has never been written and so the control
node stays unused to date.
With the increased use of offscreen renderers and GPGPU applications,
clients no longer require running compositors or graphics servers to
make use of a GPU. But the DRM API required unprivileged clients to
authenticate to a DRM-Master prior to getting GPU access. To avoid this
step and to grant clients GPU access without authenticating, render
nodes were introduced. Render nodes solely serve render clients, that
is, no modesetting or privileged ioctls can be issued on render nodes.
Only non-global rendering commands are allowed. If a driver supports
render nodes, it must advertise it via the DRIVER_RENDER DRM driver
capability. If not supported, the primary node must be used for render
clients together with the legacy drmAuth authentication procedure.
If a driver advertises render node support, DRM core will create a
separate render node called renderD<num>. There will be one render node
per device. No ioctls except PRIME-related ioctls will be allowed on
this node. Especially GEM_OPEN will be explicitly prohibited. Render
nodes are designed to avoid the buffer-leaks, which occur if clients
guess the flink names or mmap offsets on the legacy interface.
Additionally to this basic interface, drivers must mark their
driver-dependent render-only ioctls as DRM_RENDER_ALLOW so render
clients can use them. Driver authors must be careful not to allow any
privileged ioctls on render nodes.
With render nodes, user-space can now control access to the render node
via basic file-system access-modes. A running graphics server which
authenticates clients on the privileged primary/legacy node is no longer
required. Instead, a client can open the render node and is immediately
granted GPU access. Communication between clients (or servers) is done
via PRIME. FLINK from render node to legacy node is not supported. New
clients must not use the insecure FLINK interface.
Besides dropping all modeset/global ioctls, render nodes also drop the
DRM-Master concept. There is no reason to associate render clients with
a DRM-Master as they are independent of any graphics server. Besides,
they must work without any running master, anyway. Drivers must be able
to run without a master object if they support render nodes. If, on the
other hand, a driver requires shared state between clients which is
visible to user-space and accessible beyond open-file boundaries, they
cannot support render nodes.
VBlank event handling
=====================
The DRM core exposes two vertical blank related ioctls:
DRM_IOCTL_WAIT_VBLANK
This takes a struct drm_wait_vblank structure as its argument, and
it is used to block or request a signal when a specified vblank
event occurs.
DRM_IOCTL_MODESET_CTL
This was only used for user-mode-settind drivers around modesetting
changes to allow the kernel to update the vblank interrupt after
mode setting, since on many devices the vertical blank counter is
reset to 0 at some point during modeset. Modern drivers should not
call this any more since with kernel mode setting it is a no-op.
This second part of the GPU Driver Developer's Guide documents driver
code, implementation details and also all the driver-specific userspace
interfaces. Especially since all hardware-acceleration interfaces to
userspace are driver specific for efficiency and other reasons these
interfaces can be rather substantial. Hence every driver has its own
chapter.

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===========================
drm/i915 Intel GFX Driver
===========================
The drm/i915 driver supports all (with the exception of some very early
models) integrated GFX chipsets with both Intel display and rendering
blocks. This excludes a set of SoC platforms with an SGX rendering unit,
those have basic support through the gma500 drm driver.
Core Driver Infrastructure
==========================
This section covers core driver infrastructure used by both the display
and the GEM parts of the driver.
Runtime Power Management
------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
:doc: runtime pm
.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
:internal:
.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
:internal:
Interrupt Handling
------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
:doc: interrupt handling
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
:functions: intel_irq_init intel_irq_init_hw intel_hpd_init
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
:functions: intel_runtime_pm_disable_interrupts
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
:functions: intel_runtime_pm_enable_interrupts
Intel GVT-g Guest Support(vGPU)
-------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
:doc: Intel GVT-g guest support
.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
:internal:
Display Hardware Handling
=========================
This section covers everything related to the display hardware including
the mode setting infrastructure, plane, sprite and cursor handling and
display, output probing and related topics.
Mode Setting Infrastructure
---------------------------
The i915 driver is thus far the only DRM driver which doesn't use the
common DRM helper code to implement mode setting sequences. Thus it has
its own tailor-made infrastructure for executing a display configuration
change.
Frontbuffer Tracking
--------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.c
:doc: frontbuffer tracking
.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.c
:internal:
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem.c
:functions: i915_gem_track_fb
Display FIFO Underrun Reporting
-------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_fifo_underrun.c
:doc: fifo underrun handling
.. kernel-doc:: drivers/gpu/drm/i915/intel_fifo_underrun.c
:internal:
Plane Configuration
-------------------
This section covers plane configuration and composition with the primary
plane, sprites, cursors and overlays. This includes the infrastructure
to do atomic vsync'ed updates of all this state and also tightly coupled
topics like watermark setup and computation, framebuffer compression and
panel self refresh.
Atomic Plane Helpers
--------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_atomic_plane.c
:doc: atomic plane helpers
.. kernel-doc:: drivers/gpu/drm/i915/intel_atomic_plane.c
:internal:
Output Probing
--------------
This section covers output probing and related infrastructure like the
hotplug interrupt storm detection and mitigation code. Note that the
i915 driver still uses most of the common DRM helper code for output
probing, so those sections fully apply.
Hotplug
-------
.. kernel-doc:: drivers/gpu/drm/i915/intel_hotplug.c
:doc: Hotplug
.. kernel-doc:: drivers/gpu/drm/i915/intel_hotplug.c
:internal:
High Definition Audio
---------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
:doc: High Definition Audio over HDMI and Display Port
.. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c
:internal:
.. kernel-doc:: include/drm/i915_component.h
:internal:
Panel Self Refresh PSR (PSR/SRD)
--------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_psr.c
:doc: Panel Self Refresh (PSR/SRD)
.. kernel-doc:: drivers/gpu/drm/i915/intel_psr.c
:internal:
Frame Buffer Compression (FBC)
------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_fbc.c
:doc: Frame Buffer Compression (FBC)
.. kernel-doc:: drivers/gpu/drm/i915/intel_fbc.c
:internal:
Display Refresh Rate Switching (DRRS)
-------------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:doc: Display Refresh Rate Switching (DRRS)
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:functions: intel_dp_set_drrs_state
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:functions: intel_edp_drrs_enable
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:functions: intel_edp_drrs_disable
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:functions: intel_edp_drrs_invalidate
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:functions: intel_edp_drrs_flush
.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c
:functions: intel_dp_drrs_init
DPIO
----
.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
:doc: DPIO
CSR firmware support for DMC
----------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
:doc: csr support for dmc
.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
:internal:
Video BIOS Table (VBT)
----------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_bios.c
:doc: Video BIOS Table (VBT)
.. kernel-doc:: drivers/gpu/drm/i915/intel_bios.c
:internal:
.. kernel-doc:: drivers/gpu/drm/i915/intel_vbt_defs.h
:internal:
Memory Management and Command Submission
========================================
This sections covers all things related to the GEM implementation in the
i915 driver.
Batchbuffer Parsing
-------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
:doc: batch buffer command parser
.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
:internal:
Batchbuffer Pools
-----------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
:doc: batch pool
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c
:internal:
Logical Rings, Logical Ring Contexts and Execlists
--------------------------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c
:doc: Logical Rings, Logical Ring Contexts and Execlists
.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c
:internal:
Global GTT views
----------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
:doc: Global GTT views
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
:internal:
GTT Fences and Swizzling
------------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence.c
:internal:
Global GTT Fence Handling
~~~~~~~~~~~~~~~~~~~~~~~~~
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence.c
:doc: fence register handling
Hardware Tiling and Swizzling Details
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence.c
:doc: tiling swizzling details
Object Tiling IOCTLs
--------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
:internal:
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c
:doc: buffer object tiling
Buffer Object Eviction
----------------------
This section documents the interface functions for evicting buffer
objects to make space available in the virtual gpu address spaces. Note
that this is mostly orthogonal to shrinking buffer objects caches, which
has the goal to make main memory (shared with the gpu through the
unified memory architecture) available.
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
:internal:
Buffer Object Memory Shrinking
------------------------------
This section documents the interface function for shrinking memory usage
of buffer object caches. Shrinking is used to make main memory
available. Note that this is mostly orthogonal to evicting buffer
objects, which has the goal to make space in gpu virtual address spaces.
.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c
:internal:
GuC
===
GuC-specific firmware loader
----------------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
:doc: GuC-specific firmware loader
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
:internal:
GuC-based command submission
----------------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_guc_submission.c
:doc: GuC-based command submission
.. kernel-doc:: drivers/gpu/drm/i915/i915_guc_submission.c
:internal:
GuC Firmware Layout
-------------------
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
:doc: GuC Firmware Layout
Tracing
=======
This sections covers all things related to the tracepoints implemented
in the i915 driver.
i915_ppgtt_create and i915_ppgtt_release
----------------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
:doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
i915_context_create and i915_context_free
-----------------------------------------
.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
:doc: i915_context_create and i915_context_free tracepoints
switch_mm
---------
.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
:doc: switch_mm tracepoint
.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c

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==================================
Linux GPU Driver Developer's Guide
==================================
.. toctree::
introduction
drm-internals
drm-mm
drm-kms
drm-kms-helpers
drm-uapi
i915
vga-switcheroo

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============
Introduction
============
The Linux DRM layer contains code intended to support the needs of
complex graphics devices, usually containing programmable pipelines well
suited to 3D graphics acceleration. Graphics drivers in the kernel may
make use of DRM functions to make tasks like memory management,
interrupt handling and DMA easier, and provide a uniform interface to
applications.
A note on versions: this guide covers features found in the DRM tree,
including the TTM memory manager, output configuration and mode setting,
and the new vblank internals, in addition to all the regular features
found in current kernels.
[Insert diagram of typical DRM stack here]
Style Guidelines
================
For consistency this documentation uses American English. Abbreviations
are written as all-uppercase, for example: DRM, KMS, IOCTL, CRTC, and so
on. To aid in reading, documentations make full use of the markup
characters kerneldoc provides: @parameter for function parameters,
@member for structure members, &structure to reference structures and
function() for functions. These all get automatically hyperlinked if
kerneldoc for the referenced objects exists. When referencing entries in
function vtables please use ->vfunc(). Note that kerneldoc does not
support referencing struct members directly, so please add a reference
to the vtable struct somewhere in the same paragraph or at least
section.
Except in special situations (to separate locked from unlocked variants)
locking requirements for functions aren't documented in the kerneldoc.
Instead locking should be check at runtime using e.g.
``WARN_ON(!mutex_is_locked(...));``. Since it's much easier to ignore
documentation than runtime noise this provides more value. And on top of
that runtime checks do need to be updated when the locking rules change,
increasing the chances that they're correct. Within the documentation
the locking rules should be explained in the relevant structures: Either
in the comment for the lock explaining what it protects, or data fields
need a note about which lock protects them, or both.
Functions which have a non-\ ``void`` return value should have a section
called "Returns" explaining the expected return values in different
cases and their meanings. Currently there's no consensus whether that
section name should be all upper-case or not, and whether it should end
in a colon or not. Go with the file-local style. Other common section
names are "Notes" with information for dangerous or tricky corner cases,
and "FIXME" where the interface could be cleaned up.

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Owner Module/Drivers,Group,Property Name,Type,Property Values,Object attached,Description/Restrictions
DRM,Generic,“rotation”,BITMASK,"{ 0, ""rotate-0"" }, { 1, ""rotate-90"" }, { 2, ""rotate-180"" }, { 3, ""rotate-270"" }, { 4, ""reflect-x"" }, { 5, ""reflect-y"" }","CRTC, Plane",rotate-(degrees) rotates the image by the specified amount in degrees in counter clockwise direction. reflect-x and reflect-y reflects the image along the specified axis prior to rotation
,,“scaling mode”,ENUM,"{ ""None"", ""Full"", ""Center"", ""Full aspect"" }",Connector,"Supported by: amdgpu, gma500, i915, nouveau and radeon."
,Connector,“EDID”,BLOB | IMMUTABLE,0,Connector,Contains id of edid blob ptr object.
,,“DPMS”,ENUM,"{ “On”, “Standby”, “Suspend”, “Off” }",Connector,Contains DPMS operation mode value.
,,“PATH”,BLOB | IMMUTABLE,0,Connector,Contains topology path to a connector.
,,“TILE”,BLOB | IMMUTABLE,0,Connector,Contains tiling information for a connector.
,,“CRTC_ID”,OBJECT,DRM_MODE_OBJECT_CRTC,Connector,CRTC that connector is attached to (atomic)
,Plane,“type”,ENUM | IMMUTABLE,"{ ""Overlay"", ""Primary"", ""Cursor"" }",Plane,Plane type
,,“SRC_X”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source x coordinate in 16.16 fixed point (atomic)
,,“SRC_Y”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source y coordinate in 16.16 fixed point (atomic)
,,“SRC_W”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source width in 16.16 fixed point (atomic)
,,“SRC_H”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source height in 16.16 fixed point (atomic)
,,“CRTC_X”,SIGNED_RANGE,"Min=INT_MIN, Max=INT_MAX",Plane,Scanout CRTC (destination) x coordinate (atomic)
,,“CRTC_Y”,SIGNED_RANGE,"Min=INT_MIN, Max=INT_MAX",Plane,Scanout CRTC (destination) y coordinate (atomic)
,,“CRTC_W”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout CRTC (destination) width (atomic)
,,“CRTC_H”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout CRTC (destination) height (atomic)
,,“FB_ID”,OBJECT,DRM_MODE_OBJECT_FB,Plane,Scanout framebuffer (atomic)
,,“CRTC_ID”,OBJECT,DRM_MODE_OBJECT_CRTC,Plane,CRTC that plane is attached to (atomic)
,DVI-I,“subconnector”,ENUM,"{ “Unknown”, “DVI-D”, “DVI-A” }",Connector,TBD
,,“select subconnector”,ENUM,"{ “Automatic”, “DVI-D”, “DVI-A” }",Connector,TBD
,TV,“subconnector”,ENUM,"{ ""Unknown"", ""Composite"", ""SVIDEO"", ""Component"", ""SCART"" }",Connector,TBD
,,“select subconnector”,ENUM,"{ ""Automatic"", ""Composite"", ""SVIDEO"", ""Component"", ""SCART"" }",Connector,TBD
,,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD
,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD
,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD
,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD
,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD
,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD
,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD
,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD
,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD
,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD
,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD
,Virtual GPU,“suggested X”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an X offset for a connector
,,“suggested Y”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an Y offset for a connector
,Optional,"""aspect ratio""",ENUM,"{ ""None"", ""4:3"", ""16:9"" }",Connector,TDB
,,“dirty”,ENUM | IMMUTABLE,"{ ""Off"", ""On"", ""Annotate"" }",Connector,TBD
,,“DEGAMMA_LUT”,BLOB,0,CRTC,DRM property to set the degamma lookup table (LUT) mapping pixel data from the framebuffer before it is given to the transformation matrix. The data is an interpreted as an array of struct drm_color_lut elements. Hardware might choose not to use the full precision of the LUT elements nor use all the elements of the LUT (for example the hardware might choose to interpolate between LUT[0] and LUT[4]).
,,“DEGAMMA_LUT_SIZE”,RANGE | IMMUTABLE,"Min=0, Max=UINT_MAX",CRTC,DRM property to gives the size of the lookup table to be set on the DEGAMMA_LUT property (the size depends on the underlying hardware).
,,“CTM”,BLOB,0,CRTC,DRM property to set the current transformation matrix (CTM) apply to pixel data after the lookup through the degamma LUT and before the lookup through the gamma LUT. The data is an interpreted as a struct drm_color_ctm.
,,“GAMMA_LUT”,BLOB,0,CRTC,DRM property to set the gamma lookup table (LUT) mapping pixel data after to the transformation matrix to data sent to the connector. The data is an interpreted as an array of struct drm_color_lut elements. Hardware might choose not to use the full precision of the LUT elements nor use all the elements of the LUT (for example the hardware might choose to interpolate between LUT[0] and LUT[4]).
,,“GAMMA_LUT_SIZE”,RANGE | IMMUTABLE,"Min=0, Max=UINT_MAX",CRTC,DRM property to gives the size of the lookup table to be set on the GAMMA_LUT property (the size depends on the underlying hardware).
i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", ""Limited 16:235"" }",Connector,"When this property is set to Limited 16:235 and CTM is set, the hardware will be programmed with the result of the multiplication of CTM by the limited range matrix to ensure the pixels normaly in the range 0..1.0 are remapped to the range 16/255..235/255."
,,“audio”,ENUM,"{ ""force-dvi"", ""off"", ""auto"", ""on"" }",Connector,TBD
,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD
,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,"""right_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,"""top_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,"""bottom_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“hpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“vpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“contrast”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“saturation”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“hue”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“sharpness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“flicker_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“flicker_filter_adaptive”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“flicker_filter_2d”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“tv_chroma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“tv_luma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD
,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
CDV gma-500,Generic,"""Broadcast RGB""",ENUM,"{ “Full”, “Limited 16:235” }",Connector,TBD
,,"""Broadcast RGB""",ENUM,"{ “off”, “auto”, “on” }",Connector,TBD
Poulsbo,Generic,“backlight”,RANGE,"Min=0, Max=100",Connector,TBD
,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD
,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,"""right_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,"""top_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,"""bottom_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“hpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“vpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“contrast”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“saturation”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“hue”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“sharpness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“flicker_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“flicker_filter_adaptive”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“flicker_filter_2d”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“tv_chroma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“tv_luma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD
,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD
armada,CRTC,"""CSC_YUV""",ENUM,"{ ""Auto"" , ""CCIR601"", ""CCIR709"" }",CRTC,TBD
,,"""CSC_RGB""",ENUM,"{ ""Auto"", ""Computer system"", ""Studio"" }",CRTC,TBD
,Overlay,"""colorkey""",RANGE,"Min=0, Max=0xffffff",Plane,TBD
,,"""colorkey_min""",RANGE,"Min=0, Max=0xffffff",Plane,TBD
,,"""colorkey_max""",RANGE,"Min=0, Max=0xffffff",Plane,TBD
,,"""colorkey_val""",RANGE,"Min=0, Max=0xffffff",Plane,TBD
,,"""colorkey_alpha""",RANGE,"Min=0, Max=0xffffff",Plane,TBD
,,"""colorkey_mode""",ENUM,"{ ""disabled"", ""Y component"", ""U component"" , ""V component"", ""RGB"", “R component"", ""G component"", ""B component"" }",Plane,TBD
,,"""brightness""",RANGE,"Min=0, Max=256 + 255",Plane,TBD
,,"""contrast""",RANGE,"Min=0, Max=0x7fff",Plane,TBD
,,"""saturation""",RANGE,"Min=0, Max=0x7fff",Plane,TBD
exynos,CRTC,“mode”,ENUM,"{ ""normal"", ""blank"" }",CRTC,TBD
,Overlay,“zpos”,RANGE,"Min=0, Max=MAX_PLANE-1",Plane,TBD
i2c/ch7006_drv,Generic,“scale”,RANGE,"Min=0, Max=2",Connector,TBD
,TV,“mode”,ENUM,"{ ""PAL"", ""PAL-M"",""PAL-N""}, ”PAL-Nc"" , ""PAL-60"", ""NTSC-M"", ""NTSC-J"" }",Connector,TBD
nouveau,NV10 Overlay,"""colorkey""",RANGE,"Min=0, Max=0x01ffffff",Plane,TBD
,,“contrast”,RANGE,"Min=0, Max=8192-1",Plane,TBD
,,“brightness”,RANGE,"Min=0, Max=1024",Plane,TBD
,,“hue”,RANGE,"Min=0, Max=359",Plane,TBD
,,“saturation”,RANGE,"Min=0, Max=8192-1",Plane,TBD
,,“iturbt_709”,RANGE,"Min=0, Max=1",Plane,TBD
,Nv04 Overlay,“colorkey”,RANGE,"Min=0, Max=0x01ffffff",Plane,TBD
,,“brightness”,RANGE,"Min=0, Max=1024",Plane,TBD
,Display,“dithering mode”,ENUM,"{ ""auto"", ""off"", ""on"" }",Connector,TBD
,,“dithering depth”,ENUM,"{ ""auto"", ""off"", ""on"", ""static 2x2"", ""dynamic 2x2"", ""temporal"" }",Connector,TBD
,,“underscan”,ENUM,"{ ""auto"", ""6 bpc"", ""8 bpc"" }",Connector,TBD
,,“underscan hborder”,RANGE,"Min=0, Max=128",Connector,TBD
,,“underscan vborder”,RANGE,"Min=0, Max=128",Connector,TBD
,,“vibrant hue”,RANGE,"Min=0, Max=180",Connector,TBD
,,“color vibrance”,RANGE,"Min=0, Max=200",Connector,TBD
omap,Generic,“zorder”,RANGE,"Min=0, Max=3","CRTC, Plane",TBD
qxl,Generic,"“hotplug_mode_update""",RANGE,"Min=0, Max=1",Connector,TBD
radeon,DVI-I,“coherent”,RANGE,"Min=0, Max=1",Connector,TBD
,DAC enable load detect,“load detection”,RANGE,"Min=0, Max=1",Connector,TBD
,TV Standard,"""tv standard""",ENUM,"{ ""ntsc"", ""pal"", ""pal-m"", ""pal-60"", ""ntsc-j"" , ""scart-pal"", ""pal-cn"", ""secam"" }",Connector,TBD
,legacy TMDS PLL detect,"""tmds_pll""",ENUM,"{ ""driver"", ""bios"" }",-,TBD
,Underscan,"""underscan""",ENUM,"{ ""off"", ""on"", ""auto"" }",Connector,TBD
,,"""underscan hborder""",RANGE,"Min=0, Max=128",Connector,TBD
,,"""underscan vborder""",RANGE,"Min=0, Max=128",Connector,TBD
,Audio,“audio”,ENUM,"{ ""off"", ""on"", ""auto"" }",Connector,TBD
,FMT Dithering,“dither”,ENUM,"{ ""off"", ""on"" }",Connector,TBD
rcar-du,Generic,"""alpha""",RANGE,"Min=0, Max=255",Plane,TBD
,,"""colorkey""",RANGE,"Min=0, Max=0x01ffffff",Plane,TBD
,,"""zpos""",RANGE,"Min=1, Max=7",Plane,TBD
1 Owner Module/Drivers Group Property Name Type Property Values Object attached Description/Restrictions
2 DRM Generic “rotation” BITMASK { 0, "rotate-0" }, { 1, "rotate-90" }, { 2, "rotate-180" }, { 3, "rotate-270" }, { 4, "reflect-x" }, { 5, "reflect-y" } CRTC, Plane rotate-(degrees) rotates the image by the specified amount in degrees in counter clockwise direction. reflect-x and reflect-y reflects the image along the specified axis prior to rotation
3 “scaling mode” ENUM { "None", "Full", "Center", "Full aspect" } Connector Supported by: amdgpu, gma500, i915, nouveau and radeon.
4 Connector “EDID” BLOB | IMMUTABLE 0 Connector Contains id of edid blob ptr object.
5 “DPMS” ENUM { “On”, “Standby”, “Suspend”, “Off” } Connector Contains DPMS operation mode value.
6 “PATH” BLOB | IMMUTABLE 0 Connector Contains topology path to a connector.
7 “TILE” BLOB | IMMUTABLE 0 Connector Contains tiling information for a connector.
8 “CRTC_ID” OBJECT DRM_MODE_OBJECT_CRTC Connector CRTC that connector is attached to (atomic)
9 Plane “type” ENUM | IMMUTABLE { "Overlay", "Primary", "Cursor" } Plane Plane type
10 “SRC_X” RANGE Min=0, Max=UINT_MAX Plane Scanout source x coordinate in 16.16 fixed point (atomic)
11 “SRC_Y” RANGE Min=0, Max=UINT_MAX Plane Scanout source y coordinate in 16.16 fixed point (atomic)
12 “SRC_W” RANGE Min=0, Max=UINT_MAX Plane Scanout source width in 16.16 fixed point (atomic)
13 “SRC_H” RANGE Min=0, Max=UINT_MAX Plane Scanout source height in 16.16 fixed point (atomic)
14 “CRTC_X” SIGNED_RANGE Min=INT_MIN, Max=INT_MAX Plane Scanout CRTC (destination) x coordinate (atomic)
15 “CRTC_Y” SIGNED_RANGE Min=INT_MIN, Max=INT_MAX Plane Scanout CRTC (destination) y coordinate (atomic)
16 “CRTC_W” RANGE Min=0, Max=UINT_MAX Plane Scanout CRTC (destination) width (atomic)
17 “CRTC_H” RANGE Min=0, Max=UINT_MAX Plane Scanout CRTC (destination) height (atomic)
18 “FB_ID” OBJECT DRM_MODE_OBJECT_FB Plane Scanout framebuffer (atomic)
19 “CRTC_ID” OBJECT DRM_MODE_OBJECT_CRTC Plane CRTC that plane is attached to (atomic)
20 DVI-I “subconnector” ENUM { “Unknown”, “DVI-D”, “DVI-A” } Connector TBD
21 “select subconnector” ENUM { “Automatic”, “DVI-D”, “DVI-A” } Connector TBD
22 TV “subconnector” ENUM { "Unknown", "Composite", "SVIDEO", "Component", "SCART" } Connector TBD
23 “select subconnector” ENUM { "Automatic", "Composite", "SVIDEO", "Component", "SCART" } Connector TBD
24 “mode” ENUM { "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B" } etc. Connector TBD
25 “left margin” RANGE Min=0, Max=100 Connector TBD
26 “right margin” RANGE Min=0, Max=100 Connector TBD
27 “top margin” RANGE Min=0, Max=100 Connector TBD
28 “bottom margin” RANGE Min=0, Max=100 Connector TBD
29 “brightness” RANGE Min=0, Max=100 Connector TBD
30 “contrast” RANGE Min=0, Max=100 Connector TBD
31 “flicker reduction” RANGE Min=0, Max=100 Connector TBD
32 “overscan” RANGE Min=0, Max=100 Connector TBD
33 “saturation” RANGE Min=0, Max=100 Connector TBD
34 “hue” RANGE Min=0, Max=100 Connector TBD
35 Virtual GPU “suggested X” RANGE Min=0, Max=0xffffffff Connector property to suggest an X offset for a connector
36 “suggested Y” RANGE Min=0, Max=0xffffffff Connector property to suggest an Y offset for a connector
37 Optional "aspect ratio" ENUM { "None", "4:3", "16:9" } Connector TDB
38 “dirty” ENUM | IMMUTABLE { "Off", "On", "Annotate" } Connector TBD
39 “DEGAMMA_LUT” BLOB 0 CRTC DRM property to set the degamma lookup table (LUT) mapping pixel data from the framebuffer before it is given to the transformation matrix. The data is an interpreted as an array of struct drm_color_lut elements. Hardware might choose not to use the full precision of the LUT elements nor use all the elements of the LUT (for example the hardware might choose to interpolate between LUT[0] and LUT[4]).
40 “DEGAMMA_LUT_SIZE” RANGE | IMMUTABLE Min=0, Max=UINT_MAX CRTC DRM property to gives the size of the lookup table to be set on the DEGAMMA_LUT property (the size depends on the underlying hardware).
41 “CTM” BLOB 0 CRTC DRM property to set the current transformation matrix (CTM) apply to pixel data after the lookup through the degamma LUT and before the lookup through the gamma LUT. The data is an interpreted as a struct drm_color_ctm.
42 “GAMMA_LUT” BLOB 0 CRTC DRM property to set the gamma lookup table (LUT) mapping pixel data after to the transformation matrix to data sent to the connector. The data is an interpreted as an array of struct drm_color_lut elements. Hardware might choose not to use the full precision of the LUT elements nor use all the elements of the LUT (for example the hardware might choose to interpolate between LUT[0] and LUT[4]).
43 “GAMMA_LUT_SIZE” RANGE | IMMUTABLE Min=0, Max=UINT_MAX CRTC DRM property to gives the size of the lookup table to be set on the GAMMA_LUT property (the size depends on the underlying hardware).
44 i915 Generic "Broadcast RGB" ENUM { "Automatic", "Full", "Limited 16:235" } Connector When this property is set to Limited 16:235 and CTM is set, the hardware will be programmed with the result of the multiplication of CTM by the limited range matrix to ensure the pixels normaly in the range 0..1.0 are remapped to the range 16/255..235/255.
45 “audio” ENUM { "force-dvi", "off", "auto", "on" } Connector TBD
46 SDVO-TV “mode” ENUM { "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B" } etc. Connector TBD
47 "left_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
48 "right_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
49 "top_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
50 "bottom_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
51 “hpos” RANGE Min=0, Max= SDVO dependent Connector TBD
52 “vpos” RANGE Min=0, Max= SDVO dependent Connector TBD
53 “contrast” RANGE Min=0, Max= SDVO dependent Connector TBD
54 “saturation” RANGE Min=0, Max= SDVO dependent Connector TBD
55 “hue” RANGE Min=0, Max= SDVO dependent Connector TBD
56 “sharpness” RANGE Min=0, Max= SDVO dependent Connector TBD
57 “flicker_filter” RANGE Min=0, Max= SDVO dependent Connector TBD
58 “flicker_filter_adaptive” RANGE Min=0, Max= SDVO dependent Connector TBD
59 “flicker_filter_2d” RANGE Min=0, Max= SDVO dependent Connector TBD
60 “tv_chroma_filter” RANGE Min=0, Max= SDVO dependent Connector TBD
61 “tv_luma_filter” RANGE Min=0, Max= SDVO dependent Connector TBD
62 “dot_crawl” RANGE Min=0, Max=1 Connector TBD
63 SDVO-TV/LVDS “brightness” RANGE Min=0, Max= SDVO dependent Connector TBD
64 CDV gma-500 Generic "Broadcast RGB" ENUM { “Full”, “Limited 16:235” } Connector TBD
65 "Broadcast RGB" ENUM { “off”, “auto”, “on” } Connector TBD
66 Poulsbo Generic “backlight” RANGE Min=0, Max=100 Connector TBD
67 SDVO-TV “mode” ENUM { "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B" } etc. Connector TBD
68 "left_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
69 "right_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
70 "top_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
71 "bottom_margin" RANGE Min=0, Max= SDVO dependent Connector TBD
72 “hpos” RANGE Min=0, Max= SDVO dependent Connector TBD
73 “vpos” RANGE Min=0, Max= SDVO dependent Connector TBD
74 “contrast” RANGE Min=0, Max= SDVO dependent Connector TBD
75 “saturation” RANGE Min=0, Max= SDVO dependent Connector TBD
76 “hue” RANGE Min=0, Max= SDVO dependent Connector TBD
77 “sharpness” RANGE Min=0, Max= SDVO dependent Connector TBD
78 “flicker_filter” RANGE Min=0, Max= SDVO dependent Connector TBD
79 “flicker_filter_adaptive” RANGE Min=0, Max= SDVO dependent Connector TBD
80 “flicker_filter_2d” RANGE Min=0, Max= SDVO dependent Connector TBD
81 “tv_chroma_filter” RANGE Min=0, Max= SDVO dependent Connector TBD
82 “tv_luma_filter” RANGE Min=0, Max= SDVO dependent Connector TBD
83 “dot_crawl” RANGE Min=0, Max=1 Connector TBD
84 SDVO-TV/LVDS “brightness” RANGE Min=0, Max= SDVO dependent Connector TBD
85 armada CRTC "CSC_YUV" ENUM { "Auto" , "CCIR601", "CCIR709" } CRTC TBD
86 "CSC_RGB" ENUM { "Auto", "Computer system", "Studio" } CRTC TBD
87 Overlay "colorkey" RANGE Min=0, Max=0xffffff Plane TBD
88 "colorkey_min" RANGE Min=0, Max=0xffffff Plane TBD
89 "colorkey_max" RANGE Min=0, Max=0xffffff Plane TBD
90 "colorkey_val" RANGE Min=0, Max=0xffffff Plane TBD
91 "colorkey_alpha" RANGE Min=0, Max=0xffffff Plane TBD
92 "colorkey_mode" ENUM { "disabled", "Y component", "U component" , "V component", "RGB", “R component", "G component", "B component" } Plane TBD
93 "brightness" RANGE Min=0, Max=256 + 255 Plane TBD
94 "contrast" RANGE Min=0, Max=0x7fff Plane TBD
95 "saturation" RANGE Min=0, Max=0x7fff Plane TBD
96 exynos CRTC “mode” ENUM { "normal", "blank" } CRTC TBD
97 Overlay “zpos” RANGE Min=0, Max=MAX_PLANE-1 Plane TBD
98 i2c/ch7006_drv Generic “scale” RANGE Min=0, Max=2 Connector TBD
99 TV “mode” ENUM { "PAL", "PAL-M","PAL-N"}, ”PAL-Nc" , "PAL-60", "NTSC-M", "NTSC-J" } Connector TBD
100 nouveau NV10 Overlay "colorkey" RANGE Min=0, Max=0x01ffffff Plane TBD
101 “contrast” RANGE Min=0, Max=8192-1 Plane TBD
102 “brightness” RANGE Min=0, Max=1024 Plane TBD
103 “hue” RANGE Min=0, Max=359 Plane TBD
104 “saturation” RANGE Min=0, Max=8192-1 Plane TBD
105 “iturbt_709” RANGE Min=0, Max=1 Plane TBD
106 Nv04 Overlay “colorkey” RANGE Min=0, Max=0x01ffffff Plane TBD
107 “brightness” RANGE Min=0, Max=1024 Plane TBD
108 Display “dithering mode” ENUM { "auto", "off", "on" } Connector TBD
109 “dithering depth” ENUM { "auto", "off", "on", "static 2x2", "dynamic 2x2", "temporal" } Connector TBD
110 “underscan” ENUM { "auto", "6 bpc", "8 bpc" } Connector TBD
111 “underscan hborder” RANGE Min=0, Max=128 Connector TBD
112 “underscan vborder” RANGE Min=0, Max=128 Connector TBD
113 “vibrant hue” RANGE Min=0, Max=180 Connector TBD
114 “color vibrance” RANGE Min=0, Max=200 Connector TBD
115 omap Generic “zorder” RANGE Min=0, Max=3 CRTC, Plane TBD
116 qxl Generic “hotplug_mode_update" RANGE Min=0, Max=1 Connector TBD
117 radeon DVI-I “coherent” RANGE Min=0, Max=1 Connector TBD
118 DAC enable load detect “load detection” RANGE Min=0, Max=1 Connector TBD
119 TV Standard "tv standard" ENUM { "ntsc", "pal", "pal-m", "pal-60", "ntsc-j" , "scart-pal", "pal-cn", "secam" } Connector TBD
120 legacy TMDS PLL detect "tmds_pll" ENUM { "driver", "bios" } - TBD
121 Underscan "underscan" ENUM { "off", "on", "auto" } Connector TBD
122 "underscan hborder" RANGE Min=0, Max=128 Connector TBD
123 "underscan vborder" RANGE Min=0, Max=128 Connector TBD
124 Audio “audio” ENUM { "off", "on", "auto" } Connector TBD
125 FMT Dithering “dither” ENUM { "off", "on" } Connector TBD
126 rcar-du Generic "alpha" RANGE Min=0, Max=255 Plane TBD
127 "colorkey" RANGE Min=0, Max=0x01ffffff Plane TBD
128 "zpos" RANGE Min=1, Max=7 Plane TBD

102
Documentation/gpu/vga-switcheroo.rst Normal file
View File

@ -0,0 +1,102 @@
==============
VGA Switcheroo
==============
.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
:doc: Overview
Modes of Use
============
Manual switching and manual power control
-----------------------------------------
.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
:doc: Manual switching and manual power control
Driver power control
--------------------
.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
:doc: Driver power control
API
===
Public functions
----------------
.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
:export:
Public structures
-----------------
.. kernel-doc:: include/linux/vga_switcheroo.h
:functions: vga_switcheroo_handler
.. kernel-doc:: include/linux/vga_switcheroo.h
:functions: vga_switcheroo_client_ops
Public constants
----------------
.. kernel-doc:: include/linux/vga_switcheroo.h
:functions: vga_switcheroo_handler_flags_t
.. kernel-doc:: include/linux/vga_switcheroo.h
:functions: vga_switcheroo_client_id
.. kernel-doc:: include/linux/vga_switcheroo.h
:functions: vga_switcheroo_state
Private structures
------------------
.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
:functions: vgasr_priv
.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
:functions: vga_switcheroo_client
Handlers
========
apple-gmux Handler
------------------
.. kernel-doc:: drivers/platform/x86/apple-gmux.c
:doc: Overview
.. kernel-doc:: drivers/platform/x86/apple-gmux.c
:doc: Interrupt
Graphics mux
~~~~~~~~~~~~
.. kernel-doc:: drivers/platform/x86/apple-gmux.c
:doc: Graphics mux
Power control
~~~~~~~~~~~~~
.. kernel-doc:: drivers/platform/x86/apple-gmux.c
:doc: Power control
Backlight control
~~~~~~~~~~~~~~~~~
.. kernel-doc:: drivers/platform/x86/apple-gmux.c
:doc: Backlight control
Public functions
~~~~~~~~~~~~~~~~
.. kernel-doc:: include/linux/apple-gmux.h
:internal:
.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/vga/vga_switcheroo.c
.. WARNING: DOCPROC directive not supported: !Cinclude/linux/vga_switcheroo.h
.. WARNING: DOCPROC directive not supported: !Cdrivers/platform/x86/apple-gmux.c

1
Documentation/index.rst
View File

@ -13,6 +13,7 @@ Contents:
.. toctree::
:maxdepth: 2
gpu/index
Indices and tables
==================

13
MAINTAINERS
View File

@ -865,9 +865,17 @@ F: Documentation/devicetree/bindings/display/snps,arcpgu.txt
ARM HDLCD DRM DRIVER
M: Liviu Dudau <liviu.dudau@arm.com>
S: Supported
F: drivers/gpu/drm/arm/
F: drivers/gpu/drm/arm/hdlcd_*
F: Documentation/devicetree/bindings/display/arm,hdlcd.txt
ARM MALI-DP DRM DRIVER
M: Liviu Dudau <liviu.dudau@arm.com>
M: Brian Starkey <brian.starkey@arm.com>
M: Mali DP Maintainers <malidp@foss.arm.com>
S: Supported
F: drivers/gpu/drm/arm/
F: Documentation/devicetree/bindings/display/arm,malidp.txt
ARM MFM AND FLOPPY DRIVERS
M: Ian Molton <spyro@f2s.com>
S: Maintained
@ -3857,7 +3865,7 @@ F: drivers/gpu/vga/
F: Documentation/devicetree/bindings/display/
F: Documentation/devicetree/bindings/gpu/
F: Documentation/devicetree/bindings/video/
F: Documentation/DocBook/gpu.*
F: Documentation/gpu/
F: include/drm/
F: include/uapi/drm/
@ -3909,6 +3917,7 @@ S: Supported
F: drivers/gpu/drm/i915/
F: include/drm/i915*
F: include/uapi/drm/i915_drm.h
F: Documentation/gpu/i915.rst
DRM DRIVERS FOR ATMEL HLCDC
M: Boris Brezillon <boris.brezillon@free-electrons.com>

44
drivers/dma-buf/dma-buf.c
View File

@ -824,7 +824,7 @@ void dma_buf_vunmap(struct dma_buf *dmabuf, void *vaddr)
EXPORT_SYMBOL_GPL(dma_buf_vunmap);
#ifdef CONFIG_DEBUG_FS
static int dma_buf_describe(struct seq_file *s)
static int dma_buf_debug_show(struct seq_file *s, void *unused)
{
int ret;
struct dma_buf *buf_obj;
@ -879,17 +879,9 @@ static int dma_buf_describe(struct seq_file *s)
return 0;
}
static int dma_buf_show(struct seq_file *s, void *unused)
{
void (*func)(struct seq_file *) = s->private;
func(s);
return 0;
}
static int dma_buf_debug_open(struct inode *inode, struct file *file)
{
return single_open(file, dma_buf_show, inode->i_private);
return single_open(file, dma_buf_debug_show, NULL);
}
static const struct file_operations dma_buf_debug_fops = {
@ -903,20 +895,23 @@ static struct dentry *dma_buf_debugfs_dir;
static int dma_buf_init_debugfs(void)
{
struct dentry *d;
int err = 0;
dma_buf_debugfs_dir = debugfs_create_dir("dma_buf", NULL);
d = debugfs_create_dir("dma_buf", NULL);
if (IS_ERR(d))
return PTR_ERR(d);
if (IS_ERR(dma_buf_debugfs_dir)) {
err = PTR_ERR(dma_buf_debugfs_dir);
dma_buf_debugfs_dir = NULL;
return err;
}
dma_buf_debugfs_dir = d;
err = dma_buf_debugfs_create_file("bufinfo", dma_buf_describe);
if (err)
d = debugfs_create_file("bufinfo", S_IRUGO, dma_buf_debugfs_dir,
NULL, &dma_buf_debug_fops);
if (IS_ERR(d)) {
pr_debug("dma_buf: debugfs: failed to create node bufinfo\n");
debugfs_remove_recursive(dma_buf_debugfs_dir);
dma_buf_debugfs_dir = NULL;
err = PTR_ERR(d);
}
return err;
}
@ -926,17 +921,6 @@ static void dma_buf_uninit_debugfs(void)
if (dma_buf_debugfs_dir)
debugfs_remove_recursive(dma_buf_debugfs_dir);
}
int dma_buf_debugfs_create_file(const char *name,
int (*write)(struct seq_file *))
{
struct dentry *d;
d = debugfs_create_file(name, S_IRUGO, dma_buf_debugfs_dir,
write, &dma_buf_debug_fops);
return PTR_ERR_OR_ZERO(d);
}
#else
static inline int dma_buf_init_debugfs(void)
{

4
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
View File

@ -187,12 +187,12 @@ int init_pipelines(struct device_queue_manager *dqm,
unsigned int get_first_pipe(struct device_queue_manager *dqm);
unsigned int get_pipes_num(struct device_queue_manager *dqm);
extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
{
return (pdd->lds_base >> 16) & 0xFF;
}
extern inline unsigned int
static inline unsigned int
get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
{
return (pdd->lds_base >> 60) & 0x0E;

3
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
View File

@ -617,10 +617,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd);
int kfd_init_apertures(struct kfd_process *process);
/* Queue Context Management */
inline uint32_t lower_32(uint64_t x);
inline uint32_t upper_32(uint64_t x);
struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd);
inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m);
int init_queue(struct queue **q, struct queue_properties properties);
void uninit_queue(struct queue *q);

8
drivers/gpu/drm/arc/arcpgu_drv.c
View File

@ -211,15 +211,8 @@ static int arcpgu_probe(struct platform_device *pdev)
if (ret)
goto err_unload;
ret = drm_connector_register_all(drm);
if (ret)
goto err_unregister;
return 0;
err_unregister:
drm_dev_unregister(drm);
err_unload:
arcpgu_unload(drm);
@ -233,7 +226,6 @@ static int arcpgu_remove(struct platform_device *pdev)
{
struct drm_device *drm = platform_get_drvdata(pdev);
drm_connector_unregister_all(drm);
drm_dev_unregister(drm);
arcpgu_unload(drm);
drm_dev_unref(drm);

16
drivers/gpu/drm/arm/Kconfig
View File

@ -25,3 +25,19 @@ config DRM_HDLCD_SHOW_UNDERRUN
Enable this option to show in red colour the pixels that the
HDLCD device did not fetch from framebuffer due to underrun
conditions.
config DRM_MALI_DISPLAY
tristate "ARM Mali Display Processor"
depends on DRM && OF && (ARM || ARM64)
depends on COMMON_CLK
select DRM_ARM
select DRM_KMS_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
select VIDEOMODE_HELPERS
help
Choose this option if you want to compile the ARM Mali Display
Processor driver. It supports the DP500, DP550 and DP650 variants
of the hardware.
If compiled as a module it will be called mali-dp.

2
drivers/gpu/drm/arm/Makefile
View File

@ -1,2 +1,4 @@
hdlcd-y := hdlcd_drv.o hdlcd_crtc.o
obj-$(CONFIG_DRM_HDLCD) += hdlcd.o
mali-dp-y := malidp_drv.o malidp_hw.o malidp_planes.o malidp_crtc.o
obj-$(CONFIG_DRM_MALI_DISPLAY) += mali-dp.o

216
drivers/gpu/drm/arm/malidp_crtc.c Normal file
View File

@ -0,0 +1,216 @@
/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP500/DP550/DP650 driver (crtc operations)
*/
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <linux/clk.h>
#include <video/videomode.h>
#include "malidp_drv.h"
#include "malidp_hw.h"
static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
struct malidp_hw_device *hwdev = malidp->dev;
/*
* check that the hardware can drive the required clock rate,
* but skip the check if the clock is meant to be disabled (req_rate = 0)
*/
long rate, req_rate = mode->crtc_clock * 1000;
if (req_rate) {
rate = clk_round_rate(hwdev->mclk, req_rate);
if (rate < req_rate) {
DRM_DEBUG_DRIVER("mclk clock unable to reach %d kHz\n",
mode->crtc_clock);
return false;
}
rate = clk_round_rate(hwdev->pxlclk, req_rate);
if (rate != req_rate) {
DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
req_rate);
return false;
}
}
return true;
}
static void malidp_crtc_enable(struct drm_crtc *crtc)
{
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
struct malidp_hw_device *hwdev = malidp->dev;
struct videomode vm;
drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
clk_prepare_enable(hwdev->pxlclk);
/* mclk needs to be set to the same or higher rate than pxlclk */
clk_set_rate(hwdev->mclk, crtc->state->adjusted_mode.crtc_clock * 1000);
clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
hwdev->modeset(hwdev, &vm);
hwdev->leave_config_mode(hwdev);
drm_crtc_vblank_on(crtc);
}
static void malidp_crtc_disable(struct drm_crtc *crtc)
{
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
struct malidp_hw_device *hwdev = malidp->dev;
drm_crtc_vblank_off(crtc);
hwdev->enter_config_mode(hwdev);
clk_disable_unprepare(hwdev->pxlclk);
}
static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
struct malidp_hw_device *hwdev = malidp->dev;
struct drm_plane *plane;
const struct drm_plane_state *pstate;
u32 rot_mem_free, rot_mem_usable;
int rotated_planes = 0;
/*
* check if there is enough rotation memory available for planes
* that need 90° and 270° rotation. Each plane has set its required
* memory size in the ->plane_check() callback, here we only make
* sure that the sums are less that the total usable memory.
*
* The rotation memory allocation algorithm (for each plane):
* a. If no more rotated planes exist, all remaining rotate
* memory in the bank is available for use by the plane.
* b. If other rotated planes exist, and plane's layer ID is
* DE_VIDEO1, it can use all the memory from first bank if
* secondary rotation memory bank is available, otherwise it can
* use up to half the bank's memory.
* c. If other rotated planes exist, and plane's layer ID is not
* DE_VIDEO1, it can use half of the available memory
*
* Note: this algorithm assumes that the order in which the planes are
* checked always has DE_VIDEO1 plane first in the list if it is
* rotated. Because that is how we create the planes in the first
* place, under current DRM version things work, but if ever the order
* in which drm_atomic_crtc_state_for_each_plane() iterates over planes
* changes, we need to pre-sort the planes before validation.
*/
/* first count the number of rotated planes */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
if (pstate->rotation & MALIDP_ROTATED_MASK)
rotated_planes++;
}
rot_mem_free = hwdev->rotation_memory[0];
/*
* if we have more than 1 plane using rotation memory, use the second
* block of rotation memory as well
*/
if (rotated_planes > 1)
rot_mem_free += hwdev->rotation_memory[1];
/* now validate the rotation memory requirements */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
struct malidp_plane *mp = to_malidp_plane(plane);
struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
if (pstate->rotation & MALIDP_ROTATED_MASK) {
/* process current plane */
rotated_planes--;
if (!rotated_planes) {
/* no more rotated planes, we can use what's left */
rot_mem_usable = rot_mem_free;
} else {
if ((mp->layer->id != DE_VIDEO1) ||
(hwdev->rotation_memory[1] == 0))
rot_mem_usable = rot_mem_free / 2;
else
rot_mem_usable = hwdev->rotation_memory[0];
}
rot_mem_free -= rot_mem_usable;
if (ms->rotmem_size > rot_mem_usable)
return -EINVAL;
}
}
return 0;
}
static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
.mode_fixup = malidp_crtc_mode_fixup,
.enable = malidp_crtc_enable,
.disable = malidp_crtc_disable,
.atomic_check = malidp_crtc_atomic_check,
};
static const struct drm_crtc_funcs malidp_crtc_funcs = {
.destroy = drm_crtc_cleanup,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};
int malidp_crtc_init(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
struct drm_plane *primary = NULL, *plane;
int ret;
ret = malidp_de_planes_init(drm);
if (ret < 0) {
DRM_ERROR("Failed to initialise planes\n");
return ret;
}
drm_for_each_plane(plane, drm) {
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
primary = plane;
break;
}
}
if (!primary) {
DRM_ERROR("no primary plane found\n");
ret = -EINVAL;
goto crtc_cleanup_planes;
}
ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
&malidp_crtc_funcs, NULL);
if (!ret) {
drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
return 0;
}
crtc_cleanup_planes:
malidp_de_planes_destroy(drm);
return ret;
}

512
drivers/gpu/drm/arm/malidp_drv.c Normal file
View File

@ -0,0 +1,512 @@
/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP500/DP550/DP650 KMS/DRM driver
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/of_reserved_mem.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_of.h>
#include "malidp_drv.h"
#include "malidp_regs.h"
#include "malidp_hw.h"
#define MALIDP_CONF_VALID_TIMEOUT 250
/*
* set the "config valid" bit and wait until the hardware acts on it
*/
static int malidp_set_and_wait_config_valid(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
int ret;
hwdev->set_config_valid(hwdev);
/* don't wait for config_valid flag if we are in config mode */
if (hwdev->in_config_mode(hwdev))
return 0;
ret = wait_event_interruptible_timeout(malidp->wq,
atomic_read(&malidp->config_valid) == 1,
msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
return (ret > 0) ? 0 : -ETIMEDOUT;
}
static void malidp_output_poll_changed(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
drm_fbdev_cma_hotplug_event(malidp->fbdev);
}
static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
{
struct drm_pending_vblank_event *event;
struct drm_device *drm = state->dev;
struct malidp_drm *malidp = drm->dev_private;
int ret = malidp_set_and_wait_config_valid(drm);
if (ret)
DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
event = malidp->crtc.state->event;
if (event) {
malidp->crtc.state->event = NULL;
spin_lock_irq(&drm->event_lock);
if (drm_crtc_vblank_get(&malidp->crtc) == 0)
drm_crtc_arm_vblank_event(&malidp->crtc, event);
else
drm_crtc_send_vblank_event(&malidp->crtc, event);
spin_unlock_irq(&drm->event_lock);
}
drm_atomic_helper_commit_hw_done(state);
}
static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
{
struct drm_device *drm = state->dev;
drm_atomic_helper_commit_modeset_disables(drm, state);
drm_atomic_helper_commit_modeset_enables(drm, state);
drm_atomic_helper_commit_planes(drm, state, true);
malidp_atomic_commit_hw_done(state);
drm_atomic_helper_wait_for_vblanks(drm, state);
drm_atomic_helper_cleanup_planes(drm, state);
}
static struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
.atomic_commit_tail = malidp_atomic_commit_tail,
};
static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
.fb_create = drm_fb_cma_create,
.output_poll_changed = malidp_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
static int malidp_enable_vblank(struct drm_device *drm, unsigned int crtc)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
hwdev->map.de_irq_map.vsync_irq);
return 0;
}
static void malidp_disable_vblank(struct drm_device *drm, unsigned int pipe)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
hwdev->map.de_irq_map.vsync_irq);
}
static int malidp_init(struct drm_device *drm)
{
int ret;
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
drm_mode_config_init(drm);
drm->mode_config.min_width = hwdev->min_line_size;
drm->mode_config.min_height = hwdev->min_line_size;
drm->mode_config.max_width = hwdev->max_line_size;
drm->mode_config.max_height = hwdev->max_line_size;
drm->mode_config.funcs = &malidp_mode_config_funcs;
drm->mode_config.helper_private = &malidp_mode_config_helpers;
ret = malidp_crtc_init(drm);
if (ret) {
drm_mode_config_cleanup(drm);
return ret;
}
return 0;
}
static int malidp_irq_init(struct platform_device *pdev)
{
int irq_de, irq_se, ret = 0;
struct drm_device *drm = dev_get_drvdata(&pdev->dev);
/* fetch the interrupts from DT */
irq_de = platform_get_irq_byname(pdev, "DE");
if (irq_de < 0) {
DRM_ERROR("no 'DE' IRQ specified!\n");
return irq_de;
}
irq_se = platform_get_irq_byname(pdev, "SE");
if (irq_se < 0) {
DRM_ERROR("no 'SE' IRQ specified!\n");
return irq_se;
}
ret = malidp_de_irq_init(drm, irq_de);
if (ret)
return ret;
ret = malidp_se_irq_init(drm, irq_se);
if (ret) {
malidp_de_irq_fini(drm);
return ret;
}
return 0;
}
static void malidp_lastclose(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
drm_fbdev_cma_restore_mode(malidp->fbdev);
}
static const struct file_operations fops = {
.owner = THIS_MODULE,
.open = drm_open,
.release = drm_release,
.unlocked_ioctl = drm_ioctl,
#ifdef CONFIG_COMPAT
.compat_ioctl = drm_compat_ioctl,
#endif
.poll = drm_poll,
.read = drm_read,
.llseek = noop_llseek,
.mmap = drm_gem_cma_mmap,
};
static struct drm_driver malidp_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
DRIVER_PRIME,
.lastclose = malidp_lastclose,
.get_vblank_counter = drm_vblank_no_hw_counter,
.enable_vblank = malidp_enable_vblank,
.disable_vblank = malidp_disable_vblank,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = drm_gem_cma_dumb_create,
.dumb_map_offset = drm_gem_cma_dumb_map_offset,
.dumb_destroy = drm_gem_dumb_destroy,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = drm_gem_prime_export,
.gem_prime_import = drm_gem_prime_import,
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
.gem_prime_vmap = drm_gem_cma_prime_vmap,
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
.gem_prime_mmap = drm_gem_cma_prime_mmap,
.fops = &fops,
.name = "mali-dp",
.desc = "ARM Mali Display Processor driver",
.date = "20160106",
.major = 1,
.minor = 0,
};
static const struct of_device_id malidp_drm_of_match[] = {
{
.compatible = "arm,mali-dp500",
.data = &malidp_device[MALIDP_500]
},
{
.compatible = "arm,mali-dp550",
.data = &malidp_device[MALIDP_550]
},
{
.compatible = "arm,mali-dp650",
.data = &malidp_device[MALIDP_650]
},
{},
};
MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
#define MAX_OUTPUT_CHANNELS 3
static int malidp_bind(struct device *dev)
{
struct resource *res;
struct drm_device *drm;
struct malidp_drm *malidp;
struct malidp_hw_device *hwdev;
struct platform_device *pdev = to_platform_device(dev);
/* number of lines for the R, G and B output */
u8 output_width[MAX_OUTPUT_CHANNELS];
int ret = 0, i;
u32 version, out_depth = 0;
malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
if (!malidp)
return -ENOMEM;
hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
if (!hwdev)
return -ENOMEM;
/*
* copy the associated data from malidp_drm_of_match to avoid
* having to keep a reference to the OF node after binding
*/
memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
malidp->dev = hwdev;
INIT_LIST_HEAD(&malidp->event_list);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
hwdev->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(hwdev->regs)) {
DRM_ERROR("Failed to map control registers area\n");
return PTR_ERR(hwdev->regs);
}
hwdev->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(hwdev->pclk))
return PTR_ERR(hwdev->pclk);
hwdev->aclk = devm_clk_get(dev, "aclk");
if (IS_ERR(hwdev->aclk))
return PTR_ERR(hwdev->aclk);
hwdev->mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(hwdev->mclk))
return PTR_ERR(hwdev->mclk);
hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
if (IS_ERR(hwdev->pxlclk))
return PTR_ERR(hwdev->pxlclk);
/* Get the optional framebuffer memory resource */
ret = of_reserved_mem_device_init(dev);
if (ret && ret != -ENODEV)
return ret;
drm = drm_dev_alloc(&malidp_driver, dev);
if (!drm) {
ret = -ENOMEM;
goto alloc_fail;
}
/* Enable APB clock in order to get access to the registers */
clk_prepare_enable(hwdev->pclk);
/*
* Enable AXI clock and main clock so that prefetch can start once
* the registers are set
*/
clk_prepare_enable(hwdev->aclk);
clk_prepare_enable(hwdev->mclk);
ret = hwdev->query_hw(hwdev);
if (ret) {
DRM_ERROR("Invalid HW configuration\n");
goto query_hw_fail;
}
version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
(version >> 12) & 0xf, (version >> 8) & 0xf);
/* set the number of lines used for output of RGB data */
ret = of_property_read_u8_array(dev->of_node,
"arm,malidp-output-port-lines",
output_width, MAX_OUTPUT_CHANNELS);
if (ret)
goto query_hw_fail;
for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
out_depth = (out_depth << 8) | (output_width[i] & 0xf);
malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
drm->dev_private = malidp;
dev_set_drvdata(dev, drm);
atomic_set(&malidp->config_valid, 0);
init_waitqueue_head(&malidp->wq);
ret = malidp_init(drm);
if (ret < 0)
goto init_fail;
ret = drm_dev_register(drm, 0);
if (ret)
goto register_fail;
/* Set the CRTC's port so that the encoder component can find it */
malidp->crtc.port = of_graph_get_next_endpoint(dev->of_node, NULL);
ret = component_bind_all(dev, drm);
of_node_put(malidp->crtc.port);
if (ret) {
DRM_ERROR("Failed to bind all components\n");
goto bind_fail;
}
ret = malidp_irq_init(pdev);
if (ret < 0)
goto irq_init_fail;
ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
if (ret < 0) {
DRM_ERROR("failed to initialise vblank\n");
goto vblank_fail;
}
drm_mode_config_reset(drm);
malidp->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
drm->mode_config.num_connector);
if (IS_ERR(malidp->fbdev)) {
ret = PTR_ERR(malidp->fbdev);
malidp->fbdev = NULL;
goto fbdev_fail;
}
drm_kms_helper_poll_init(drm);
return 0;
fbdev_fail:
drm_vblank_cleanup(drm);
vblank_fail:
malidp_se_irq_fini(drm);
malidp_de_irq_fini(drm);
irq_init_fail:
component_unbind_all(dev, drm);
bind_fail:
drm_dev_unregister(drm);
register_fail:
malidp_de_planes_destroy(drm);
drm_mode_config_cleanup(drm);
init_fail:
drm->dev_private = NULL;
dev_set_drvdata(dev, NULL);
query_hw_fail:
clk_disable_unprepare(hwdev->mclk);
clk_disable_unprepare(hwdev->aclk);
clk_disable_unprepare(hwdev->pclk);
drm_dev_unref(drm);
alloc_fail:
of_reserved_mem_device_release(dev);
return ret;
}
static void malidp_unbind(struct device *dev)
{
struct drm_device *drm = dev_get_drvdata(dev);
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
if (malidp->fbdev) {
drm_fbdev_cma_fini(malidp->fbdev);
malidp->fbdev = NULL;
}
drm_kms_helper_poll_fini(drm);
malidp_se_irq_fini(drm);
malidp_de_irq_fini(drm);
drm_vblank_cleanup(drm);
component_unbind_all(dev, drm);
drm_dev_unregister(drm);
malidp_de_planes_destroy(drm);
drm_mode_config_cleanup(drm);
drm->dev_private = NULL;
dev_set_drvdata(dev, NULL);
clk_disable_unprepare(hwdev->mclk);
clk_disable_unprepare(hwdev->aclk);
clk_disable_unprepare(hwdev->pclk);
drm_dev_unref(drm);
of_reserved_mem_device_release(dev);
}
static const struct component_master_ops malidp_master_ops = {
.bind = malidp_bind,
.unbind = malidp_unbind,
};
static int malidp_compare_dev(struct device *dev, void *data)
{
struct device_node *np = data;
return dev->of_node == np;
}
static int malidp_platform_probe(struct platform_device *pdev)
{
struct device_node *port, *ep;
struct component_match *match = NULL;
if (!pdev->dev.of_node)
return -ENODEV;
/* there is only one output port inside each device, find it */
ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
if (!ep)
return -ENODEV;
if (!of_device_is_available(ep)) {
of_node_put(ep);
return -ENODEV;
}
/* add the remote encoder port as component */
port = of_graph_get_remote_port_parent(ep);
of_node_put(ep);
if (!port || !of_device_is_available(port)) {
of_node_put(port);
return -EAGAIN;
}
component_match_add(&pdev->dev, &match, malidp_compare_dev, port);
return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
match);
}
static int malidp_platform_remove(struct platform_device *pdev)
{
component_master_del(&pdev->dev, &malidp_master_ops);
return 0;
}
static struct platform_driver malidp_platform_driver = {
.probe = malidp_platform_probe,
.remove = malidp_platform_remove,
.driver = {
.name = "mali-dp",
.of_match_table = malidp_drm_of_match,
},
};
module_platform_driver(malidp_platform_driver);
MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
MODULE_DESCRIPTION("ARM Mali DP DRM driver");
MODULE_LICENSE("GPL v2");

54
drivers/gpu/drm/arm/malidp_drv.h Normal file
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/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP500/DP550/DP650 KMS/DRM driver structures
*/
#ifndef __MALIDP_DRV_H__
#define __MALIDP_DRV_H__
#include <linux/mutex.h>
#include <linux/wait.h>
#include "malidp_hw.h"
struct malidp_drm {
struct malidp_hw_device *dev;
struct drm_fbdev_cma *fbdev;
struct list_head event_list;
struct drm_crtc crtc;
wait_queue_head_t wq;
atomic_t config_valid;
};
#define crtc_to_malidp_device(x) container_of(x, struct malidp_drm, crtc)
struct malidp_plane {
struct drm_plane base;
struct malidp_hw_device *hwdev;
const struct malidp_layer *layer;
};
struct malidp_plane_state {
struct drm_plane_state base;
/* size of the required rotation memory if plane is rotated */
u32 rotmem_size;
};
#define to_malidp_plane(x) container_of(x, struct malidp_plane, base)
#define to_malidp_plane_state(x) container_of(x, struct malidp_plane_state, base)
int malidp_de_planes_init(struct drm_device *drm);
void malidp_de_planes_destroy(struct drm_device *drm);
int malidp_crtc_init(struct drm_device *drm);
/* often used combination of rotational bits */
#define MALIDP_ROTATED_MASK (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))
#endif /* __MALIDP_DRV_H__ */

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/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
* the difference between various versions of the hardware is being dealt with
* in an attempt to provide to the rest of the driver code a unified view
*/
#include <linux/types.h>
#include <linux/io.h>
#include <drm/drmP.h>
#include <video/videomode.h>
#include <video/display_timing.h>
#include "malidp_drv.h"
#include "malidp_hw.h"
static const struct malidp_input_format malidp500_de_formats[] = {
/* fourcc, layers supporting the format, internal id */
{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 },
{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 },
{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 },
{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 },
{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 4 },
{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 5 },
{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 },
{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 },
{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 },
{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 9 },
{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 },
{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 },
{ DRM_FORMAT_UYVY, DE_VIDEO1, 12 },
{ DRM_FORMAT_YUYV, DE_VIDEO1, 13 },
{ DRM_FORMAT_NV12, DE_VIDEO1, 14 },
{ DRM_FORMAT_YUV420, DE_VIDEO1, 15 },
};
#define MALIDP_ID(__group, __format) \
((((__group) & 0x7) << 3) | ((__format) & 0x7))
#define MALIDP_COMMON_FORMATS \
/* fourcc, layers supporting the format, internal id */ \
{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \
{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \
{ DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \
{ DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \
{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \
{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \
{ DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \
{ DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \
{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \
{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \
{ DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \
{ DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \
{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \
{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \
{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \
{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \
{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \
{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \
{ DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \
{ DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \
{ DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \
{ DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }
static const struct malidp_input_format malidp550_de_formats[] = {
MALIDP_COMMON_FORMATS,
};
static const struct malidp_layer malidp500_layers[] = {
{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE },
{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE },
{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE },
};
static const struct malidp_layer malidp550_layers[] = {
{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE },
{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE },
{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE },
{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE },
};
#define MALIDP_DE_DEFAULT_PREFETCH_START 5
static int malidp500_query_hw(struct malidp_hw_device *hwdev)
{
u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
/* bit 4 of the CONFIG_ID register holds the line size multiplier */
u8 ln_size_mult = conf & 0x10 ? 2 : 1;
hwdev->min_line_size = 2;
hwdev->max_line_size = SZ_2K * ln_size_mult;
hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
return 0;
}
static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
{
u32 status, count = 100;
malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
while (count) {
status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
break;
/*
* entering config mode can take as long as the rendering
* of a full frame, hence the long sleep here
*/
usleep_range(1000, 10000);
count--;
}
WARN(count == 0, "timeout while entering config mode");
}
static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
{
u32 status, count = 100;
malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
while (count) {
status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
break;
usleep_range(100, 1000);
count--;
}
WARN(count == 0, "timeout while leaving config mode");
}
static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
{
u32 status;
status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
return true;
return false;
}
static void malidp500_set_config_valid(struct malidp_hw_device *hwdev)
{
malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
}
static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
{
u32 val = 0;
malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= MALIDP500_HSYNCPOL;
if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= MALIDP500_VSYNCPOL;
val |= MALIDP_DE_DEFAULT_PREFETCH_START;
malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
/*
* Mali-DP500 encodes the background color like this:
* - red @ MALIDP500_BGND_COLOR[12:0]
* - green @ MALIDP500_BGND_COLOR[27:16]
* - blue @ (MALIDP500_BGND_COLOR + 4)[12:0]
*/
val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
(MALIDP_BGND_COLOR_R & 0xfff);
malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
MALIDP_DE_H_BACKPORCH(mode->hback_porch);
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
MALIDP_DE_V_BACKPORCH(mode->vback_porch);
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
else
malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
}
static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
{
unsigned int depth;
int bpp;
/* RGB888 or BGR888 can't be rotated */
if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
return -EINVAL;
/*
* Each layer needs enough rotation memory to fit 8 lines
* worth of pixel data. Required size is then:
* size = rotated_width * (bpp / 8) * 8;
*/
drm_fb_get_bpp_depth(fmt, &depth, &bpp);
return w * bpp;
}
static int malidp550_query_hw(struct malidp_hw_device *hwdev)
{
u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
u8 ln_size = (conf >> 4) & 0x3, rsize;
hwdev->min_line_size = 2;
switch (ln_size) {
case 0:
hwdev->max_line_size = SZ_2K;
/* two banks of 64KB for rotation memory */
rsize = 64;
break;
case 1:
hwdev->max_line_size = SZ_4K;
/* two banks of 128KB for rotation memory */
rsize = 128;
break;
case 2:
hwdev->max_line_size = 1280;
/* two banks of 40KB for rotation memory */
rsize = 40;
break;
case 3:
/* reserved value */
hwdev->max_line_size = 0;
return -EINVAL;
}
hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
return 0;
}
static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
{
u32 status, count = 100;
malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
while (count) {
status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
break;
/*
* entering config mode can take as long as the rendering
* of a full frame, hence the long sleep here
*/
usleep_range(1000, 10000);
count--;
}
WARN(count == 0, "timeout while entering config mode");
}
static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
{
u32 status, count = 100;
malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
while (count) {
status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
break;
usleep_range(100, 1000);
count--;
}
WARN(count == 0, "timeout while leaving config mode");
}
static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
{
u32 status;
status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
return true;
return false;
}
static void malidp550_set_config_valid(struct malidp_hw_device *hwdev)
{
malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
}
static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
{
u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
/*
* Mali-DP550 and Mali-DP650 encode the background color like this:
* - red @ MALIDP550_DE_BGND_COLOR[23:16]
* - green @ MALIDP550_DE_BGND_COLOR[15:8]
* - blue @ MALIDP550_DE_BGND_COLOR[7:0]
*
* We need to truncate the least significant 4 bits from the default
* MALIDP_BGND_COLOR_x values
*/
val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
(((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
((MALIDP_BGND_COLOR_B >> 4) & 0xff);
malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
MALIDP_DE_H_BACKPORCH(mode->hback_porch);
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
MALIDP_DE_V_BACKPORCH(mode->vback_porch);
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= MALIDP550_HSYNCPOL;
if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= MALIDP550_VSYNCPOL;
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
else
malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
}
static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
{
u32 bytes_per_col;
/* raw RGB888 or BGR888 can't be rotated */
if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
return -EINVAL;
switch (fmt) {
/* 8 lines at 4 bytes per pixel */
case DRM_FORMAT_ARGB2101010:
case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_RGBA1010102:
case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_RGBA8888:
case DRM_FORMAT_BGRA8888:
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_RGBX8888:
case DRM_FORMAT_BGRX8888:
case DRM_FORMAT_RGB888:
case DRM_FORMAT_BGR888:
/* 16 lines at 2 bytes per pixel */
case DRM_FORMAT_RGBA5551:
case DRM_FORMAT_ABGR1555:
case DRM_FORMAT_RGB565:
case DRM_FORMAT_BGR565:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YUYV:
bytes_per_col = 32;
break;
/* 16 lines at 1.5 bytes per pixel */
case DRM_FORMAT_NV12:
case DRM_FORMAT_YUV420:
bytes_per_col = 24;
break;
default:
return -EINVAL;
}
return w * bytes_per_col;
}
static int malidp650_query_hw(struct malidp_hw_device *hwdev)
{
u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
u8 ln_size = (conf >> 4) & 0x3, rsize;
hwdev->min_line_size = 4;
switch (ln_size) {
case 0:
case 2:
/* reserved values */
hwdev->max_line_size = 0;
return -EINVAL;
case 1:
hwdev->max_line_size = SZ_4K;
/* two banks of 128KB for rotation memory */
rsize = 128;
break;
case 3:
hwdev->max_line_size = 2560;
/* two banks of 80KB for rotation memory */
rsize = 80;
}
hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
return 0;
}
const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
[MALIDP_500] = {
.map = {
.se_base = MALIDP500_SE_BASE,
.dc_base = MALIDP500_DC_BASE,
.out_depth_base = MALIDP500_OUTPUT_DEPTH,
.features = 0, /* no CLEARIRQ register */
.n_layers = ARRAY_SIZE(malidp500_layers),
.layers = malidp500_layers,
.de_irq_map = {
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
MALIDP500_DE_IRQ_AXI_ERR |
MALIDP500_DE_IRQ_VSYNC |
MALIDP500_DE_IRQ_GLOBAL,
.vsync_irq = MALIDP500_DE_IRQ_VSYNC,
},
.se_irq_map = {
.irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
.vsync_irq = 0,
},
.dc_irq_map = {
.irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
},
.input_formats = malidp500_de_formats,
.n_input_formats = ARRAY_SIZE(malidp500_de_formats),
},
.query_hw = malidp500_query_hw,
.enter_config_mode = malidp500_enter_config_mode,
.leave_config_mode = malidp500_leave_config_mode,
.in_config_mode = malidp500_in_config_mode,
.set_config_valid = malidp500_set_config_valid,
.modeset = malidp500_modeset,
.rotmem_required = malidp500_rotmem_required,
},
[MALIDP_550] = {
.map = {
.se_base = MALIDP550_SE_BASE,
.dc_base = MALIDP550_DC_BASE,
.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
.features = MALIDP_REGMAP_HAS_CLEARIRQ,
.n_layers = ARRAY_SIZE(malidp550_layers),
.layers = malidp550_layers,
.de_irq_map = {
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
MALIDP550_DE_IRQ_VSYNC,
.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
},
.se_irq_map = {
.irq_mask = MALIDP550_SE_IRQ_EOW |
MALIDP550_SE_IRQ_AXI_ERR,
},
.dc_irq_map = {
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
},
.input_formats = malidp550_de_formats,
.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
},
.query_hw = malidp550_query_hw,
.enter_config_mode = malidp550_enter_config_mode,
.leave_config_mode = malidp550_leave_config_mode,
.in_config_mode = malidp550_in_config_mode,
.set_config_valid = malidp550_set_config_valid,
.modeset = malidp550_modeset,
.rotmem_required = malidp550_rotmem_required,
},
[MALIDP_650] = {
.map = {
.se_base = MALIDP550_SE_BASE,
.dc_base = MALIDP550_DC_BASE,
.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
.features = MALIDP_REGMAP_HAS_CLEARIRQ,
.n_layers = ARRAY_SIZE(malidp550_layers),
.layers = malidp550_layers,
.de_irq_map = {
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
MALIDP650_DE_IRQ_DRIFT |
MALIDP550_DE_IRQ_VSYNC,
.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
},
.se_irq_map = {
.irq_mask = MALIDP550_SE_IRQ_EOW |
MALIDP550_SE_IRQ_AXI_ERR,
},
.dc_irq_map = {
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
},
.input_formats = malidp550_de_formats,
.n_input_formats = ARRAY_SIZE(malidp550_de_formats),
},
.query_hw = malidp650_query_hw,
.enter_config_mode = malidp550_enter_config_mode,
.leave_config_mode = malidp550_leave_config_mode,
.in_config_mode = malidp550_in_config_mode,
.set_config_valid = malidp550_set_config_valid,
.modeset = malidp550_modeset,
.rotmem_required = malidp550_rotmem_required,
},
};
u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
u8 layer_id, u32 format)
{
unsigned int i;
for (i = 0; i < map->n_input_formats; i++) {
if (((map->input_formats[i].layer & layer_id) == layer_id) &&
(map->input_formats[i].format == format))
return map->input_formats[i].id;
}
return MALIDP_INVALID_FORMAT_ID;
}
static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
{
u32 base = malidp_get_block_base(hwdev, block);
if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
else
malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
}
static irqreturn_t malidp_de_irq(int irq, void *arg)
{
struct drm_device *drm = arg;
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev;
const struct malidp_irq_map *de;
u32 status, mask, dc_status;
irqreturn_t ret = IRQ_NONE;
if (!drm->dev_private)
return IRQ_HANDLED;
hwdev = malidp->dev;
de = &hwdev->map.de_irq_map;
/* first handle the config valid IRQ */
dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
/* we have a page flip event */
atomic_set(&malidp->config_valid, 1);
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
ret = IRQ_WAKE_THREAD;
}
status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
if (!(status & de->irq_mask))
return ret;
mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
status &= mask;
if (status & de->vsync_irq)
drm_crtc_handle_vblank(&malidp->crtc);
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
}
static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
{
struct drm_device *drm = arg;
struct malidp_drm *malidp = drm->dev_private;
wake_up(&malidp->wq);
return IRQ_HANDLED;
}
int malidp_de_irq_init(struct drm_device *drm, int irq)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
int ret;
/* ensure interrupts are disabled */
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
malidp_de_irq_thread_handler,
IRQF_SHARED, "malidp-de", drm);
if (ret < 0) {
DRM_ERROR("failed to install DE IRQ handler\n");
return ret;
}
/* first enable the DC block IRQs */
malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
hwdev->map.dc_irq_map.irq_mask);
/* now enable the DE block IRQs */
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
hwdev->map.de_irq_map.irq_mask);
return 0;
}
void malidp_de_irq_fini(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
hwdev->map.de_irq_map.irq_mask);
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
hwdev->map.dc_irq_map.irq_mask);
}
static irqreturn_t malidp_se_irq(int irq, void *arg)
{
struct drm_device *drm = arg;
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
u32 status, mask;
status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
if (!(status & hwdev->map.se_irq_map.irq_mask))
return IRQ_NONE;
mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ);
status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
status &= mask;
/* ToDo: status decoding and firing up of VSYNC and page flip events */
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
return IRQ_HANDLED;
}
static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
{
return IRQ_HANDLED;
}
int malidp_se_irq_init(struct drm_device *drm, int irq)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
int ret;
/* ensure interrupts are disabled */
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
malidp_se_irq_thread_handler,
IRQF_SHARED, "malidp-se", drm);
if (ret < 0) {
DRM_ERROR("failed to install SE IRQ handler\n");
return ret;
}
malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
hwdev->map.se_irq_map.irq_mask);
return 0;
}
void malidp_se_irq_fini(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
struct malidp_hw_device *hwdev = malidp->dev;
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
hwdev->map.se_irq_map.irq_mask);
}

241
drivers/gpu/drm/arm/malidp_hw.h Normal file
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@ -0,0 +1,241 @@
/*
*
* (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP hardware manipulation routines.
*/
#ifndef __MALIDP_HW_H__
#define __MALIDP_HW_H__
#include <linux/bitops.h>
#include "malidp_regs.h"
struct videomode;
struct clk;
/* Mali DP IP blocks */
enum {
MALIDP_DE_BLOCK = 0,
MALIDP_SE_BLOCK,
MALIDP_DC_BLOCK
};
/* Mali DP layer IDs */
enum {
DE_VIDEO1 = BIT(0),
DE_GRAPHICS1 = BIT(1),
DE_GRAPHICS2 = BIT(2), /* used only in DP500 */
DE_VIDEO2 = BIT(3),
DE_SMART = BIT(4),
};
struct malidp_input_format {
u32 format; /* DRM fourcc */
u8 layer; /* bitmask of layers supporting it */
u8 id; /* used internally */
};
#define MALIDP_INVALID_FORMAT_ID 0xff
/*
* hide the differences between register maps
* by using a common structure to hold the
* base register offsets
*/
struct malidp_irq_map {
u32 irq_mask; /* mask of IRQs that can be enabled in the block */
u32 vsync_irq; /* IRQ bit used for signaling during VSYNC */
};
struct malidp_layer {
u16 id; /* layer ID */
u16 base; /* address offset for the register bank */
u16 ptr; /* address offset for the pointer register */
};
/* regmap features */
#define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0)
struct malidp_hw_regmap {
/* address offset of the DE register bank */
/* is always 0x0000 */
/* address offset of the SE registers bank */
const u16 se_base;
/* address offset of the DC registers bank */
const u16 dc_base;
/* address offset for the output depth register */
const u16 out_depth_base;
/* bitmap with register map features */
const u8 features;
/* list of supported layers */
const u8 n_layers;
const struct malidp_layer *layers;
const struct malidp_irq_map de_irq_map;
const struct malidp_irq_map se_irq_map;
const struct malidp_irq_map dc_irq_map;
/* list of supported input formats for each layer */
const struct malidp_input_format *input_formats;
const u8 n_input_formats;
};
struct malidp_hw_device {
const struct malidp_hw_regmap map;
void __iomem *regs;
/* APB clock */
struct clk *pclk;
/* AXI clock */
struct clk *aclk;
/* main clock for display core */
struct clk *mclk;
/* pixel clock for display core */
struct clk *pxlclk;
/*
* Validate the driver instance against the hardware bits
*/
int (*query_hw)(struct malidp_hw_device *hwdev);
/*
* Set the hardware into config mode, ready to accept mode changes
*/
void (*enter_config_mode)(struct malidp_hw_device *hwdev);
/*
* Tell hardware to exit configuration mode
*/
void (*leave_config_mode)(struct malidp_hw_device *hwdev);
/*
* Query if hardware is in configuration mode
*/
bool (*in_config_mode)(struct malidp_hw_device *hwdev);
/*
* Set configuration valid flag for hardware parameters that can
* be changed outside the configuration mode. Hardware will use
* the new settings when config valid is set after the end of the
* current buffer scanout
*/
void (*set_config_valid)(struct malidp_hw_device *hwdev);
/*
* Set a new mode in hardware. Requires the hardware to be in
* configuration mode before this function is called.
*/
void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m);
/*
* Calculate the required rotation memory given the active area
* and the buffer format.
*/
int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt);
u8 features;
u8 min_line_size;
u16 max_line_size;
/* size of memory used for rotating layers, up to two banks available */
u32 rotation_memory[2];
};
/* Supported variants of the hardware */
enum {
MALIDP_500 = 0,
MALIDP_550,
MALIDP_650,
/* keep the next entry last */
MALIDP_MAX_DEVICES
};
extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES];
static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
{
return readl(hwdev->regs + reg);
}
static inline void malidp_hw_write(struct malidp_hw_device *hwdev,
u32 value, u32 reg)
{
writel(value, hwdev->regs + reg);
}
static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev,
u32 mask, u32 reg)
{
u32 data = malidp_hw_read(hwdev, reg);
data |= mask;
malidp_hw_write(hwdev, data, reg);
}
static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev,
u32 mask, u32 reg)
{
u32 data = malidp_hw_read(hwdev, reg);
data &= ~mask;
malidp_hw_write(hwdev, data, reg);
}
static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev,
u8 block)
{
switch (block) {
case MALIDP_SE_BLOCK:
return hwdev->map.se_base;
case MALIDP_DC_BLOCK:
return hwdev->map.dc_base;
}
return 0;
}
static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev,
u8 block, u32 irq)
{
u32 base = malidp_get_block_base(hwdev, block);
malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
}
static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev,
u8 block, u32 irq)
{
u32 base = malidp_get_block_base(hwdev, block);
malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ);
}
int malidp_de_irq_init(struct drm_device *drm, int irq);
void malidp_de_irq_fini(struct drm_device *drm);
int malidp_se_irq_init(struct drm_device *drm, int irq);
void malidp_se_irq_fini(struct drm_device *drm);
u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
u8 layer_id, u32 format);
/*
* background color components are defined as 12bits values,
* they will be shifted right when stored on hardware that
* supports only 8bits per channel
*/
#define MALIDP_BGND_COLOR_R 0x000
#define MALIDP_BGND_COLOR_G 0x000
#define MALIDP_BGND_COLOR_B 0x000
#endif /* __MALIDP_HW_H__ */

298
drivers/gpu/drm/arm/malidp_planes.c Normal file
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@ -0,0 +1,298 @@
/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP plane manipulation routines.
*/
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_plane_helper.h>
#include "malidp_hw.h"
#include "malidp_drv.h"
/* Layer specific register offsets */
#define MALIDP_LAYER_FORMAT 0x000
#define MALIDP_LAYER_CONTROL 0x004
#define LAYER_ENABLE (1 << 0)
#define LAYER_ROT_OFFSET 8
#define LAYER_H_FLIP (1 << 10)
#define LAYER_V_FLIP (1 << 11)
#define LAYER_ROT_MASK (0xf << 8)
#define MALIDP_LAYER_SIZE 0x00c
#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
#define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
#define MALIDP_LAYER_COMP_SIZE 0x010
#define MALIDP_LAYER_OFFSET 0x014
#define MALIDP_LAYER_STRIDE 0x018
static void malidp_de_plane_destroy(struct drm_plane *plane)
{
struct malidp_plane *mp = to_malidp_plane(plane);
if (mp->base.fb)
drm_framebuffer_unreference(mp->base.fb);
drm_plane_helper_disable(plane);
drm_plane_cleanup(plane);
devm_kfree(plane->dev->dev, mp);
}
struct drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
{
struct malidp_plane_state *state, *m_state;
if (!plane->state)
return NULL;
state = kmalloc(sizeof(*state), GFP_KERNEL);
if (state) {
m_state = to_malidp_plane_state(plane->state);
__drm_atomic_helper_plane_duplicate_state(plane, &state->base);
state->rotmem_size = m_state->rotmem_size;
}
return &state->base;
}
void malidp_destroy_plane_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct malidp_plane_state *m_state = to_malidp_plane_state(state);
__drm_atomic_helper_plane_destroy_state(state);
kfree(m_state);
}
static const struct drm_plane_funcs malidp_de_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = malidp_de_plane_destroy,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = malidp_duplicate_plane_state,
.atomic_destroy_state = malidp_destroy_plane_state,
};
static int malidp_de_plane_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct malidp_plane *mp = to_malidp_plane(plane);
struct malidp_plane_state *ms = to_malidp_plane_state(state);
u8 format_id;
u32 src_w, src_h;
if (!state->crtc || !state->fb)
return 0;
format_id = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id,
state->fb->pixel_format);
if (format_id == MALIDP_INVALID_FORMAT_ID)
return -EINVAL;
src_w = state->src_w >> 16;
src_h = state->src_h >> 16;
if ((state->crtc_w > mp->hwdev->max_line_size) ||
(state->crtc_h > mp->hwdev->max_line_size) ||
(state->crtc_w < mp->hwdev->min_line_size) ||
(state->crtc_h < mp->hwdev->min_line_size) ||
(state->crtc_w != src_w) || (state->crtc_h != src_h))
return -EINVAL;
/* packed RGB888 / BGR888 can't be rotated or flipped */
if (state->rotation != BIT(DRM_ROTATE_0) &&
(state->fb->pixel_format == DRM_FORMAT_RGB888 ||
state->fb->pixel_format == DRM_FORMAT_BGR888))
return -EINVAL;
ms->rotmem_size = 0;
if (state->rotation & MALIDP_ROTATED_MASK) {
int val;
val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h,
state->crtc_w,
state->fb->pixel_format);
if (val < 0)
return val;
ms->rotmem_size = val;
}
return 0;
}
static void malidp_de_plane_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct drm_gem_cma_object *obj;
struct malidp_plane *mp;
const struct malidp_hw_regmap *map;
u8 format_id;
u16 ptr;
u32 format, src_w, src_h, dest_w, dest_h, val = 0;
int num_planes, i;
mp = to_malidp_plane(plane);
map = &mp->hwdev->map;
format = plane->state->fb->pixel_format;
format_id = malidp_hw_get_format_id(map, mp->layer->id, format);
num_planes = drm_format_num_planes(format);
/* convert src values from Q16 fixed point to integer */
src_w = plane->state->src_w >> 16;
src_h = plane->state->src_h >> 16;
if (plane->state->rotation & MALIDP_ROTATED_MASK) {
dest_w = plane->state->crtc_h;
dest_h = plane->state->crtc_w;
} else {
dest_w = plane->state->crtc_w;
dest_h = plane->state->crtc_h;
}
malidp_hw_write(mp->hwdev, format_id, mp->layer->base);
for (i = 0; i < num_planes; i++) {
/* calculate the offset for the layer's plane registers */
ptr = mp->layer->ptr + (i << 4);
obj = drm_fb_cma_get_gem_obj(plane->state->fb, i);
malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr);
malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4);
malidp_hw_write(mp->hwdev, plane->state->fb->pitches[i],
mp->layer->base + MALIDP_LAYER_STRIDE);
}
malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
mp->layer->base + MALIDP_LAYER_SIZE);
malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
mp->layer->base + MALIDP_LAYER_COMP_SIZE);
malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
LAYER_V_VAL(plane->state->crtc_y),
mp->layer->base + MALIDP_LAYER_OFFSET);
/* first clear the rotation bits in the register */
malidp_hw_clearbits(mp->hwdev, LAYER_ROT_MASK,
mp->layer->base + MALIDP_LAYER_CONTROL);
/* setup the rotation and axis flip bits */
if (plane->state->rotation & DRM_ROTATE_MASK)
val = ilog2(plane->state->rotation & DRM_ROTATE_MASK) << LAYER_ROT_OFFSET;
if (plane->state->rotation & BIT(DRM_REFLECT_X))
val |= LAYER_V_FLIP;
if (plane->state->rotation & BIT(DRM_REFLECT_Y))
val |= LAYER_H_FLIP;
/* set the 'enable layer' bit */
val |= LAYER_ENABLE;
malidp_hw_setbits(mp->hwdev, val,
mp->layer->base + MALIDP_LAYER_CONTROL);
}
static void malidp_de_plane_disable(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct malidp_plane *mp = to_malidp_plane(plane);
malidp_hw_clearbits(mp->hwdev, LAYER_ENABLE,
mp->layer->base + MALIDP_LAYER_CONTROL);
}
static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
.atomic_check = malidp_de_plane_check,
.atomic_update = malidp_de_plane_update,
.atomic_disable = malidp_de_plane_disable,
};
int malidp_de_planes_init(struct drm_device *drm)
{
struct malidp_drm *malidp = drm->dev_private;
const struct malidp_hw_regmap *map = &malidp->dev->map;
struct malidp_plane *plane = NULL;
enum drm_plane_type plane_type;
unsigned long crtcs = 1 << drm->mode_config.num_crtc;
u32 *formats;
int ret, i, j, n;
formats = kcalloc(map->n_input_formats, sizeof(*formats), GFP_KERNEL);
if (!formats) {
ret = -ENOMEM;
goto cleanup;
}
for (i = 0; i < map->n_layers; i++) {
u8 id = map->layers[i].id;
plane = kzalloc(sizeof(*plane), GFP_KERNEL);
if (!plane) {
ret = -ENOMEM;
goto cleanup;
}
/* build the list of DRM supported formats based on the map */
for (n = 0, j = 0; j < map->n_input_formats; j++) {
if ((map->input_formats[j].layer & id) == id)
formats[n++] = map->input_formats[j].format;
}
plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
DRM_PLANE_TYPE_OVERLAY;
ret = drm_universal_plane_init(drm, &plane->base, crtcs,
&malidp_de_plane_funcs, formats,
n, plane_type, NULL);
if (ret < 0)
goto cleanup;
if (!drm->mode_config.rotation_property) {
unsigned long flags = BIT(DRM_ROTATE_0) |
BIT(DRM_ROTATE_90) |
BIT(DRM_ROTATE_180) |
BIT(DRM_ROTATE_270) |
BIT(DRM_REFLECT_X) |
BIT(DRM_REFLECT_Y);
drm->mode_config.rotation_property =
drm_mode_create_rotation_property(drm, flags);
}
/* SMART layer can't be rotated */
if (drm->mode_config.rotation_property && (id != DE_SMART))
drm_object_attach_property(&plane->base.base,
drm->mode_config.rotation_property,
BIT(DRM_ROTATE_0));
drm_plane_helper_add(&plane->base,
&malidp_de_plane_helper_funcs);
plane->hwdev = malidp->dev;
plane->layer = &map->layers[i];
}
kfree(formats);
return 0;
cleanup:
malidp_de_planes_destroy(drm);
kfree(formats);
return ret;
}
void malidp_de_planes_destroy(struct drm_device *drm)
{
struct drm_plane *p, *pt;
list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
drm_plane_cleanup(p);
kfree(p);
}
}

172
drivers/gpu/drm/arm/malidp_regs.h Normal file
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@ -0,0 +1,172 @@
/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Liviu Dudau <Liviu.Dudau@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*
* ARM Mali DP500/DP550/DP650 registers definition.
*/
#ifndef __MALIDP_REGS_H__
#define __MALIDP_REGS_H__
/*
* abbreviations used:
* - DC - display core (general settings)
* - DE - display engine
* - SE - scaling engine
*/
/* interrupt bit masks */
#define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
#define MALIDP500_DE_IRQ_AXI_ERR (1 << 4)
#define MALIDP500_DE_IRQ_VSYNC (1 << 5)
#define MALIDP500_DE_IRQ_PROG_LINE (1 << 6)
#define MALIDP500_DE_IRQ_SATURATION (1 << 7)
#define MALIDP500_DE_IRQ_CONF_VALID (1 << 8)
#define MALIDP500_DE_IRQ_CONF_MODE (1 << 11)
#define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17)
#define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18)
#define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19)
#define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24)
#define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28)
#define MALIDP500_DE_IRQ_GLOBAL (1 << 31)
#define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
#define MALIDP500_SE_IRQ_CONF_VALID (1 << 4)
#define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5)
#define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8)
#define MALIDP500_SE_IRQ_OVERRUN (1 << 9)
#define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12)
#define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13)
#define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17)
#define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18)
#define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28)
#define MALIDP500_SE_IRQ_GLOBAL (1 << 31)
#define MALIDP550_DE_IRQ_SATURATION (1 << 8)
#define MALIDP550_DE_IRQ_VSYNC (1 << 12)
#define MALIDP550_DE_IRQ_PROG_LINE (1 << 13)
#define MALIDP550_DE_IRQ_AXI_ERR (1 << 16)
#define MALIDP550_SE_IRQ_EOW (1 << 0)
#define MALIDP550_SE_IRQ_AXI_ERR (1 << 16)
#define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
#define MALIDP550_DC_IRQ_CONF_MODE (1 << 4)
#define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16)
#define MALIDP550_DC_IRQ_DE (1 << 20)
#define MALIDP550_DC_IRQ_SE (1 << 24)
#define MALIDP650_DE_IRQ_DRIFT (1 << 4)
/* bit masks that are common between products */
#define MALIDP_CFG_VALID (1 << 0)
#define MALIDP_DISP_FUNC_ILACED (1 << 8)
/* register offsets for IRQ management */
#define MALIDP_REG_STATUS 0x00000
#define MALIDP_REG_SETIRQ 0x00004
#define MALIDP_REG_MASKIRQ 0x00008
#define MALIDP_REG_CLEARIRQ 0x0000c
/* register offsets */
#define MALIDP_DE_CORE_ID 0x00018
#define MALIDP_DE_DISPLAY_FUNC 0x00020
/* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
#define MALIDP_DE_H_TIMINGS 0x0
#define MALIDP_DE_V_TIMINGS 0x4
#define MALIDP_DE_SYNC_WIDTH 0x8
#define MALIDP_DE_HV_ACTIVE 0xc
/* macros to set values into registers */
#define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0)
#define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16)
#define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0)
#define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0)
#define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16)
#define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0)
#define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16)
#define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0)
#define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16)
/* register offsets and bits specific to DP500 */
#define MALIDP500_DC_BASE 0x00000
#define MALIDP500_DC_CONTROL 0x0000c
#define MALIDP500_DC_CONFIG_REQ (1 << 17)
#define MALIDP500_HSYNCPOL (1 << 20)
#define MALIDP500_VSYNCPOL (1 << 21)
#define MALIDP500_DC_CLEAR_MASK 0x300fff
#define MALIDP500_DE_LINE_COUNTER 0x00010
#define MALIDP500_DE_AXI_CONTROL 0x00014
#define MALIDP500_DE_SECURE_CTRL 0x0001c
#define MALIDP500_DE_CHROMA_KEY 0x00024
#define MALIDP500_TIMINGS_BASE 0x00028
#define MALIDP500_CONFIG_3D 0x00038
#define MALIDP500_BGND_COLOR 0x0003c
#define MALIDP500_OUTPUT_DEPTH 0x00044
#define MALIDP500_YUV_RGB_COEF 0x00048
#define MALIDP500_COLOR_ADJ_COEF 0x00078
#define MALIDP500_COEF_TABLE_ADDR 0x000a8
#define MALIDP500_COEF_TABLE_DATA 0x000ac
#define MALIDP500_DE_LV_BASE 0x00100
#define MALIDP500_DE_LV_PTR_BASE 0x00124
#define MALIDP500_DE_LG1_BASE 0x00200
#define MALIDP500_DE_LG1_PTR_BASE 0x0021c
#define MALIDP500_DE_LG2_BASE 0x00300
#define MALIDP500_DE_LG2_PTR_BASE 0x0031c
#define MALIDP500_SE_BASE 0x00c00
#define MALIDP500_SE_PTR_BASE 0x00e0c
#define MALIDP500_DC_IRQ_BASE 0x00f00
#define MALIDP500_CONFIG_VALID 0x00f00
#define MALIDP500_CONFIG_ID 0x00fd4
/* register offsets and bits specific to DP550/DP650 */
#define MALIDP550_DE_CONTROL 0x00010
#define MALIDP550_DE_LINE_COUNTER 0x00014
#define MALIDP550_DE_AXI_CONTROL 0x00018
#define MALIDP550_DE_QOS 0x0001c
#define MALIDP550_TIMINGS_BASE 0x00030
#define MALIDP550_HSYNCPOL (1 << 12)
#define MALIDP550_VSYNCPOL (1 << 28)
#define MALIDP550_DE_DISP_SIDEBAND 0x00040
#define MALIDP550_DE_BGND_COLOR 0x00044
#define MALIDP550_DE_OUTPUT_DEPTH 0x0004c
#define MALIDP550_DE_COLOR_COEF 0x00050
#define MALIDP550_DE_COEF_TABLE_ADDR 0x00080
#define MALIDP550_DE_COEF_TABLE_DATA 0x00084
#define MALIDP550_DE_LV1_BASE 0x00100
#define MALIDP550_DE_LV1_PTR_BASE 0x00124
#define MALIDP550_DE_LV2_BASE 0x00200
#define MALIDP550_DE_LV2_PTR_BASE 0x00224
#define MALIDP550_DE_LG_BASE 0x00300
#define MALIDP550_DE_LG_PTR_BASE 0x0031c
#define MALIDP550_DE_LS_BASE 0x00400
#define MALIDP550_DE_LS_PTR_BASE 0x0042c
#define MALIDP550_DE_PERF_BASE 0x00500
#define MALIDP550_SE_BASE 0x08000
#define MALIDP550_DC_BASE 0x0c000
#define MALIDP550_DC_CONTROL 0x0c010
#define MALIDP550_DC_CONFIG_REQ (1 << 16)
#define MALIDP550_CONFIG_VALID 0x0c014
#define MALIDP550_CONFIG_ID 0x0ffd4
/*
* Starting with DP550 the register map blocks has been standardised to the
* following layout:
*
* Offset Block registers
* 0x00000 Display Engine
* 0x08000 Scaling Engine
* 0x0c000 Display Core
* 0x10000 Secure control
*
* The old DP500 IP mixes some DC with the DE registers, hence the need
* for a mapping structure.
*/
#endif /* __MALIDP_REGS_H__ */

1
drivers/gpu/drm/armada/armada_drv.c
View File

@ -189,7 +189,6 @@ static struct drm_driver armada_drm_driver = {
.load = armada_drm_load,
.lastclose = armada_drm_lastclose,
.unload = armada_drm_unload,
.set_busid = drm_platform_set_busid,
.get_vblank_counter = drm_vblank_no_hw_counter,
.enable_vblank = armada_drm_enable_vblank,
.disable_vblank = armada_drm_disable_vblank,

1
drivers/gpu/drm/armada/armada_overlay.c
View File

@ -121,6 +121,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
int ret;
ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
BIT(DRM_ROTATE_0),
0, INT_MAX, true, false, &visible);
if (ret)
return ret;

15
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
View File

@ -691,13 +691,6 @@ static void atmel_hlcdc_dc_unload(struct drm_device *dev)
destroy_workqueue(dc->wq);
}
static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
{
mutex_lock(&dev->mode_config.mutex);
drm_connector_unregister_all(dev);
mutex_unlock(&dev->mode_config.mutex);
}
static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
{
struct atmel_hlcdc_dc *dc = dev->dev_private;
@ -815,15 +808,8 @@ static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
if (ret)
goto err_unload;
ret = drm_connector_register_all(ddev);
if (ret)
goto err_unregister;
return 0;
err_unregister:
drm_dev_unregister(ddev);
err_unload:
atmel_hlcdc_dc_unload(ddev);
@ -837,7 +823,6 @@ static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
{
struct drm_device *ddev = platform_get_drvdata(pdev);
atmel_hlcdc_dc_connector_unplug_all(ddev);
drm_dev_unregister(ddev);
atmel_hlcdc_dc_unload(ddev);
drm_dev_unref(ddev);

8
drivers/gpu/drm/bridge/Kconfig
View File

@ -50,6 +50,14 @@ config DRM_PARADE_PS8622
---help---
Parade eDP-LVDS bridge chip driver.
config DRM_SII902X
tristate "Silicon Image sii902x RGB/HDMI bridge"
depends on OF
select DRM_KMS_HELPER
select REGMAP_I2C
---help---
Silicon Image sii902x bridge chip driver.
source "drivers/gpu/drm/bridge/analogix/Kconfig"
endmenu

1
drivers/gpu/drm/bridge/Makefile
View File

@ -5,4 +5,5 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/

467
drivers/gpu/drm/bridge/sii902x.c Normal file
View File

@ -0,0 +1,467 @@
/*
* Copyright (C) 2016 Atmel
* Bo Shen <voice.shen@atmel.com>
*
* Authors: Bo Shen <voice.shen@atmel.com>
* Boris Brezillon <boris.brezillon@free-electrons.com>
* Wu, Songjun <Songjun.Wu@atmel.com>
*
*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#define SII902X_TPI_VIDEO_DATA 0x0
#define SII902X_TPI_PIXEL_REPETITION 0x8
#define SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT BIT(5)
#define SII902X_TPI_AVI_PIXEL_REP_RISING_EDGE BIT(4)
#define SII902X_TPI_AVI_PIXEL_REP_4X 3
#define SII902X_TPI_AVI_PIXEL_REP_2X 1
#define SII902X_TPI_AVI_PIXEL_REP_NONE 0
#define SII902X_TPI_CLK_RATIO_HALF (0 << 6)
#define SII902X_TPI_CLK_RATIO_1X (1 << 6)
#define SII902X_TPI_CLK_RATIO_2X (2 << 6)
#define SII902X_TPI_CLK_RATIO_4X (3 << 6)
#define SII902X_TPI_AVI_IN_FORMAT 0x9
#define SII902X_TPI_AVI_INPUT_BITMODE_12BIT BIT(7)
#define SII902X_TPI_AVI_INPUT_DITHER BIT(6)
#define SII902X_TPI_AVI_INPUT_RANGE_LIMITED (2 << 2)
#define SII902X_TPI_AVI_INPUT_RANGE_FULL (1 << 2)
#define SII902X_TPI_AVI_INPUT_RANGE_AUTO (0 << 2)
#define SII902X_TPI_AVI_INPUT_COLORSPACE_BLACK (3 << 0)
#define SII902X_TPI_AVI_INPUT_COLORSPACE_YUV422 (2 << 0)
#define SII902X_TPI_AVI_INPUT_COLORSPACE_YUV444 (1 << 0)
#define SII902X_TPI_AVI_INPUT_COLORSPACE_RGB (0 << 0)
#define SII902X_TPI_AVI_INFOFRAME 0x0c
#define SII902X_SYS_CTRL_DATA 0x1a
#define SII902X_SYS_CTRL_PWR_DWN BIT(4)
#define SII902X_SYS_CTRL_AV_MUTE BIT(3)
#define SII902X_SYS_CTRL_DDC_BUS_REQ BIT(2)
#define SII902X_SYS_CTRL_DDC_BUS_GRTD BIT(1)
#define SII902X_SYS_CTRL_OUTPUT_MODE BIT(0)
#define SII902X_SYS_CTRL_OUTPUT_HDMI 1
#define SII902X_SYS_CTRL_OUTPUT_DVI 0
#define SII902X_REG_CHIPID(n) (0x1b + (n))
#define SII902X_PWR_STATE_CTRL 0x1e
#define SII902X_AVI_POWER_STATE_MSK GENMASK(1, 0)
#define SII902X_AVI_POWER_STATE_D(l) ((l) & SII902X_AVI_POWER_STATE_MSK)
#define SII902X_INT_ENABLE 0x3c
#define SII902X_INT_STATUS 0x3d
#define SII902X_HOTPLUG_EVENT BIT(0)
#define SII902X_PLUGGED_STATUS BIT(2)
#define SII902X_REG_TPI_RQB 0xc7
#define SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS 500
struct sii902x {
struct i2c_client *i2c;
struct regmap *regmap;
struct drm_bridge bridge;
struct drm_connector connector;
struct gpio_desc *reset_gpio;
};
static inline struct sii902x *bridge_to_sii902x(struct drm_bridge *bridge)
{
return container_of(bridge, struct sii902x, bridge);
}
static inline struct sii902x *connector_to_sii902x(struct drm_connector *con)
{
return container_of(con, struct sii902x, connector);
}
static void sii902x_reset(struct sii902x *sii902x)
{
if (!sii902x->reset_gpio)
return;
gpiod_set_value(sii902x->reset_gpio, 1);
/* The datasheet says treset-min = 100us. Make it 150us to be sure. */
usleep_range(150, 200);
gpiod_set_value(sii902x->reset_gpio, 0);
}
static enum drm_connector_status
sii902x_connector_detect(struct drm_connector *connector, bool force)
{
struct sii902x *sii902x = connector_to_sii902x(connector);
unsigned int status;
regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
return (status & SII902X_PLUGGED_STATUS) ?
connector_status_connected : connector_status_disconnected;
}
static const struct drm_connector_funcs sii902x_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = sii902x_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = drm_connector_cleanup,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static int sii902x_get_modes(struct drm_connector *connector)
{
struct sii902x *sii902x = connector_to_sii902x(connector);
struct regmap *regmap = sii902x->regmap;
u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
unsigned long timeout;
unsigned int status;
struct edid *edid;
int num = 0;
int ret;
ret = regmap_update_bits(regmap, SII902X_SYS_CTRL_DATA,
SII902X_SYS_CTRL_DDC_BUS_REQ,
SII902X_SYS_CTRL_DDC_BUS_REQ);
if (ret)
return ret;
timeout = jiffies +
msecs_to_jiffies(SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS);
do {
ret = regmap_read(regmap, SII902X_SYS_CTRL_DATA, &status);
if (ret)
return ret;
} while (!(status & SII902X_SYS_CTRL_DDC_BUS_GRTD) &&
time_before(jiffies, timeout));
if (!(status & SII902X_SYS_CTRL_DDC_BUS_GRTD)) {
dev_err(&sii902x->i2c->dev, "failed to acquire the i2c bus");
return -ETIMEDOUT;
}
ret = regmap_write(regmap, SII902X_SYS_CTRL_DATA, status);
if (ret)
return ret;
edid = drm_get_edid(connector, sii902x->i2c->adapter);
drm_mode_connector_update_edid_property(connector, edid);
if (edid) {
num = drm_add_edid_modes(connector, edid);
kfree(edid);
}
ret = drm_display_info_set_bus_formats(&connector->display_info,
&bus_format, 1);
if (ret)
return ret;
ret = regmap_read(regmap, SII902X_SYS_CTRL_DATA, &status);
if (ret)
return ret;
ret = regmap_update_bits(regmap, SII902X_SYS_CTRL_DATA,
SII902X_SYS_CTRL_DDC_BUS_REQ |
SII902X_SYS_CTRL_DDC_BUS_GRTD, 0);
if (ret)
return ret;
timeout = jiffies +
msecs_to_jiffies(SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS);
do {
ret = regmap_read(regmap, SII902X_SYS_CTRL_DATA, &status);
if (ret)
return ret;
} while (status & (SII902X_SYS_CTRL_DDC_BUS_REQ |
SII902X_SYS_CTRL_DDC_BUS_GRTD) &&
time_before(jiffies, timeout));
if (status & (SII902X_SYS_CTRL_DDC_BUS_REQ |
SII902X_SYS_CTRL_DDC_BUS_GRTD)) {
dev_err(&sii902x->i2c->dev, "failed to release the i2c bus");
return -ETIMEDOUT;
}
return num;
}
static enum drm_mode_status sii902x_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
/* TODO: check mode */
return MODE_OK;
}
static const struct drm_connector_helper_funcs sii902x_connector_helper_funcs = {
.get_modes = sii902x_get_modes,
.mode_valid = sii902x_mode_valid,
};
static void sii902x_bridge_disable(struct drm_bridge *bridge)
{
struct sii902x *sii902x = bridge_to_sii902x(bridge);
regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
SII902X_SYS_CTRL_PWR_DWN,
SII902X_SYS_CTRL_PWR_DWN);
}
static void sii902x_bridge_enable(struct drm_bridge *bridge)
{
struct sii902x *sii902x = bridge_to_sii902x(bridge);
regmap_update_bits(sii902x->regmap, SII902X_PWR_STATE_CTRL,
SII902X_AVI_POWER_STATE_MSK,
SII902X_AVI_POWER_STATE_D(0));
regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
SII902X_SYS_CTRL_PWR_DWN, 0);
}
static void sii902x_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
struct sii902x *sii902x = bridge_to_sii902x(bridge);
struct regmap *regmap = sii902x->regmap;
u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
struct hdmi_avi_infoframe frame;
int ret;
buf[0] = adj->clock;
buf[1] = adj->clock >> 8;
buf[2] = adj->vrefresh;
buf[3] = 0x00;
buf[4] = adj->hdisplay;
buf[5] = adj->hdisplay >> 8;
buf[6] = adj->vdisplay;
buf[7] = adj->vdisplay >> 8;
buf[8] = SII902X_TPI_CLK_RATIO_1X | SII902X_TPI_AVI_PIXEL_REP_NONE |
SII902X_TPI_AVI_PIXEL_REP_BUS_24BIT;
buf[9] = SII902X_TPI_AVI_INPUT_RANGE_AUTO |
SII902X_TPI_AVI_INPUT_COLORSPACE_RGB;
ret = regmap_bulk_write(regmap, SII902X_TPI_VIDEO_DATA, buf, 10);
if (ret)
return;
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, adj);
if (ret < 0) {
DRM_ERROR("couldn't fill AVI infoframe\n");
return;
}
ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
if (ret < 0) {
DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
return;
}
/* Do not send the infoframe header, but keep the CRC field. */
regmap_bulk_write(regmap, SII902X_TPI_AVI_INFOFRAME,
buf + HDMI_INFOFRAME_HEADER_SIZE - 1,
HDMI_AVI_INFOFRAME_SIZE + 1);
}
static int sii902x_bridge_attach(struct drm_bridge *bridge)
{
struct sii902x *sii902x = bridge_to_sii902x(bridge);
struct drm_device *drm = bridge->dev;
int ret;
drm_connector_helper_add(&sii902x->connector,
&sii902x_connector_helper_funcs);
if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) {
dev_err(&sii902x->i2c->dev,
"sii902x driver is only compatible with DRM devices supporting atomic updates");
return -ENOTSUPP;
}
ret = drm_connector_init(drm, &sii902x->connector,
&sii902x_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA);
if (ret)
return ret;
if (sii902x->i2c->irq > 0)
sii902x->connector.polled = DRM_CONNECTOR_POLL_HPD;
else
sii902x->connector.polled = DRM_CONNECTOR_POLL_CONNECT;
drm_mode_connector_attach_encoder(&sii902x->connector, bridge->encoder);
return 0;
}
static const struct drm_bridge_funcs sii902x_bridge_funcs = {
.attach = sii902x_bridge_attach,
.mode_set = sii902x_bridge_mode_set,
.disable = sii902x_bridge_disable,
.enable = sii902x_bridge_enable,
};
static const struct regmap_range sii902x_volatile_ranges[] = {
{ .range_min = 0, .range_max = 0xff },
};
static const struct regmap_access_table sii902x_volatile_table = {
.yes_ranges = sii902x_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(sii902x_volatile_ranges),
};
static const struct regmap_config sii902x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &sii902x_volatile_table,
.cache_type = REGCACHE_NONE,
};
static irqreturn_t sii902x_interrupt(int irq, void *data)
{
struct sii902x *sii902x = data;
unsigned int status = 0;
regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
regmap_write(sii902x->regmap, SII902X_INT_STATUS, status);
if ((status & SII902X_HOTPLUG_EVENT) && sii902x->bridge.dev)
drm_helper_hpd_irq_event(sii902x->bridge.dev);
return IRQ_HANDLED;
}
static int sii902x_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct device *dev = &client->dev;
unsigned int status = 0;
struct sii902x *sii902x;
u8 chipid[4];
int ret;
sii902x = devm_kzalloc(dev, sizeof(*sii902x), GFP_KERNEL);
if (!sii902x)
return -ENOMEM;
sii902x->i2c = client;
sii902x->regmap = devm_regmap_init_i2c(client, &sii902x_regmap_config);
if (IS_ERR(sii902x->regmap))
return PTR_ERR(sii902x->regmap);
sii902x->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(sii902x->reset_gpio)) {
dev_err(dev, "Failed to retrieve/request reset gpio: %ld\n",
PTR_ERR(sii902x->reset_gpio));
return PTR_ERR(sii902x->reset_gpio);
}
sii902x_reset(sii902x);
ret = regmap_write(sii902x->regmap, SII902X_REG_TPI_RQB, 0x0);
if (ret)
return ret;
ret = regmap_bulk_read(sii902x->regmap, SII902X_REG_CHIPID(0),
&chipid, 4);
if (ret) {
dev_err(dev, "regmap_read failed %d\n", ret);
return ret;
}
if (chipid[0] != 0xb0) {
dev_err(dev, "Invalid chipid: %02x (expecting 0xb0)\n",
chipid[0]);
return -EINVAL;
}
/* Clear all pending interrupts */
regmap_read(sii902x->regmap, SII902X_INT_STATUS, &status);
regmap_write(sii902x->regmap, SII902X_INT_STATUS, status);
if (client->irq > 0) {
regmap_write(sii902x->regmap, SII902X_INT_ENABLE,
SII902X_HOTPLUG_EVENT);
ret = devm_request_threaded_irq(dev, client->irq, NULL,
sii902x_interrupt,
IRQF_ONESHOT, dev_name(dev),
sii902x);
if (ret)
return ret;
}
sii902x->bridge.funcs = &sii902x_bridge_funcs;
sii902x->bridge.of_node = dev->of_node;
ret = drm_bridge_add(&sii902x->bridge);
if (ret) {
dev_err(dev, "Failed to add drm_bridge\n");
return ret;
}
i2c_set_clientdata(client, sii902x);
return 0;
}
static int sii902x_remove(struct i2c_client *client)
{
struct sii902x *sii902x = i2c_get_clientdata(client);
drm_bridge_remove(&sii902x->bridge);
return 0;
}
static const struct of_device_id sii902x_dt_ids[] = {
{ .compatible = "sil,sii9022", },
{ }
};
MODULE_DEVICE_TABLE(of, sii902x_dt_ids);
static const struct i2c_device_id sii902x_i2c_ids[] = {
{ "sii9022", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, sii902x_i2c_ids);
static struct i2c_driver sii902x_driver = {
.probe = sii902x_probe,
.remove = sii902x_remove,
.driver = {
.name = "sii902x",
.of_match_table = sii902x_dt_ids,
},
.id_table = sii902x_i2c_ids,
};
module_i2c_driver(sii902x_driver);
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
MODULE_DESCRIPTION("SII902x RGB -> HDMI bridges");
MODULE_LICENSE("GPL");

285
drivers/gpu/drm/drm_auth.c
View File

@ -30,25 +30,36 @@
#include <drm/drmP.h>
#include "drm_internal.h"
#include "drm_legacy.h"
/**
* drm_getmagic - Get unique magic of a client
* @dev: DRM device to operate on
* @data: ioctl data containing the drm_auth object
* @file_priv: DRM file that performs the operation
* DOC: master and authentication
*
* This looks up the unique magic of the passed client and returns it. If the
* client did not have a magic assigned, yet, a new one is registered. The magic
* is stored in the passed drm_auth object.
* struct &drm_master is used to track groups of clients with open
* primary/legacy device nodes. For every struct &drm_file which has had at
* least once successfully became the device master (either through the
* SET_MASTER IOCTL, or implicitly through opening the primary device node when
* no one else is the current master that time) there exists one &drm_master.
* This is noted in the is_master member of &drm_file. All other clients have
* just a pointer to the &drm_master they are associated with.
*
* Returns: 0 on success, negative error code on failure.
* In addition only one &drm_master can be the current master for a &drm_device.
* It can be switched through the DROP_MASTER and SET_MASTER IOCTL, or
* implicitly through closing/openeing the primary device node. See also
* drm_is_current_master().
*
* Clients can authenticate against the current master (if it matches their own)
* using the GETMAGIC and AUTHMAGIC IOCTLs. Together with exchanging masters,
* this allows controlled access to the device for an entire group of mutually
* trusted clients.
*/
int drm_getmagic(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
struct drm_auth *auth = data;
int ret = 0;
mutex_lock(&dev->struct_mutex);
mutex_lock(&dev->master_mutex);
if (!file_priv->magic) {
ret = idr_alloc(&file_priv->master->magic_map, file_priv,
1, 0, GFP_KERNEL);
@ -56,23 +67,13 @@ int drm_getmagic(struct drm_device *dev, void *data, struct drm_file *file_priv)
file_priv->magic = ret;
}
auth->magic = file_priv->magic;
mutex_unlock(&dev->struct_mutex);
mutex_unlock(&dev->master_mutex);
DRM_DEBUG("%u\n", auth->magic);
return ret < 0 ? ret : 0;
}
/**
* drm_authmagic - Authenticate client with a magic
* @dev: DRM device to operate on
* @data: ioctl data containing the drm_auth object
* @file_priv: DRM file that performs the operation
*
* This looks up a DRM client by the passed magic and authenticates it.
*
* Returns: 0 on success, negative error code on failure.
*/
int drm_authmagic(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
@ -81,13 +82,253 @@ int drm_authmagic(struct drm_device *dev, void *data,
DRM_DEBUG("%u\n", auth->magic);
mutex_lock(&dev->struct_mutex);
mutex_lock(&dev->master_mutex);
file = idr_find(&file_priv->master->magic_map, auth->magic);
if (file) {
file->authenticated = 1;
idr_replace(&file_priv->master->magic_map, NULL, auth->magic);
}
mutex_unlock(&dev->struct_mutex);
mutex_unlock(&dev->master_mutex);
return file ? 0 : -EINVAL;
}
static struct drm_master *drm_master_create(struct drm_device *dev)
{
struct drm_master *master;
master = kzalloc(sizeof(*master), GFP_KERNEL);
if (!master)
return NULL;
kref_init(&master->refcount);
spin_lock_init(&master->lock.spinlock);
init_waitqueue_head(&master->lock.lock_queue);
idr_init(&master->magic_map);
master->dev = dev;
return master;
}
static int drm_set_master(struct drm_device *dev, struct drm_file *fpriv,
bool new_master)
{
int ret = 0;
dev->master = drm_master_get(fpriv->master);
if (dev->driver->master_set) {
ret = dev->driver->master_set(dev, fpriv, new_master);
if (unlikely(ret != 0)) {
drm_master_put(&dev->master);
}
}
return ret;
}
static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv)
{
struct drm_master *old_master;
int ret;
lockdep_assert_held_once(&dev->master_mutex);
old_master = fpriv->master;
fpriv->master = drm_master_create(dev);
if (!fpriv->master) {
fpriv->master = old_master;
return -ENOMEM;
}
if (dev->driver->master_create) {
ret = dev->driver->master_create(dev, fpriv->master);
if (ret)
goto out_err;
}
fpriv->is_master = 1;
fpriv->authenticated = 1;
ret = drm_set_master(dev, fpriv, true);
if (ret)
goto out_err;
if (old_master)
drm_master_put(&old_master);
return 0;
out_err:
/* drop references and restore old master on failure */
drm_master_put(&fpriv->master);
fpriv->master = old_master;
return ret;
}
int drm_setmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
int ret = 0;
mutex_lock(&dev->master_mutex);
if (drm_is_current_master(file_priv))
goto out_unlock;
if (dev->master) {
ret = -EINVAL;
goto out_unlock;
}
if (!file_priv->master) {
ret = -EINVAL;
goto out_unlock;
}
if (!file_priv->is_master) {
ret = drm_new_set_master(dev, file_priv);
goto out_unlock;
}
ret = drm_set_master(dev, file_priv, false);
out_unlock:
mutex_unlock(&dev->master_mutex);
return ret;
}
static void drm_drop_master(struct drm_device *dev,
struct drm_file *fpriv)
{
if (dev->driver->master_drop)
dev->driver->master_drop(dev, fpriv);
drm_master_put(&dev->master);
}
int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
int ret = -EINVAL;
mutex_lock(&dev->master_mutex);
if (!drm_is_current_master(file_priv))
goto out_unlock;
if (!dev->master)
goto out_unlock;
ret = 0;
drm_drop_master(dev, file_priv);
out_unlock:
mutex_unlock(&dev->master_mutex);
return ret;
}
int drm_master_open(struct drm_file *file_priv)
{
struct drm_device *dev = file_priv->minor->dev;
int ret = 0;
/* if there is no current master make this fd it, but do not create
* any master object for render clients */
mutex_lock(&dev->master_mutex);
if (!dev->master)
ret = drm_new_set_master(dev, file_priv);
else
file_priv->master = drm_master_get(dev->master);
mutex_unlock(&dev->master_mutex);
return ret;
}
void drm_master_release(struct drm_file *file_priv)
{
struct drm_device *dev = file_priv->minor->dev;
struct drm_master *master = file_priv->master;
mutex_lock(&dev->master_mutex);
if (file_priv->magic)
idr_remove(&file_priv->master->magic_map, file_priv->magic);
if (!drm_is_current_master(file_priv))
goto out;
if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
/*
* Since the master is disappearing, so is the
* possibility to lock.
*/
mutex_lock(&dev->struct_mutex);
if (master->lock.hw_lock) {
if (dev->sigdata.lock == master->lock.hw_lock)
dev->sigdata.lock = NULL;
master->lock.hw_lock = NULL;
master->lock.file_priv = NULL;
wake_up_interruptible_all(&master->lock.lock_queue);
}
mutex_unlock(&dev->struct_mutex);
}
if (dev->master == file_priv->master)
drm_drop_master(dev, file_priv);
out:
/* drop the master reference held by the file priv */
if (file_priv->master)
drm_master_put(&file_priv->master);
mutex_unlock(&dev->master_mutex);
}
/**
* drm_is_current_master - checks whether @priv is the current master
* @fpriv: DRM file private
*
* Checks whether @fpriv is current master on its device. This decides whether a
* client is allowed to run DRM_MASTER IOCTLs.
*
* Most of the modern IOCTL which require DRM_MASTER are for kernel modesetting
* - the current master is assumed to own the non-shareable display hardware.
*/
bool drm_is_current_master(struct drm_file *fpriv)
{
return fpriv->is_master && fpriv->master == fpriv->minor->dev->master;
}
EXPORT_SYMBOL(drm_is_current_master);
/**
* drm_master_get - reference a master pointer
* @master: struct &drm_master
*
* Increments the reference count of @master and returns a pointer to @master.
*/
struct drm_master *drm_master_get(struct drm_master *master)
{
kref_get(&master->refcount);
return master;
}
EXPORT_SYMBOL(drm_master_get);
static void drm_master_destroy(struct kref *kref)
{
struct drm_master *master = container_of(kref, struct drm_master, refcount);
struct drm_device *dev = master->dev;
if (dev->driver->master_destroy)
dev->driver->master_destroy(dev, master);
drm_legacy_master_rmmaps(dev, master);
idr_destroy(&master->magic_map);
kfree(master->unique);
kfree(master);
}
/**
* drm_master_put - unreference and clear a master pointer
* @master: pointer to a pointer of struct &drm_master
*
* This decrements the &drm_master behind @master and sets it to NULL.
*/
void drm_master_put(struct drm_master **master)
{
kref_put(&(*master)->refcount, drm_master_destroy);
*master = NULL;
}
EXPORT_SYMBOL(drm_master_put);

8
drivers/gpu/drm/drm_bufs.c
View File

@ -51,7 +51,7 @@ static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
*/
if (!entry->map ||
map->type != entry->map->type ||
entry->master != dev->primary->master)
entry->master != dev->master)
continue;
switch (map->type) {
case _DRM_SHM:
@ -245,12 +245,12 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
map->offset = (unsigned long)map->handle;
if (map->flags & _DRM_CONTAINS_LOCK) {
/* Prevent a 2nd X Server from creating a 2nd lock */
if (dev->primary->master->lock.hw_lock != NULL) {
if (dev->master->lock.hw_lock != NULL) {
vfree(map->handle);
kfree(map);
return -EBUSY;
}
dev->sigdata.lock = dev->primary->master->lock.hw_lock = map->handle; /* Pointer to lock */
dev->sigdata.lock = dev->master->lock.hw_lock = map->handle; /* Pointer to lock */
}
break;
case _DRM_AGP: {
@ -356,7 +356,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
mutex_unlock(&dev->struct_mutex);
if (!(map->flags & _DRM_DRIVER))
list->master = dev->primary->master;
list->master = dev->master;
*maplist = list;
return 0;
}

164
drivers/gpu/drm/drm_crtc.c
View File

@ -39,6 +39,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_modeset_lock.h>
#include <drm/drm_atomic.h>
#include <drm/drm_auth.h>
#include "drm_crtc_internal.h"
#include "drm_internal.h"
@ -608,6 +609,31 @@ static unsigned int drm_num_crtcs(struct drm_device *dev)
return num;
}
static int drm_crtc_register_all(struct drm_device *dev)
{
struct drm_crtc *crtc;
int ret = 0;
drm_for_each_crtc(crtc, dev) {
if (crtc->funcs->late_register)
ret = crtc->funcs->late_register(crtc);
if (ret)
return ret;
}
return 0;
}
static void drm_crtc_unregister_all(struct drm_device *dev)
{
struct drm_crtc *crtc;
drm_for_each_crtc(crtc, dev) {
if (crtc->funcs->early_unregister)
crtc->funcs->early_unregister(crtc);
}
}
/**
* drm_crtc_init_with_planes - Initialise a new CRTC object with
* specified primary and cursor planes.
@ -938,6 +964,12 @@ void drm_connector_cleanup(struct drm_connector *connector)
struct drm_device *dev = connector->dev;
struct drm_display_mode *mode, *t;
/* The connector should have been removed from userspace long before
* it is finally destroyed.
*/
if (WARN_ON(connector->registered))
drm_connector_unregister(connector);
if (connector->tile_group) {
drm_mode_put_tile_group(dev, connector->tile_group);
connector->tile_group = NULL;
@ -984,19 +1016,34 @@ int drm_connector_register(struct drm_connector *connector)
{
int ret;
if (connector->registered)
return 0;
ret = drm_sysfs_connector_add(connector);
if (ret)
return ret;
ret = drm_debugfs_connector_add(connector);
if (ret) {
drm_sysfs_connector_remove(connector);
return ret;
goto err_sysfs;
}
if (connector->funcs->late_register) {
ret = connector->funcs->late_register(connector);
if (ret)
goto err_debugfs;
}
drm_mode_object_register(connector->dev, &connector->base);
connector->registered = true;
return 0;
err_debugfs:
drm_debugfs_connector_remove(connector);
err_sysfs:
drm_sysfs_connector_remove(connector);
return ret;
}
EXPORT_SYMBOL(drm_connector_register);
@ -1008,8 +1055,16 @@ EXPORT_SYMBOL(drm_connector_register);
*/
void drm_connector_unregister(struct drm_connector *connector)
{
if (!connector->registered)
return;
if (connector->funcs->early_unregister)
connector->funcs->early_unregister(connector);
drm_sysfs_connector_remove(connector);
drm_debugfs_connector_remove(connector);
connector->registered = false;
}
EXPORT_SYMBOL(drm_connector_unregister);
@ -1018,9 +1073,9 @@ EXPORT_SYMBOL(drm_connector_unregister);
* @dev: drm device
*
* This function registers all connectors in sysfs and other places so that
* userspace can start to access them. Drivers can call it after calling
* drm_dev_register() to complete the device registration, if they don't call
* drm_connector_register() on each connector individually.
* userspace can start to access them. drm_connector_register_all() is called
* automatically from drm_dev_register() to complete the device registration,
* if they don't call drm_connector_register() on each connector individually.
*
* When a device is unplugged and should be removed from userspace access,
* call drm_connector_unregister_all(), which is the inverse of this
@ -1073,6 +1128,31 @@ void drm_connector_unregister_all(struct drm_device *dev)
}
EXPORT_SYMBOL(drm_connector_unregister_all);
static int drm_encoder_register_all(struct drm_device *dev)
{
struct drm_encoder *encoder;
int ret = 0;
drm_for_each_encoder(encoder, dev) {
if (encoder->funcs->late_register)
ret = encoder->funcs->late_register(encoder);
if (ret)
return ret;
}
return 0;
}
static void drm_encoder_unregister_all(struct drm_device *dev)
{
struct drm_encoder *encoder;
drm_for_each_encoder(encoder, dev) {
if (encoder->funcs->early_unregister)
encoder->funcs->early_unregister(encoder);
}
}
/**
* drm_encoder_init - Init a preallocated encoder
* @dev: drm device
@ -1261,6 +1341,31 @@ int drm_universal_plane_init(struct drm_device *dev, struct drm_plane *plane,
}
EXPORT_SYMBOL(drm_universal_plane_init);
static int drm_plane_register_all(struct drm_device *dev)
{
struct drm_plane *plane;
int ret = 0;
drm_for_each_plane(plane, dev) {
if (plane->funcs->late_register)
ret = plane->funcs->late_register(plane);
if (ret)
return ret;
}
return 0;
}
static void drm_plane_unregister_all(struct drm_device *dev)
{
struct drm_plane *plane;
drm_for_each_plane(plane, dev) {
if (plane->funcs->early_unregister)
plane->funcs->early_unregister(plane);
}
}
/**
* drm_plane_init - Initialize a legacy plane
* @dev: DRM device
@ -1383,6 +1488,46 @@ void drm_plane_force_disable(struct drm_plane *plane)
}
EXPORT_SYMBOL(drm_plane_force_disable);
int drm_modeset_register_all(struct drm_device *dev)
{
int ret;
ret = drm_plane_register_all(dev);
if (ret)
goto err_plane;
ret = drm_crtc_register_all(dev);
if (ret)
goto err_crtc;
ret = drm_encoder_register_all(dev);
if (ret)
goto err_encoder;
ret = drm_connector_register_all(dev);
if (ret)
goto err_connector;
return 0;
err_connector:
drm_encoder_unregister_all(dev);
err_encoder:
drm_crtc_unregister_all(dev);
err_crtc:
drm_plane_unregister_all(dev);
err_plane:
return ret;
}
void drm_modeset_unregister_all(struct drm_device *dev)
{
drm_connector_unregister_all(dev);
drm_encoder_unregister_all(dev);
drm_crtc_unregister_all(dev);
drm_plane_unregister_all(dev);
}
static int drm_mode_create_standard_properties(struct drm_device *dev)
{
struct drm_property *prop;
@ -3499,7 +3644,7 @@ int drm_mode_getfb(struct drm_device *dev,
r->bpp = fb->bits_per_pixel;
r->pitch = fb->pitches[0];
if (fb->funcs->create_handle) {
if (file_priv->is_master || capable(CAP_SYS_ADMIN) ||
if (drm_is_current_master(file_priv) || capable(CAP_SYS_ADMIN) ||
drm_is_control_client(file_priv)) {
ret = fb->funcs->create_handle(fb, file_priv,
&r->handle);
@ -3656,6 +3801,13 @@ void drm_fb_release(struct drm_file *priv)
}
}
static bool drm_property_type_valid(struct drm_property *property)
{
if (property->flags & DRM_MODE_PROP_EXTENDED_TYPE)
return !(property->flags & DRM_MODE_PROP_LEGACY_TYPE);
return !!(property->flags & DRM_MODE_PROP_LEGACY_TYPE);
}
/**
* drm_property_create - create a new property type
* @dev: drm device

3
drivers/gpu/drm/drm_crtc_helper.c
View File

@ -232,6 +232,9 @@ static void __drm_helper_disable_unused_functions(struct drm_device *dev)
*/
void drm_helper_disable_unused_functions(struct drm_device *dev)
{
if (drm_core_check_feature(dev, DRIVER_ATOMIC))
DRM_ERROR("Called for atomic driver, this is not what you want.\n");
drm_modeset_lock_all(dev);
__drm_helper_disable_unused_functions(dev);
drm_modeset_unlock_all(dev);

88
drivers/gpu/drm/drm_crtc_internal.h
View File

@ -31,14 +31,100 @@
* and are not exported to drivers.
*/
/* drm_crtc.c */
void drm_connector_ida_init(void);
void drm_connector_ida_destroy(void);
int drm_mode_object_get(struct drm_device *dev,
struct drm_mode_object *obj, uint32_t obj_type);
void drm_mode_object_unregister(struct drm_device *dev,
struct drm_mode_object *object);
bool drm_property_change_valid_get(struct drm_property *property,
uint64_t value,
struct drm_mode_object **ref);
void drm_property_change_valid_put(struct drm_property *property,
struct drm_mode_object *ref);
int drm_plane_check_pixel_format(const struct drm_plane *plane,
u32 format);
int drm_crtc_check_viewport(const struct drm_crtc *crtc,
int x, int y,
const struct drm_display_mode *mode,
const struct drm_framebuffer *fb);
void drm_fb_release(struct drm_file *file_priv);
void drm_property_destroy_user_blobs(struct drm_device *dev,
struct drm_file *file_priv);
/* dumb buffer support IOCTLs */
int drm_mode_create_dumb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_mmap_dumb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
/* framebuffer IOCTLs */
extern int drm_mode_addfb(struct drm_device *dev,
void *data, struct drm_file *file_priv);
extern int drm_mode_addfb2(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_rmfb(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getfb(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
/* IOCTLs */
int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_mode_getresources(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getplane_res(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_mode_getcrtc(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getconnector(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_setcrtc(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getplane(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_setplane(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_cursor_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_cursor2_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getproperty_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getblob_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_createblob_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_destroyblob_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_getencoder(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_gamma_get_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_gamma_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_mode_page_flip_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
/* drm_atomic.c */
int drm_atomic_get_property(struct drm_mode_object *obj,
struct drm_property *property, uint64_t *val);
struct drm_property *property, uint64_t *val);
int drm_mode_atomic_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
int drm_modeset_register_all(struct drm_device *dev);
void drm_modeset_unregister_all(struct drm_device *dev);

3
drivers/gpu/drm/drm_debugfs.c
View File

@ -46,11 +46,8 @@
static const struct drm_info_list drm_debugfs_list[] = {
{"name", drm_name_info, 0},
{"vm", drm_vm_info, 0},
{"clients", drm_clients_info, 0},
{"bufs", drm_bufs_info, 0},
{"gem_names", drm_gem_name_info, DRIVER_GEM},
{"vma", drm_vma_info, 0},
};
#define DRM_DEBUGFS_ENTRIES ARRAY_SIZE(drm_debugfs_list)

56
drivers/gpu/drm/drm_dp_helper.c
View File

@ -708,8 +708,6 @@ static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
memset(&msg, 0, sizeof(msg));
mutex_lock(&aux->hw_mutex);
for (i = 0; i < num; i++) {
msg.address = msgs[i].addr;
drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
@ -764,8 +762,6 @@ static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
msg.size = 0;
(void)drm_dp_i2c_do_msg(aux, &msg);
mutex_unlock(&aux->hw_mutex);
return err;
}
@ -774,21 +770,63 @@ static const struct i2c_algorithm drm_dp_i2c_algo = {
.master_xfer = drm_dp_i2c_xfer,
};
static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
{
return container_of(i2c, struct drm_dp_aux, ddc);
}
static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
{
mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
}
static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
{
return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
}
static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
{
mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
}
/**
* drm_dp_aux_init() - minimally initialise an aux channel
* @aux: DisplayPort AUX channel
*
* If you need to use the drm_dp_aux's i2c adapter prior to registering it
* with the outside world, call drm_dp_aux_init() first. You must still
* call drm_dp_aux_register() once the connector has been registered to
* allow userspace access to the auxiliary DP channel.
*/
void drm_dp_aux_init(struct drm_dp_aux *aux)
{
mutex_init(&aux->hw_mutex);
aux->ddc.algo = &drm_dp_i2c_algo;
aux->ddc.algo_data = aux;
aux->ddc.retries = 3;
aux->ddc.lock_bus = lock_bus;
aux->ddc.trylock_bus = trylock_bus;
aux->ddc.unlock_bus = unlock_bus;
}
EXPORT_SYMBOL(drm_dp_aux_init);
/**
* drm_dp_aux_register() - initialise and register aux channel
* @aux: DisplayPort AUX channel
*
* Automatically calls drm_dp_aux_init() if this hasn't been done yet.
*
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_aux_register(struct drm_dp_aux *aux)
{
int ret;
mutex_init(&aux->hw_mutex);
aux->ddc.algo = &drm_dp_i2c_algo;
aux->ddc.algo_data = aux;
aux->ddc.retries = 3;
if (!aux->ddc.algo)
drm_dp_aux_init(aux);
aux->ddc.class = I2C_CLASS_DDC;
aux->ddc.owner = THIS_MODULE;

239
drivers/gpu/drm/drm_drv.c
View File

@ -34,8 +34,10 @@
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_core.h>
#include "drm_crtc_internal.h"
#include "drm_legacy.h"
#include "drm_internal.h"
#include "drm_crtc_internal.h"
/*
* drm_debug: Enable debug output.
@ -93,114 +95,6 @@ void drm_ut_debug_printk(const char *function_name, const char *format, ...)
}
EXPORT_SYMBOL(drm_ut_debug_printk);
struct drm_master *drm_master_create(struct drm_minor *minor)
{
struct drm_master *master;
master = kzalloc(sizeof(*master), GFP_KERNEL);
if (!master)
return NULL;
kref_init(&master->refcount);
spin_lock_init(&master->lock.spinlock);
init_waitqueue_head(&master->lock.lock_queue);
idr_init(&master->magic_map);
master->minor = minor;
return master;
}
struct drm_master *drm_master_get(struct drm_master *master)
{
kref_get(&master->refcount);
return master;
}
EXPORT_SYMBOL(drm_master_get);
static void drm_master_destroy(struct kref *kref)
{
struct drm_master *master = container_of(kref, struct drm_master, refcount);
struct drm_device *dev = master->minor->dev;
if (dev->driver->master_destroy)
dev->driver->master_destroy(dev, master);
drm_legacy_master_rmmaps(dev, master);
idr_destroy(&master->magic_map);
kfree(master->unique);
kfree(master);
}
void drm_master_put(struct drm_master **master)
{
kref_put(&(*master)->refcount, drm_master_destroy);
*master = NULL;
}
EXPORT_SYMBOL(drm_master_put);
int drm_setmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
int ret = 0;
mutex_lock(&dev->master_mutex);
if (file_priv->is_master)
goto out_unlock;
if (file_priv->minor->master) {
ret = -EINVAL;
goto out_unlock;
}
if (!file_priv->master) {
ret = -EINVAL;
goto out_unlock;
}
if (!file_priv->allowed_master) {
ret = drm_new_set_master(dev, file_priv);
goto out_unlock;
}
file_priv->minor->master = drm_master_get(file_priv->master);
file_priv->is_master = 1;
if (dev->driver->master_set) {
ret = dev->driver->master_set(dev, file_priv, false);
if (unlikely(ret != 0)) {
file_priv->is_master = 0;
drm_master_put(&file_priv->minor->master);
}
}
out_unlock:
mutex_unlock(&dev->master_mutex);
return ret;
}
int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
int ret = -EINVAL;
mutex_lock(&dev->master_mutex);
if (!file_priv->is_master)
goto out_unlock;
if (!file_priv->minor->master)
goto out_unlock;
ret = 0;
if (dev->driver->master_drop)
dev->driver->master_drop(dev, file_priv, false);
drm_master_put(&file_priv->minor->master);
file_priv->is_master = 0;
out_unlock:
mutex_unlock(&dev->master_mutex);
return ret;
}
/*
* DRM Minors
* A DRM device can provide several char-dev interfaces on the DRM-Major. Each
@ -405,10 +299,9 @@ void drm_minor_release(struct drm_minor *minor)
* callbacks implemented by the driver. The driver then needs to initialize all
* the various subsystems for the drm device like memory management, vblank
* handling, modesetting support and intial output configuration plus obviously
* initialize all the corresponding hardware bits. An important part of this is
* also calling drm_dev_set_unique() to set the userspace-visible unique name of
* this device instance. Finally when everything is up and running and ready for
* userspace the device instance can be published using drm_dev_register().
* initialize all the corresponding hardware bits. Finally when everything is up
* and running and ready for userspace the device instance can be published
* using drm_dev_register().
*
* There is also deprecated support for initalizing device instances using
* bus-specific helpers and the ->load() callback. But due to
@ -430,6 +323,14 @@ void drm_minor_release(struct drm_minor *minor)
* dev_priv field of &drm_device.
*/
static int drm_dev_set_unique(struct drm_device *dev, const char *name)
{
kfree(dev->unique);
dev->unique = kstrdup(name, GFP_KERNEL);
return dev->unique ? 0 : -ENOMEM;
}
/**
* drm_put_dev - Unregister and release a DRM device
* @dev: DRM device
@ -549,11 +450,12 @@ static void drm_fs_inode_free(struct inode *inode)
}
/**
* drm_dev_alloc - Allocate new DRM device
* @driver: DRM driver to allocate device for
* drm_dev_init - Initialise new DRM device
* @dev: DRM device
* @driver: DRM driver
* @parent: Parent device object
*
* Allocate and initialize a new DRM device. No device registration is done.
* Initialize a new DRM device. No device registration is done.
* Call drm_dev_register() to advertice the device to user space and register it
* with other core subsystems. This should be done last in the device
* initialization sequence to make sure userspace can't access an inconsistent
@ -564,19 +466,18 @@ static void drm_fs_inode_free(struct inode *inode)
*
* Note that for purely virtual devices @parent can be NULL.
*
* Drivers that do not want to allocate their own device struct
* embedding struct &drm_device can call drm_dev_alloc() instead.
*
* RETURNS:
* Pointer to new DRM device, or NULL if out of memory.
* 0 on success, or error code on failure.
*/
struct drm_device *drm_dev_alloc(struct drm_driver *driver,
struct device *parent)
int drm_dev_init(struct drm_device *dev,
struct drm_driver *driver,
struct device *parent)
{
struct drm_device *dev;
int ret;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return NULL;
kref_init(&dev->ref);
dev->dev = parent;
dev->driver = driver;
@ -617,7 +518,8 @@ struct drm_device *drm_dev_alloc(struct drm_driver *driver,
if (ret)
goto err_minors;
if (drm_ht_create(&dev->map_hash, 12))
ret = drm_ht_create(&dev->map_hash, 12);
if (ret)
goto err_minors;
drm_legacy_ctxbitmap_init(dev);
@ -630,13 +532,13 @@ struct drm_device *drm_dev_alloc(struct drm_driver *driver,
}
}
if (parent) {
ret = drm_dev_set_unique(dev, dev_name(parent));
if (ret)
goto err_setunique;
}
/* Use the parent device name as DRM device unique identifier, but fall
* back to the driver name for virtual devices like vgem. */
ret = drm_dev_set_unique(dev, parent ? dev_name(parent) : driver->name);
if (ret)
goto err_setunique;
return dev;
return 0;
err_setunique:
if (drm_core_check_feature(dev, DRIVER_GEM))
@ -651,8 +553,49 @@ err_minors:
drm_fs_inode_free(dev->anon_inode);
err_free:
mutex_destroy(&dev->master_mutex);
kfree(dev);
return NULL;
return ret;
}
EXPORT_SYMBOL(drm_dev_init);
/**
* drm_dev_alloc - Allocate new DRM device
* @driver: DRM driver to allocate device for
* @parent: Parent device object
*
* Allocate and initialize a new DRM device. No device registration is done.
* Call drm_dev_register() to advertice the device to user space and register it
* with other core subsystems. This should be done last in the device
* initialization sequence to make sure userspace can't access an inconsistent
* state.
*
* The initial ref-count of the object is 1. Use drm_dev_ref() and
* drm_dev_unref() to take and drop further ref-counts.
*
* Note that for purely virtual devices @parent can be NULL.
*
* Drivers that wish to subclass or embed struct &drm_device into their
* own struct should look at using drm_dev_init() instead.
*
* RETURNS:
* Pointer to new DRM device, or NULL if out of memory.
*/
struct drm_device *drm_dev_alloc(struct drm_driver *driver,
struct device *parent)
{
struct drm_device *dev;
int ret;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return NULL;
ret = drm_dev_init(dev, driver, parent);
if (ret) {
kfree(dev);
return NULL;
}
return dev;
}
EXPORT_SYMBOL(drm_dev_alloc);
@ -716,11 +659,7 @@ EXPORT_SYMBOL(drm_dev_unref);
*
* Register the DRM device @dev with the system, advertise device to user-space
* and start normal device operation. @dev must be allocated via drm_dev_alloc()
* previously. Right after drm_dev_register() the driver should call
* drm_connector_register_all() to register all connectors in sysfs. This is
* a separate call for backward compatibility with drivers still using
* the deprecated ->load() callback, where connectors are registered from within
* the ->load() callback.
* previously.
*
* Never call this twice on any device!
*
@ -757,6 +696,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags)
goto err_minors;
}
if (drm_core_check_feature(dev, DRIVER_MODESET))
drm_modeset_register_all(dev);
ret = 0;
goto out_unlock;
@ -787,6 +729,9 @@ void drm_dev_unregister(struct drm_device *dev)
drm_lastclose(dev);
if (drm_core_check_feature(dev, DRIVER_MODESET))
drm_modeset_unregister_all(dev);
if (dev->driver->unload)
dev->driver->unload(dev);
@ -804,26 +749,6 @@ void drm_dev_unregister(struct drm_device *dev)
}
EXPORT_SYMBOL(drm_dev_unregister);
/**
* drm_dev_set_unique - Set the unique name of a DRM device
* @dev: device of which to set the unique name
* @name: unique name
*
* Sets the unique name of a DRM device using the specified string. Drivers
* can use this at driver probe time if the unique name of the devices they
* drive is static.
*
* Return: 0 on success or a negative error code on failure.
*/
int drm_dev_set_unique(struct drm_device *dev, const char *name)
{
kfree(dev->unique);
dev->unique = kstrdup(name, GFP_KERNEL);
return dev->unique ? 0 : -ENOMEM;
}
EXPORT_SYMBOL(drm_dev_set_unique);
/*
* DRM Core
* The DRM core module initializes all global DRM objects and makes them

2
drivers/gpu/drm/drm_fb_helper.c
View File

@ -464,7 +464,7 @@ static bool drm_fb_helper_is_bound(struct drm_fb_helper *fb_helper)
/* Sometimes user space wants everything disabled, so don't steal the
* display if there's a master. */
if (dev->primary->master)
if (lockless_dereference(dev->master))
return false;
drm_for_each_crtc(crtc, dev) {

125
drivers/gpu/drm/drm_fops.c
View File

@ -40,6 +40,7 @@
#include <linux/module.h>
#include "drm_legacy.h"
#include "drm_internal.h"
#include "drm_crtc_internal.h"
/* from BKL pushdown */
DEFINE_MUTEX(drm_global_mutex);
@ -167,60 +168,6 @@ static int drm_cpu_valid(void)
return 1;
}
/*
* drm_new_set_master - Allocate a new master object and become master for the
* associated master realm.
*
* @dev: The associated device.
* @fpriv: File private identifying the client.
*
* This function must be called with dev::struct_mutex held.
* Returns negative error code on failure. Zero on success.
*/
int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv)
{
struct drm_master *old_master;
int ret;
lockdep_assert_held_once(&dev->master_mutex);
/* create a new master */
fpriv->minor->master = drm_master_create(fpriv->minor);
if (!fpriv->minor->master)
return -ENOMEM;
/* take another reference for the copy in the local file priv */
old_master = fpriv->master;
fpriv->master = drm_master_get(fpriv->minor->master);
if (dev->driver->master_create) {
ret = dev->driver->master_create(dev, fpriv->master);
if (ret)
goto out_err;
}
if (dev->driver->master_set) {
ret = dev->driver->master_set(dev, fpriv, true);
if (ret)
goto out_err;
}
fpriv->is_master = 1;
fpriv->allowed_master = 1;
fpriv->authenticated = 1;
if (old_master)
drm_master_put(&old_master);
return 0;
out_err:
/* drop both references and restore old master on failure */
drm_master_put(&fpriv->minor->master);
drm_master_put(&fpriv->master);
fpriv->master = old_master;
return ret;
}
/*
* Called whenever a process opens /dev/drm.
*
@ -283,19 +230,11 @@ static int drm_open_helper(struct file *filp, struct drm_minor *minor)
goto out_prime_destroy;
}
/* if there is no current master make this fd it, but do not create
* any master object for render clients */
mutex_lock(&dev->master_mutex);
if (drm_is_primary_client(priv) && !priv->minor->master) {
/* create a new master */
ret = drm_new_set_master(dev, priv);
if (drm_is_primary_client(priv)) {
ret = drm_master_open(priv);
if (ret)
goto out_close;
} else if (drm_is_primary_client(priv)) {
/* get a reference to the master */
priv->master = drm_master_get(priv->minor->master);
}
mutex_unlock(&dev->master_mutex);
mutex_lock(&dev->filelist_mutex);
list_add(&priv->lhead, &dev->filelist);
@ -324,7 +263,6 @@ static int drm_open_helper(struct file *filp, struct drm_minor *minor)
return 0;
out_close:
mutex_unlock(&dev->master_mutex);
if (dev->driver->postclose)
dev->driver->postclose(dev, priv);
out_prime_destroy:
@ -338,18 +276,6 @@ out_prime_destroy:
return ret;
}
static void drm_master_release(struct drm_device *dev, struct file *filp)
{
struct drm_file *file_priv = filp->private_data;
if (drm_legacy_i_have_hw_lock(dev, file_priv)) {
DRM_DEBUG("File %p released, freeing lock for context %d\n",
filp, _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
drm_legacy_lock_free(&file_priv->master->lock,
_DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
}
}
static void drm_events_release(struct drm_file *file_priv)
{
struct drm_device *dev = file_priv->minor->dev;
@ -451,11 +377,6 @@ int drm_release(struct inode *inode, struct file *filp)
list_del(&file_priv->lhead);
mutex_unlock(&dev->filelist_mutex);
mutex_lock(&dev->struct_mutex);
if (file_priv->magic)
idr_remove(&file_priv->master->magic_map, file_priv->magic);
mutex_unlock(&dev->struct_mutex);
if (dev->driver->preclose)
dev->driver->preclose(dev, file_priv);
@ -468,9 +389,8 @@ int drm_release(struct inode *inode, struct file *filp)
(long)old_encode_dev(file_priv->minor->kdev->devt),
dev->open_count);
/* if the master has gone away we can't do anything with the lock */
if (file_priv->minor->master)
drm_master_release(dev, filp);
if (!drm_core_check_feature(dev, DRIVER_MODESET))
drm_legacy_lock_release(dev, filp);
if (drm_core_check_feature(dev, DRIVER_HAVE_DMA))
drm_legacy_reclaim_buffers(dev, file_priv);
@ -487,43 +407,12 @@ int drm_release(struct inode *inode, struct file *filp)
drm_legacy_ctxbitmap_flush(dev, file_priv);
mutex_lock(&dev->master_mutex);
if (file_priv->is_master) {
struct drm_master *master = file_priv->master;
/*
* Since the master is disappearing, so is the
* possibility to lock.
*/
mutex_lock(&dev->struct_mutex);
if (master->lock.hw_lock) {
if (dev->sigdata.lock == master->lock.hw_lock)
dev->sigdata.lock = NULL;
master->lock.hw_lock = NULL;
master->lock.file_priv = NULL;
wake_up_interruptible_all(&master->lock.lock_queue);
}
mutex_unlock(&dev->struct_mutex);
if (file_priv->minor->master == file_priv->master) {
/* drop the reference held my the minor */
if (dev->driver->master_drop)
dev->driver->master_drop(dev, file_priv, true);
drm_master_put(&file_priv->minor->master);
}
}
/* drop the master reference held by the file priv */
if (file_priv->master)
drm_master_put(&file_priv->master);
file_priv->is_master = 0;
mutex_unlock(&dev->master_mutex);
if (drm_is_primary_client(file_priv))
drm_master_release(file_priv);
if (dev->driver->postclose)
dev->driver->postclose(dev, file_priv);
if (drm_core_check_feature(dev, DRIVER_PRIME))
drm_prime_destroy_file_private(&file_priv->prime);

115
drivers/gpu/drm/drm_info.c
View File

@ -50,106 +50,24 @@ int drm_name_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_minor *minor = node->minor;
struct drm_device *dev = minor->dev;
struct drm_master *master = minor->master;
struct drm_master *master;
mutex_lock(&dev->master_mutex);
master = dev->master;
if (!master)
return 0;
goto out_unlock;
if (master->unique) {
seq_printf(m, "%s %s %s\n",
dev->driver->name,
dev_name(dev->dev), master->unique);
} else {
seq_printf(m, "%s %s\n",
dev->driver->name, dev_name(dev->dev));
}
return 0;
}
/**
* Called when "/proc/dri/.../vm" is read.
*
* Prints information about all mappings in drm_device::maplist.
*/
int drm_vm_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct drm_local_map *map;
struct drm_map_list *r_list;
/* Hardcoded from _DRM_FRAME_BUFFER,
_DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and
_DRM_SCATTER_GATHER and _DRM_CONSISTENT */
const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" };
const char *type;
int i;
mutex_lock(&dev->struct_mutex);
seq_printf(m, "slot offset size type flags address mtrr\n\n");
i = 0;
list_for_each_entry(r_list, &dev->maplist, head) {
map = r_list->map;
if (!map)
continue;
if (map->type < 0 || map->type > 5)
type = "??";
else
type = types[map->type];
seq_printf(m, "%4d 0x%016llx 0x%08lx %4.4s 0x%02x 0x%08lx ",
i,
(unsigned long long)map->offset,
map->size, type, map->flags,
(unsigned long) r_list->user_token);
if (map->mtrr < 0)
seq_printf(m, "none\n");
else
seq_printf(m, "%4d\n", map->mtrr);
i++;
}
mutex_unlock(&dev->struct_mutex);
return 0;
}
/**
* Called when "/proc/dri/.../bufs" is read.
*/
int drm_bufs_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct drm_device_dma *dma;
int i, seg_pages;
mutex_lock(&dev->struct_mutex);
dma = dev->dma;
if (!dma) {
mutex_unlock(&dev->struct_mutex);
return 0;
}
seq_printf(m, " o size count free segs pages kB\n\n");
for (i = 0; i <= DRM_MAX_ORDER; i++) {
if (dma->bufs[i].buf_count) {
seg_pages = dma->bufs[i].seg_count * (1 << dma->bufs[i].page_order);
seq_printf(m, "%2d %8d %5d %5d %5d %5d %5ld\n",
i,
dma->bufs[i].buf_size,
dma->bufs[i].buf_count,
0,
dma->bufs[i].seg_count,
seg_pages,
seg_pages * PAGE_SIZE / 1024);
}
}
seq_printf(m, "%s", dev->driver->name);
if (dev->dev)
seq_printf(m, " dev=%s", dev_name(dev->dev));
if (master && master->unique)
seq_printf(m, " master=%s", master->unique);
if (dev->unique)
seq_printf(m, " unique=%s", dev->unique);
seq_printf(m, "\n");
for (i = 0; i < dma->buf_count; i++) {
if (i && !(i % 32))
seq_printf(m, "\n");
seq_printf(m, " %d", dma->buflist[i]->list);
}
seq_printf(m, "\n");
mutex_unlock(&dev->struct_mutex);
out_unlock:
mutex_unlock(&dev->master_mutex);
return 0;
}
@ -184,7 +102,7 @@ int drm_clients_info(struct seq_file *m, void *data)
task ? task->comm : "<unknown>",
pid_vnr(priv->pid),
priv->minor->index,
priv->is_master ? 'y' : 'n',
drm_is_current_master(priv) ? 'y' : 'n',
priv->authenticated ? 'y' : 'n',
from_kuid_munged(seq_user_ns(m), priv->uid),
priv->magic);
@ -194,7 +112,6 @@ int drm_clients_info(struct seq_file *m, void *data)
return 0;
}
static int drm_gem_one_name_info(int id, void *ptr, void *data)
{
struct drm_gem_object *obj = ptr;

21
drivers/gpu/drm/drm_internal.h
View File

@ -29,15 +29,9 @@ extern struct mutex drm_global_mutex;
void drm_lastclose(struct drm_device *dev);
/* drm_pci.c */
int drm_pci_set_unique(struct drm_device *dev,
struct drm_master *master,
struct drm_unique *u);
int drm_irq_by_busid(struct drm_device *dev, void *data,
struct drm_file *file_priv);
/* drm_vm.c */
int drm_vma_info(struct seq_file *m, void *data);
/* drm_prime.c */
int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
@ -51,8 +45,6 @@ void drm_prime_remove_buf_handle_locked(struct drm_prime_file_private *prime_fpr
/* drm_info.c */
int drm_name_info(struct seq_file *m, void *data);
int drm_vm_info(struct seq_file *m, void *data);
int drm_bufs_info(struct seq_file *m, void *data);
int drm_clients_info(struct seq_file *m, void* data);
int drm_gem_name_info(struct seq_file *m, void *data);
@ -67,6 +59,12 @@ int drm_getmagic(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_authmagic(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_setmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_master_open(struct drm_file *file_priv);
void drm_master_release(struct drm_file *file_priv);
/* drm_sysfs.c */
extern struct class *drm_class;
@ -92,13 +90,6 @@ int drm_gem_open_ioctl(struct drm_device *dev, void *data,
void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
/* drm_drv.c */
int drm_setmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int drm_dropmaster_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
struct drm_master *drm_master_create(struct drm_minor *minor);
/* drm_debugfs.c */
#if defined(CONFIG_DEBUG_FS)
int drm_debugfs_init(struct drm_minor *minor, int minor_id,

124
drivers/gpu/drm/drm_ioctl.c
View File

@ -30,6 +30,7 @@
#include <drm/drmP.h>
#include <drm/drm_core.h>
#include <drm/drm_auth.h>
#include "drm_legacy.h"
#include "drm_internal.h"
#include "drm_crtc_internal.h"
@ -37,6 +38,64 @@
#include <linux/pci.h>
#include <linux/export.h>
/**
* DOC: getunique and setversion story
*
* BEWARE THE DRAGONS! MIND THE TRAPDOORS!
*
* In an attempt to warn anyone else who's trying to figure out what's going
* on here, I'll try to summarize the story. First things first, let's clear up
* the names, because the kernel internals, libdrm and the ioctls are all named
* differently:
*
* - GET_UNIQUE ioctl, implemented by drm_getunique is wrapped up in libdrm
* through the drmGetBusid function.
* - The libdrm drmSetBusid function is backed by the SET_UNIQUE ioctl. All
* that code is nerved in the kernel with drm_invalid_op().
* - The internal set_busid kernel functions and driver callbacks are
* exclusively use by the SET_VERSION ioctl, because only drm 1.0 (which is
* nerved) allowed userspace to set the busid through the above ioctl.
* - Other ioctls and functions involved are named consistently.
*
* For anyone wondering what's the difference between drm 1.1 and 1.4: Correctly
* handling pci domains in the busid on ppc. Doing this correctly was only
* implemented in libdrm in 2010, hence can't be nerved yet. No one knows what's
* special with drm 1.2 and 1.3.
*
* Now the actual horror story of how device lookup in drm works. At large,
* there's 2 different ways, either by busid, or by device driver name.
*
* Opening by busid is fairly simple:
*
* 1. First call SET_VERSION to make sure pci domains are handled properly. As a
* side-effect this fills out the unique name in the master structure.
* 2. Call GET_UNIQUE to read out the unique name from the master structure,
* which matches the busid thanks to step 1. If it doesn't, proceed to try
* the next device node.
*
* Opening by name is slightly different:
*
* 1. Directly call VERSION to get the version and to match against the driver
* name returned by that ioctl. Note that SET_VERSION is not called, which
* means the the unique name for the master node just opening is _not_ filled
* out. This despite that with current drm device nodes are always bound to
* one device, and can't be runtime assigned like with drm 1.0.
* 2. Match driver name. If it mismatches, proceed to the next device node.
* 3. Call GET_UNIQUE, and check whether the unique name has length zero (by
* checking that the first byte in the string is 0). If that's not the case
* libdrm skips and proceeds to the next device node. Probably this is just
* copypasta from drm 1.0 times where a set unique name meant that the driver
* was in use already, but that's just conjecture.
*
* Long story short: To keep the open by name logic working, GET_UNIQUE must
* _not_ return a unique string when SET_VERSION hasn't been called yet,
* otherwise libdrm breaks. Even when that unique string can't ever change, and
* is totally irrelevant for actually opening the device because runtime
* assignable device instances were only support in drm 1.0, which is long dead.
* But the libdrm code in drmOpenByName somehow survived, hence this can't be
* broken.
*/
static int drm_version(struct drm_device *dev, void *data,
struct drm_file *file_priv);
@ -75,51 +134,6 @@ drm_unset_busid(struct drm_device *dev,
master->unique_len = 0;
}
/*
* Set the bus id.
*
* \param inode device inode.
* \param file_priv DRM file private.
* \param cmd command.
* \param arg user argument, pointing to a drm_unique structure.
* \return zero on success or a negative number on failure.
*
* Copies the bus id from userspace into drm_device::unique, and verifies that
* it matches the device this DRM is attached to (EINVAL otherwise). Deprecated
* in interface version 1.1 and will return EBUSY when setversion has requested
* version 1.1 or greater. Also note that KMS is all version 1.1 and later and
* UMS was only ever supported on pci devices.
*/
static int drm_setunique(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_unique *u = data;
struct drm_master *master = file_priv->master;
int ret;
if (master->unique_len || master->unique)
return -EBUSY;
if (!u->unique_len || u->unique_len > 1024)
return -EINVAL;
if (drm_core_check_feature(dev, DRIVER_MODESET))
return 0;
if (WARN_ON(!dev->pdev))
return -EINVAL;
ret = drm_pci_set_unique(dev, master, u);
if (ret)
goto err;
return 0;
err:
drm_unset_busid(dev, master);
return ret;
}
static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_master *master = file_priv->master;
@ -135,12 +149,7 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv)
return ret;
}
} else {
if (WARN(dev->unique == NULL,
"No drm_driver.set_busid() implementation provided by "
"%ps. Use drm_dev_set_unique() to set the unique "
"name explicitly.", dev->driver))
return -EINVAL;
WARN_ON(!dev->unique);
master->unique = kstrdup(dev->unique, GFP_KERNEL);
if (master->unique)
master->unique_len = strlen(dev->unique);
@ -473,7 +482,8 @@ int drm_ioctl_permit(u32 flags, struct drm_file *file_priv)
return -EACCES;
/* MASTER is only for master or control clients */
if (unlikely((flags & DRM_MASTER) && !file_priv->is_master &&
if (unlikely((flags & DRM_MASTER) &&
!drm_is_current_master(file_priv) &&
!drm_is_control_client(file_priv)))
return -EACCES;
@ -504,7 +514,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version,
DRM_UNLOCKED|DRM_RENDER_ALLOW|DRM_CONTROL_ALLOW),
DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),
DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),
DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_legacy_getmap_ioctl, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED),
@ -513,10 +523,10 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, 0),
DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER),
DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_UNLOCKED|DRM_MASTER),
DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_legacy_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_legacy_rmmap_ioctl, DRM_AUTH),
@ -524,8 +534,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_SET_SAREA_CTX, drm_legacy_setsareactx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_GET_SAREA_CTX, drm_legacy_getsareactx, DRM_AUTH),
DRM_IOCTL_DEF(DRM_IOCTL_SET_MASTER, drm_setmaster_ioctl, DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_DROP_MASTER, drm_dropmaster_ioctl, DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_SET_MASTER, drm_setmaster_ioctl, DRM_UNLOCKED|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_DROP_MASTER, drm_dropmaster_ioctl, DRM_UNLOCKED|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_legacy_addctx, DRM_AUTH|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_RM_CTX, drm_legacy_rmctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

4
drivers/gpu/drm/drm_irq.c
View File

@ -994,10 +994,10 @@ static void send_vblank_event(struct drm_device *dev,
e->event.tv_sec = now->tv_sec;
e->event.tv_usec = now->tv_usec;
drm_send_event_locked(dev, &e->base);
trace_drm_vblank_event_delivered(e->base.pid, e->pipe,
e->event.sequence);
drm_send_event_locked(dev, &e->base);
}
/**

8
drivers/gpu/drm/drm_legacy.h
View File

@ -88,14 +88,10 @@ struct drm_agp_mem {
struct list_head head;
};
/*
* Generic Userspace Locking-API
*/
int drm_legacy_i_have_hw_lock(struct drm_device *d, struct drm_file *f);
/* drm_lock.c */
int drm_legacy_lock(struct drm_device *d, void *v, struct drm_file *f);
int drm_legacy_unlock(struct drm_device *d, void *v, struct drm_file *f);
int drm_legacy_lock_free(struct drm_lock_data *lock, unsigned int ctx);
void drm_legacy_lock_release(struct drm_device *dev, struct file *filp);
/* DMA support */
int drm_legacy_dma_setup(struct drm_device *dev);

240
drivers/gpu/drm/drm_lock.c
View File

@ -40,6 +40,110 @@
static int drm_lock_take(struct drm_lock_data *lock_data, unsigned int context);
/**
* Take the heavyweight lock.
*
* \param lock lock pointer.
* \param context locking context.
* \return one if the lock is held, or zero otherwise.
*
* Attempt to mark the lock as held by the given context, via the \p cmpxchg instruction.
*/
static
int drm_lock_take(struct drm_lock_data *lock_data,
unsigned int context)
{
unsigned int old, new, prev;
volatile unsigned int *lock = &lock_data->hw_lock->lock;
spin_lock_bh(&lock_data->spinlock);
do {
old = *lock;
if (old & _DRM_LOCK_HELD)
new = old | _DRM_LOCK_CONT;
else {
new = context | _DRM_LOCK_HELD |
((lock_data->user_waiters + lock_data->kernel_waiters > 1) ?
_DRM_LOCK_CONT : 0);
}
prev = cmpxchg(lock, old, new);
} while (prev != old);
spin_unlock_bh(&lock_data->spinlock);
if (_DRM_LOCKING_CONTEXT(old) == context) {
if (old & _DRM_LOCK_HELD) {
if (context != DRM_KERNEL_CONTEXT) {
DRM_ERROR("%d holds heavyweight lock\n",
context);
}
return 0;
}
}
if ((_DRM_LOCKING_CONTEXT(new)) == context && (new & _DRM_LOCK_HELD)) {
/* Have lock */
return 1;
}
return 0;
}
/**
* This takes a lock forcibly and hands it to context. Should ONLY be used
* inside *_unlock to give lock to kernel before calling *_dma_schedule.
*
* \param dev DRM device.
* \param lock lock pointer.
* \param context locking context.
* \return always one.
*
* Resets the lock file pointer.
* Marks the lock as held by the given context, via the \p cmpxchg instruction.
*/
static int drm_lock_transfer(struct drm_lock_data *lock_data,
unsigned int context)
{
unsigned int old, new, prev;
volatile unsigned int *lock = &lock_data->hw_lock->lock;
lock_data->file_priv = NULL;
do {
old = *lock;
new = context | _DRM_LOCK_HELD;
prev = cmpxchg(lock, old, new);
} while (prev != old);
return 1;
}
static int drm_legacy_lock_free(struct drm_lock_data *lock_data,
unsigned int context)
{
unsigned int old, new, prev;
volatile unsigned int *lock = &lock_data->hw_lock->lock;
spin_lock_bh(&lock_data->spinlock);
if (lock_data->kernel_waiters != 0) {
drm_lock_transfer(lock_data, 0);
lock_data->idle_has_lock = 1;
spin_unlock_bh(&lock_data->spinlock);
return 1;
}
spin_unlock_bh(&lock_data->spinlock);
do {
old = *lock;
new = _DRM_LOCKING_CONTEXT(old);
prev = cmpxchg(lock, old, new);
} while (prev != old);
if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) {
DRM_ERROR("%d freed heavyweight lock held by %d\n",
context, _DRM_LOCKING_CONTEXT(old));
return 1;
}
wake_up_interruptible(&lock_data->lock_queue);
return 0;
}
/**
* Lock ioctl.
*
@ -115,7 +219,7 @@ int drm_legacy_lock(struct drm_device *dev, void *data,
/* don't set the block all signals on the master process for now
* really probably not the correct answer but lets us debug xkb
* xserver for now */
if (!file_priv->is_master) {
if (!drm_is_current_master(file_priv)) {
dev->sigdata.context = lock->context;
dev->sigdata.lock = master->lock.hw_lock;
}
@ -164,120 +268,6 @@ int drm_legacy_unlock(struct drm_device *dev, void *data, struct drm_file *file_
return 0;
}
/**
* Take the heavyweight lock.
*
* \param lock lock pointer.
* \param context locking context.
* \return one if the lock is held, or zero otherwise.
*
* Attempt to mark the lock as held by the given context, via the \p cmpxchg instruction.
*/
static
int drm_lock_take(struct drm_lock_data *lock_data,
unsigned int context)
{
unsigned int old, new, prev;
volatile unsigned int *lock = &lock_data->hw_lock->lock;
spin_lock_bh(&lock_data->spinlock);
do {
old = *lock;
if (old & _DRM_LOCK_HELD)
new = old | _DRM_LOCK_CONT;
else {
new = context | _DRM_LOCK_HELD |
((lock_data->user_waiters + lock_data->kernel_waiters > 1) ?
_DRM_LOCK_CONT : 0);
}
prev = cmpxchg(lock, old, new);
} while (prev != old);
spin_unlock_bh(&lock_data->spinlock);
if (_DRM_LOCKING_CONTEXT(old) == context) {
if (old & _DRM_LOCK_HELD) {
if (context != DRM_KERNEL_CONTEXT) {
DRM_ERROR("%d holds heavyweight lock\n",
context);
}
return 0;
}
}
if ((_DRM_LOCKING_CONTEXT(new)) == context && (new & _DRM_LOCK_HELD)) {
/* Have lock */
return 1;
}
return 0;
}
/**
* This takes a lock forcibly and hands it to context. Should ONLY be used
* inside *_unlock to give lock to kernel before calling *_dma_schedule.
*
* \param dev DRM device.
* \param lock lock pointer.
* \param context locking context.
* \return always one.
*
* Resets the lock file pointer.
* Marks the lock as held by the given context, via the \p cmpxchg instruction.
*/
static int drm_lock_transfer(struct drm_lock_data *lock_data,
unsigned int context)
{
unsigned int old, new, prev;
volatile unsigned int *lock = &lock_data->hw_lock->lock;
lock_data->file_priv = NULL;
do {
old = *lock;
new = context | _DRM_LOCK_HELD;
prev = cmpxchg(lock, old, new);
} while (prev != old);
return 1;
}
/**
* Free lock.
*
* \param dev DRM device.
* \param lock lock.
* \param context context.
*
* Resets the lock file pointer.
* Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task
* waiting on the lock queue.
*/
int drm_legacy_lock_free(struct drm_lock_data *lock_data, unsigned int context)
{
unsigned int old, new, prev;
volatile unsigned int *lock = &lock_data->hw_lock->lock;
spin_lock_bh(&lock_data->spinlock);
if (lock_data->kernel_waiters != 0) {
drm_lock_transfer(lock_data, 0);
lock_data->idle_has_lock = 1;
spin_unlock_bh(&lock_data->spinlock);
return 1;
}
spin_unlock_bh(&lock_data->spinlock);
do {
old = *lock;
new = _DRM_LOCKING_CONTEXT(old);
prev = cmpxchg(lock, old, new);
} while (prev != old);
if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) {
DRM_ERROR("%d freed heavyweight lock held by %d\n",
context, _DRM_LOCKING_CONTEXT(old));
return 1;
}
wake_up_interruptible(&lock_data->lock_queue);
return 0;
}
/**
* This function returns immediately and takes the hw lock
* with the kernel context if it is free, otherwise it gets the highest priority when and if
@ -330,11 +320,27 @@ void drm_legacy_idlelock_release(struct drm_lock_data *lock_data)
}
EXPORT_SYMBOL(drm_legacy_idlelock_release);
int drm_legacy_i_have_hw_lock(struct drm_device *dev,
struct drm_file *file_priv)
static int drm_legacy_i_have_hw_lock(struct drm_device *dev,
struct drm_file *file_priv)
{
struct drm_master *master = file_priv->master;
return (file_priv->lock_count && master->lock.hw_lock &&
_DRM_LOCK_IS_HELD(master->lock.hw_lock->lock) &&
master->lock.file_priv == file_priv);
}
void drm_legacy_lock_release(struct drm_device *dev, struct file *filp)
{
struct drm_file *file_priv = filp->private_data;
/* if the master has gone away we can't do anything with the lock */
if (!dev->master)
return;
if (drm_legacy_i_have_hw_lock(dev, file_priv)) {
DRM_DEBUG("File %p released, freeing lock for context %d\n",
filp, _DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
drm_legacy_lock_free(&file_priv->master->lock,
_DRM_LOCKING_CONTEXT(file_priv->master->lock.hw_lock->lock));
}
}

51
drivers/gpu/drm/drm_pci.c
View File

@ -144,50 +144,6 @@ int drm_pci_set_busid(struct drm_device *dev, struct drm_master *master)
}
EXPORT_SYMBOL(drm_pci_set_busid);
int drm_pci_set_unique(struct drm_device *dev,
struct drm_master *master,
struct drm_unique *u)
{
int domain, bus, slot, func, ret;
master->unique_len = u->unique_len;
master->unique = kmalloc(master->unique_len + 1, GFP_KERNEL);
if (!master->unique) {
ret = -ENOMEM;
goto err;
}
if (copy_from_user(master->unique, u->unique, master->unique_len)) {
ret = -EFAULT;
goto err;
}
master->unique[master->unique_len] = '\0';
/* Return error if the busid submitted doesn't match the device's actual
* busid.
*/
ret = sscanf(master->unique, "PCI:%d:%d:%d", &bus, &slot, &func);
if (ret != 3) {
ret = -EINVAL;
goto err;
}
domain = bus >> 8;
bus &= 0xff;
if ((domain != drm_get_pci_domain(dev)) ||
(bus != dev->pdev->bus->number) ||
(slot != PCI_SLOT(dev->pdev->devfn)) ||
(func != PCI_FUNC(dev->pdev->devfn))) {
ret = -EINVAL;
goto err;
}
return 0;
err:
return ret;
}
static int drm_pci_irq_by_busid(struct drm_device *dev, struct drm_irq_busid *p)
{
if ((p->busnum >> 8) != drm_get_pci_domain(dev) ||
@ -444,13 +400,6 @@ int drm_irq_by_busid(struct drm_device *dev, void *data,
{
return -EINVAL;
}
int drm_pci_set_unique(struct drm_device *dev,
struct drm_master *master,
struct drm_unique *u)
{
return -EINVAL;
}
#endif
EXPORT_SYMBOL(drm_pci_init);

28
drivers/gpu/drm/drm_plane_helper.c
View File

@ -115,6 +115,7 @@ static int get_connectors_for_crtc(struct drm_crtc *crtc,
* @src: source coordinates in 16.16 fixed point
* @dest: integer destination coordinates
* @clip: integer clipping coordinates
* @rotation: plane rotation
* @min_scale: minimum @src:@dest scaling factor in 16.16 fixed point
* @max_scale: maximum @src:@dest scaling factor in 16.16 fixed point
* @can_position: is it legal to position the plane such that it
@ -134,16 +135,17 @@ static int get_connectors_for_crtc(struct drm_crtc *crtc,
* Zero if update appears valid, error code on failure
*/
int drm_plane_helper_check_update(struct drm_plane *plane,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_rect *src,
struct drm_rect *dest,
const struct drm_rect *clip,
int min_scale,
int max_scale,
bool can_position,
bool can_update_disabled,
bool *visible)
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_rect *src,
struct drm_rect *dest,
const struct drm_rect *clip,
unsigned int rotation,
int min_scale,
int max_scale,
bool can_position,
bool can_update_disabled,
bool *visible)
{
int hscale, vscale;
@ -163,6 +165,8 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
return -EINVAL;
}
drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
/* Check scaling */
hscale = drm_rect_calc_hscale(src, dest, min_scale, max_scale);
vscale = drm_rect_calc_vscale(src, dest, min_scale, max_scale);
@ -174,6 +178,9 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
}
*visible = drm_rect_clip_scaled(src, dest, clip, hscale, vscale);
drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
if (!*visible)
/*
* Plane isn't visible; some drivers can handle this
@ -267,6 +274,7 @@ int drm_primary_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
ret = drm_plane_helper_check_update(plane, crtc, fb,
&src, &dest, &clip,
BIT(DRM_ROTATE_0),
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
false, false, &visible);

18
drivers/gpu/drm/drm_platform.c
View File

@ -68,24 +68,6 @@ err_free:
return ret;
}
int drm_platform_set_busid(struct drm_device *dev, struct drm_master *master)
{
int id;
id = dev->platformdev->id;
if (id < 0)
id = 0;
master->unique = kasprintf(GFP_KERNEL, "platform:%s:%02d",
dev->platformdev->name, id);
if (!master->unique)
return -ENOMEM;
master->unique_len = strlen(master->unique);
return 0;
}
EXPORT_SYMBOL(drm_platform_set_busid);
/**
* drm_platform_init - Register a platform device with the DRM subsystem
* @driver: DRM device driver

1
drivers/gpu/drm/drm_simple_kms_helper.c
View File

@ -105,6 +105,7 @@ static int drm_simple_kms_plane_atomic_check(struct drm_plane *plane,
ret = drm_plane_helper_check_update(plane, &pipe->crtc,
plane_state->fb,
&src, &dest, &clip,
plane_state->rotation,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
false, true, &visible);

54
drivers/gpu/drm/drm_vm.c
View File

@ -670,57 +670,3 @@ void drm_legacy_vma_flush(struct drm_device *dev)
kfree(vma);
}
}
int drm_vma_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct drm_vma_entry *pt;
struct vm_area_struct *vma;
unsigned long vma_count = 0;
#if defined(__i386__)
unsigned int pgprot;
#endif
mutex_lock(&dev->struct_mutex);
list_for_each_entry(pt, &dev->vmalist, head)
vma_count++;
seq_printf(m, "vma use count: %lu, high_memory = %pK, 0x%pK\n",
vma_count, high_memory,
(void *)(unsigned long)virt_to_phys(high_memory));
list_for_each_entry(pt, &dev->vmalist, head) {
vma = pt->vma;
if (!vma)
continue;
seq_printf(m,
"\n%5d 0x%pK-0x%pK %c%c%c%c%c%c 0x%08lx000",
pt->pid,
(void *)vma->vm_start, (void *)vma->vm_end,
vma->vm_flags & VM_READ ? 'r' : '-',
vma->vm_flags & VM_WRITE ? 'w' : '-',
vma->vm_flags & VM_EXEC ? 'x' : '-',
vma->vm_flags & VM_MAYSHARE ? 's' : 'p',
vma->vm_flags & VM_LOCKED ? 'l' : '-',
vma->vm_flags & VM_IO ? 'i' : '-',
vma->vm_pgoff);
#if defined(__i386__)
pgprot = pgprot_val(vma->vm_page_prot);
seq_printf(m, " %c%c%c%c%c%c%c%c%c",
pgprot & _PAGE_PRESENT ? 'p' : '-',
pgprot & _PAGE_RW ? 'w' : 'r',
pgprot & _PAGE_USER ? 'u' : 's',
pgprot & _PAGE_PWT ? 't' : 'b',
pgprot & _PAGE_PCD ? 'u' : 'c',
pgprot & _PAGE_ACCESSED ? 'a' : '-',
pgprot & _PAGE_DIRTY ? 'd' : '-',
pgprot & _PAGE_PSE ? 'm' : 'k',
pgprot & _PAGE_GLOBAL ? 'g' : 'l');
#endif
seq_printf(m, "\n");
}
mutex_unlock(&dev->struct_mutex);
return 0;
}

1
drivers/gpu/drm/etnaviv/etnaviv_drv.c
View File

@ -496,7 +496,6 @@ static struct drm_driver etnaviv_drm_driver = {
DRIVER_RENDER,
.open = etnaviv_open,
.preclose = etnaviv_preclose,
.set_busid = drm_platform_set_busid,
.gem_free_object_unlocked = etnaviv_gem_free_object,
.gem_vm_ops = &vm_ops,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,

1
drivers/gpu/drm/exynos/exynos_drm_drv.c
View File

@ -407,7 +407,6 @@ static struct drm_driver exynos_drm_driver = {
.preclose = exynos_drm_preclose,
.lastclose = exynos_drm_lastclose,
.postclose = exynos_drm_postclose,
.set_busid = drm_platform_set_busid,
.get_vblank_counter = drm_vblank_no_hw_counter,
.enable_vblank = exynos_drm_crtc_enable_vblank,
.disable_vblank = exynos_drm_crtc_disable_vblank,

13
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
View File

@ -37,23 +37,22 @@ int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
ret = fsl_dcu_drm_crtc_create(fsl_dev);
if (ret)
return ret;
goto err;
ret = fsl_dcu_drm_encoder_create(fsl_dev, &fsl_dev->crtc);
if (ret)
goto fail_encoder;
goto err;
ret = fsl_dcu_drm_connector_create(fsl_dev, &fsl_dev->encoder);
if (ret)
goto fail_connector;
goto err;
drm_mode_config_reset(fsl_dev->drm);
drm_kms_helper_poll_init(fsl_dev->drm);
return 0;
fail_encoder:
fsl_dev->crtc.funcs->destroy(&fsl_dev->crtc);
fail_connector:
fsl_dev->encoder.funcs->destroy(&fsl_dev->encoder);
err:
drm_mode_config_cleanup(fsl_dev->drm);
return ret;
}

9
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
View File

@ -171,7 +171,6 @@ static struct drm_driver kirin_drm_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
DRIVER_ATOMIC | DRIVER_HAVE_IRQ,
.fops = &kirin_drm_fops,
.set_busid = drm_platform_set_busid,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
@ -221,19 +220,12 @@ static int kirin_drm_bind(struct device *dev)
if (ret)
goto err_kms_cleanup;
/* connectors should be registered after drm device register */
ret = drm_connector_register_all(drm_dev);
if (ret)
goto err_drm_dev_unregister;
DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
driver->name, driver->major, driver->minor, driver->patchlevel,
driver->date, drm_dev->primary->index);
return 0;
err_drm_dev_unregister:
drm_dev_unregister(drm_dev);
err_kms_cleanup:
kirin_drm_kms_cleanup(drm_dev);
err_drm_dev_unref:
@ -246,7 +238,6 @@ static void kirin_drm_unbind(struct device *dev)
{
struct drm_device *drm_dev = dev_get_drvdata(dev);
drm_connector_unregister_all(drm_dev);
drm_dev_unregister(drm_dev);
kirin_drm_kms_cleanup(drm_dev);
drm_dev_unref(drm_dev);

3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -47,6 +47,7 @@
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
#include <drm/drm_auth.h>
#include "i915_params.h"
#include "i915_reg.h"
@ -3728,7 +3729,7 @@ extern void intel_modeset_init_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
extern void intel_connector_unregister(struct intel_connector *);
extern void intel_connector_unregister(struct drm_connector *);
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
extern void intel_display_resume(struct drm_device *dev);
extern void i915_redisable_vga(struct drm_device *dev);

4
drivers/gpu/drm/i915/i915_gem_execbuffer.c
View File

@ -1446,7 +1446,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
dispatch_flags = 0;
if (args->flags & I915_EXEC_SECURE) {
if (!file->is_master || !capable(CAP_SYS_ADMIN))
if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
return -EPERM;
dispatch_flags |= I915_DISPATCH_SECURE;
@ -1553,7 +1553,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
batch_obj,
args->batch_start_offset,
args->batch_len,
file->is_master);
drm_is_current_master(file));
if (IS_ERR(parsed_batch_obj)) {
ret = PTR_ERR(parsed_batch_obj);
goto err;

2
drivers/gpu/drm/i915/intel_crt.c
View File

@ -743,6 +743,7 @@ static const struct drm_connector_funcs intel_crt_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = intel_crt_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.early_unregister = intel_connector_unregister,
.destroy = intel_crt_destroy,
.set_property = intel_crt_set_property,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
@ -875,7 +876,6 @@ void intel_crt_init(struct drm_device *dev)
crt->base.get_hw_state = intel_crt_get_hw_state;
}
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);

15
drivers/gpu/drm/i915/intel_display.c
View File

@ -14184,6 +14184,7 @@ intel_check_primary_plane(struct drm_plane *plane,
return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
&state->dst, &state->clip,
state->base.rotation,
min_scale, max_scale,
can_position, true,
&state->visible);
@ -14375,6 +14376,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
&state->dst, &state->clip,
state->base.rotation,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
true, true, &state->visible);
@ -16316,23 +16318,20 @@ void intel_modeset_gem_init(struct drm_device *dev)
intel_backlight_register(dev);
}
void intel_connector_unregister(struct intel_connector *intel_connector)
void intel_connector_unregister(struct drm_connector *connector)
{
struct drm_connector *connector = &intel_connector->base;
struct intel_connector *intel_connector = to_intel_connector(connector);
intel_backlight_device_unregister(intel_connector);
intel_panel_destroy_backlight(connector);
drm_connector_unregister(connector);
}
void intel_modeset_cleanup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_connector *connector;
intel_disable_gt_powersave(dev_priv);
intel_backlight_unregister(dev);
/*
* Interrupts and polling as the first thing to avoid creating havoc.
* Too much stuff here (turning of connectors, ...) would
@ -16353,9 +16352,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
/* flush any delayed tasks or pending work */
flush_scheduled_work();
/* destroy the backlight and sysfs files before encoders/connectors */
for_each_intel_connector(dev, connector)
connector->unregister(connector);
drm_connector_unregister_all(dev);
drm_mode_config_cleanup(dev);

22
drivers/gpu/drm/i915/intel_dp.c
View File

@ -1246,7 +1246,6 @@ static void intel_aux_reg_init(struct intel_dp *intel_dp)
static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
drm_dp_aux_unregister(&intel_dp->aux);
kfree(intel_dp->aux.name);
}
@ -1281,15 +1280,6 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
return 0;
}
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
intel_dp_aux_fini(intel_dp);
intel_connector_unregister(intel_connector);
}
static int
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
{
@ -4530,6 +4520,13 @@ done:
return 0;
}
static void
intel_dp_connector_unregister(struct drm_connector *connector)
{
drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
intel_connector_unregister(connector);
}
static void
intel_dp_connector_destroy(struct drm_connector *connector)
{
@ -4570,6 +4567,9 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
intel_dp->edp_notifier.notifier_call = NULL;
}
}
intel_dp_aux_fini(intel_dp);
drm_encoder_cleanup(encoder);
kfree(intel_dig_port);
}
@ -4648,6 +4648,7 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_dp_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
.early_unregister = intel_dp_connector_unregister,
.destroy = intel_dp_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
@ -5583,7 +5584,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
else
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_dp_connector_unregister;
/* Set up the hotplug pin. */
switch (port) {

4
drivers/gpu/drm/i915/intel_dp_mst.c
View File

@ -336,6 +336,7 @@ static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_dp_mst_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
.early_unregister = intel_connector_unregister,
.destroy = intel_dp_mst_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
@ -455,7 +456,6 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
intel_connector->unregister = intel_connector_unregister;
intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
intel_connector->mst_port = intel_dp;
intel_connector->port = port;
@ -489,7 +489,7 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_device *dev = connector->dev;
intel_connector->unregister(intel_connector);
drm_connector_unregister(connector);
/* need to nuke the connector */
drm_modeset_lock_all(dev);

17
drivers/gpu/drm/i915/intel_drv.h
View File

@ -243,14 +243,6 @@ struct intel_connector {
* and active (i.e. dpms ON state). */
bool (*get_hw_state)(struct intel_connector *);
/*
* Removes all interfaces through which the connector is accessible
* - like sysfs, debugfs entries -, so that no new operations can be
* started on the connector. Also makes sure all currently pending
* operations finish before returing.
*/
void (*unregister)(struct intel_connector *);
/* Panel info for eDP and LVDS */
struct intel_panel panel;
@ -1514,7 +1506,14 @@ extern struct drm_display_mode *intel_find_panel_downclock(
struct drm_display_mode *fixed_mode,
struct drm_connector *connector);
void intel_backlight_register(struct drm_device *dev);
void intel_backlight_unregister(struct drm_device *dev);
#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
void intel_backlight_device_unregister(struct intel_connector *connector);
#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
static inline void intel_backlight_device_unregister(struct intel_connector *connector)
{
}
#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
/* intel_psr.c */

2
drivers/gpu/drm/i915/intel_dsi.c
View File

@ -1390,6 +1390,7 @@ static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
static const struct drm_connector_funcs intel_dsi_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = intel_dsi_detect,
.early_unregister = intel_connector_unregister,
.destroy = intel_dsi_connector_destroy,
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_dsi_set_property,
@ -1466,7 +1467,6 @@ void intel_dsi_init(struct drm_device *dev)
intel_encoder->get_config = intel_dsi_get_config;
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
/*
* On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI

2
drivers/gpu/drm/i915/intel_dvo.c
View File

@ -341,6 +341,7 @@ static void intel_dvo_destroy(struct drm_connector *connector)
static const struct drm_connector_funcs intel_dvo_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = intel_dvo_detect,
.early_unregister = intel_connector_unregister,
.destroy = intel_dvo_destroy,
.fill_modes = drm_helper_probe_single_connector_modes,
.atomic_get_property = intel_connector_atomic_get_property,
@ -447,7 +448,6 @@ void intel_dvo_init(struct drm_device *dev)
intel_encoder->compute_config = intel_dvo_compute_config;
intel_encoder->pre_enable = intel_dvo_pre_enable;
intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
/* Now, try to find a controller */
for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {

2
drivers/gpu/drm/i915/intel_hdmi.c
View File

@ -1774,6 +1774,7 @@ static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_hdmi_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
.early_unregister = intel_connector_unregister,
.destroy = intel_hdmi_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
@ -1909,7 +1910,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
else
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
intel_hdmi_add_properties(intel_hdmi, connector);

2
drivers/gpu/drm/i915/intel_lvds.c
View File

@ -555,6 +555,7 @@ static const struct drm_connector_funcs intel_lvds_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_lvds_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
.early_unregister = intel_connector_unregister,
.destroy = intel_lvds_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
@ -993,7 +994,6 @@ void intel_lvds_init(struct drm_device *dev)
intel_encoder->get_hw_state = intel_lvds_get_hw_state;
intel_encoder->get_config = intel_lvds_get_config;
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
intel_connector_attach_encoder(intel_connector, intel_encoder);
intel_encoder->type = INTEL_OUTPUT_LVDS;

13
drivers/gpu/drm/i915/intel_panel.c
View File

@ -1216,7 +1216,7 @@ static int intel_backlight_device_register(struct intel_connector *connector)
return 0;
}
static void intel_backlight_device_unregister(struct intel_connector *connector)
void intel_backlight_device_unregister(struct intel_connector *connector)
{
struct intel_panel *panel = &connector->panel;
@ -1230,9 +1230,6 @@ static int intel_backlight_device_register(struct intel_connector *connector)
{
return 0;
}
static void intel_backlight_device_unregister(struct intel_connector *connector)
{
}
#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
/*
@ -1820,11 +1817,3 @@ void intel_backlight_register(struct drm_device *dev)
for_each_intel_connector(dev, connector)
intel_backlight_device_register(connector);
}
void intel_backlight_unregister(struct drm_device *dev)
{
struct intel_connector *connector;
for_each_intel_connector(dev, connector)
intel_backlight_device_unregister(connector);
}

26
drivers/gpu/drm/i915/intel_sdvo.c
View File

@ -2177,12 +2177,23 @@ done:
#undef CHECK_PROPERTY
}
static void
intel_sdvo_connector_unregister(struct drm_connector *connector)
{
struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
sysfs_remove_link(&connector->kdev->kobj,
sdvo->ddc.dev.kobj.name);
intel_connector_unregister(connector);
}
static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = intel_sdvo_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_sdvo_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
.early_unregister = intel_sdvo_connector_unregister,
.destroy = intel_sdvo_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
@ -2345,20 +2356,6 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
return 0x72;
}
static void
intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
{
struct drm_connector *drm_connector;
struct intel_sdvo *sdvo_encoder;
drm_connector = &intel_connector->base;
sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
sysfs_remove_link(&drm_connector->kdev->kobj,
sdvo_encoder->ddc.dev.kobj.name);
intel_connector_unregister(intel_connector);
}
static int
intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
struct intel_sdvo *encoder)
@ -2381,7 +2378,6 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
connector->base.base.doublescan_allowed = 0;
connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
connector->base.unregister = intel_sdvo_connector_unregister;
intel_connector_attach_encoder(&connector->base, &encoder->base);
ret = drm_connector_register(drm_connector);

2
drivers/gpu/drm/i915/intel_tv.c
View File

@ -1501,6 +1501,7 @@ out:
static const struct drm_connector_funcs intel_tv_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = intel_tv_detect,
.early_unregister = intel_connector_unregister,
.destroy = intel_tv_destroy,
.set_property = intel_tv_set_property,
.atomic_get_property = intel_connector_atomic_get_property,
@ -1599,7 +1600,6 @@ intel_tv_init(struct drm_device *dev)
intel_encoder->disable = intel_disable_tv;
intel_encoder->get_hw_state = intel_tv_get_hw_state;
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
intel_connector_attach_encoder(intel_connector, intel_encoder);
intel_encoder->type = INTEL_OUTPUT_TVOUT;

1
drivers/gpu/drm/imx/imx-drm-core.c
View File

@ -407,7 +407,6 @@ static struct drm_driver imx_drm_driver = {
.load = imx_drm_driver_load,
.unload = imx_drm_driver_unload,
.lastclose = imx_drm_driver_lastclose,
.set_busid = drm_platform_set_busid,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = drm_gem_cma_dumb_create,

9
drivers/gpu/drm/mediatek/Kconfig
View File

@ -6,7 +6,6 @@ config DRM_MEDIATEK
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL
select IOMMU_DMA
select MEMORY
select MTK_SMI
help
@ -14,3 +13,11 @@ config DRM_MEDIATEK
The module will be called mediatek-drm
This driver provides kernel mode setting and
buffer management to userspace.
config DRM_MEDIATEK_HDMI
tristate "DRM HDMI Support for Mediatek SoCs"
depends on DRM_MEDIATEK
select SND_SOC_HDMI_CODEC if SND_SOC
select GENERIC_PHY
help
DRM/KMS HDMI driver for Mediatek SoCs

7
drivers/gpu/drm/mediatek/Makefile
View File

@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \
mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
mediatek-drm-hdmi-objs := mtk_cec.o \
mtk_hdmi.o \
mtk_hdmi_ddc.o \
mtk_mt8173_hdmi_phy.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o

265
drivers/gpu/drm/mediatek/mtk_cec.c Normal file
View File

@ -0,0 +1,265 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include "mtk_cec.h"
#define TR_CONFIG 0x00
#define CLEAR_CEC_IRQ BIT(15)
#define CEC_CKGEN 0x04
#define CEC_32K_PDN BIT(19)
#define PDN BIT(16)
#define RX_EVENT 0x54
#define HDMI_PORD BIT(25)
#define HDMI_HTPLG BIT(24)
#define HDMI_PORD_INT_EN BIT(9)
#define HDMI_HTPLG_INT_EN BIT(8)
#define RX_GEN_WD 0x58
#define HDMI_PORD_INT_32K_STATUS BIT(26)
#define RX_RISC_INT_32K_STATUS BIT(25)
#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
#define HDMI_PORD_INT_32K_CLR BIT(18)
#define RX_INT_32K_CLR BIT(17)
#define HDMI_HTPLG_INT_32K_CLR BIT(16)
#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
#define RX_RISC_INT_32K_STA_MASK BIT(9)
#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
#define HDMI_PORD_INT_32K_EN BIT(2)
#define RX_INT_32K_EN BIT(1)
#define HDMI_HTPLG_INT_32K_EN BIT(0)
#define NORMAL_INT_CTRL 0x5C
#define HDMI_HTPLG_INT_STA BIT(0)
#define HDMI_PORD_INT_STA BIT(1)
#define HDMI_HTPLG_INT_CLR BIT(16)
#define HDMI_PORD_INT_CLR BIT(17)
#define HDMI_FULL_INT_CLR BIT(20)
struct mtk_cec {
void __iomem *regs;
struct clk *clk;
int irq;
bool hpd;
void (*hpd_event)(bool hpd, struct device *dev);
struct device *hdmi_dev;
spinlock_t lock;
};
static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
unsigned int bits)
{
void __iomem *reg = cec->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp &= ~bits;
writel(tmp, reg);
}
static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
unsigned int bits)
{
void __iomem *reg = cec->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp |= bits;
writel(tmp, reg);
}
static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
unsigned int val, unsigned int mask)
{
u32 tmp = readl(cec->regs + offset) & ~mask;
tmp |= val & mask;
writel(val, cec->regs + offset);
}
void mtk_cec_set_hpd_event(struct device *dev,
void (*hpd_event)(bool hpd, struct device *dev),
struct device *hdmi_dev)
{
struct mtk_cec *cec = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&cec->lock, flags);
cec->hdmi_dev = hdmi_dev;
cec->hpd_event = hpd_event;
spin_unlock_irqrestore(&cec->lock, flags);
}
bool mtk_cec_hpd_high(struct device *dev)
{
struct mtk_cec *cec = dev_get_drvdata(dev);
unsigned int status;
status = readl(cec->regs + RX_EVENT);
return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
}
static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
{
mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
}
static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
{
mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
}
static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
{
mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
}
static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
{
mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
usleep_range(5, 10);
mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
}
static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
{
void (*hpd_event)(bool hpd, struct device *dev);
struct device *hdmi_dev;
unsigned long flags;
spin_lock_irqsave(&cec->lock, flags);
hpd_event = cec->hpd_event;
hdmi_dev = cec->hdmi_dev;
spin_unlock_irqrestore(&cec->lock, flags);
if (hpd_event)
hpd_event(hpd, hdmi_dev);
}
static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
{
struct device *dev = arg;
struct mtk_cec *cec = dev_get_drvdata(dev);
bool hpd;
mtk_cec_clear_htplg_irq(cec);
hpd = mtk_cec_hpd_high(dev);
if (cec->hpd != hpd) {
dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
cec->hpd, hpd);
cec->hpd = hpd;
mtk_cec_hpd_event(cec, hpd);
}
return IRQ_HANDLED;
}
static int mtk_cec_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_cec *cec;
struct resource *res;
int ret;
cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
if (!cec)
return -ENOMEM;
platform_set_drvdata(pdev, cec);
spin_lock_init(&cec->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
cec->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(cec->regs)) {
ret = PTR_ERR(cec->regs);
dev_err(dev, "Failed to ioremap cec: %d\n", ret);
return ret;
}
cec->clk = devm_clk_get(dev, NULL);
if (IS_ERR(cec->clk)) {
ret = PTR_ERR(cec->clk);
dev_err(dev, "Failed to get cec clock: %d\n", ret);
return ret;
}
cec->irq = platform_get_irq(pdev, 0);
if (cec->irq < 0) {
dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);
return cec->irq;
}
ret = devm_request_threaded_irq(dev, cec->irq, NULL,
mtk_cec_htplg_isr_thread,
IRQF_SHARED | IRQF_TRIGGER_LOW |
IRQF_ONESHOT, "hdmi hpd", dev);
if (ret) {
dev_err(dev, "Failed to register cec irq: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(cec->clk);
if (ret) {
dev_err(dev, "Failed to enable cec clock: %d\n", ret);
return ret;
}
mtk_cec_htplg_irq_init(cec);
mtk_cec_htplg_irq_enable(cec);
return 0;
}
static int mtk_cec_remove(struct platform_device *pdev)
{
struct mtk_cec *cec = platform_get_drvdata(pdev);
mtk_cec_htplg_irq_disable(cec);
clk_disable_unprepare(cec->clk);
return 0;
}
static const struct of_device_id mtk_cec_of_ids[] = {
{ .compatible = "mediatek,mt8173-cec", },
{}
};
struct platform_driver mtk_cec_driver = {
.probe = mtk_cec_probe,
.remove = mtk_cec_remove,
.driver = {
.name = "mediatek-cec",
.of_match_table = mtk_cec_of_ids,
},
};

26
drivers/gpu/drm/mediatek/mtk_cec.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_CEC_H
#define _MTK_CEC_H
#include <linux/types.h>
struct device;
void mtk_cec_set_hpd_event(struct device *dev,
void (*hotplug_event)(bool hpd, struct device *dev),
struct device *hdmi_dev);
bool mtk_cec_hpd_high(struct device *dev);
#endif /* _MTK_CEC_H */

9
drivers/gpu/drm/mediatek/mtk_drm_drv.c
View File

@ -280,8 +280,6 @@ static int mtk_drm_bind(struct device *dev)
if (!drm)
return -ENOMEM;
drm_dev_set_unique(drm, dev_name(dev));
drm->dev_private = private;
private->drm = drm;
@ -293,14 +291,8 @@ static int mtk_drm_bind(struct device *dev)
if (ret < 0)
goto err_deinit;
ret = drm_connector_register_all(drm);
if (ret < 0)
goto err_unregister;
return 0;
err_unregister:
drm_dev_unregister(drm);
err_deinit:
mtk_drm_kms_deinit(drm);
err_free:
@ -455,7 +447,6 @@ static int mtk_drm_remove(struct platform_device *pdev)
struct drm_device *drm = private->drm;
int i;
drm_connector_unregister_all(drm);
drm_dev_unregister(drm);
mtk_drm_kms_deinit(drm);
drm_dev_unref(drm);

1
drivers/gpu/drm/mediatek/mtk_drm_plane.c
View File

@ -170,6 +170,7 @@ static int mtk_plane_atomic_check(struct drm_plane *plane,
return drm_plane_helper_check_update(plane, state->crtc, fb,
&src, &dest, &clip,
state->rotation,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
true, true, &visible);

1828
drivers/gpu/drm/mediatek/mtk_hdmi.c Normal file
View File

File diff suppressed because it is too large Load Diff

23
drivers/gpu/drm/mediatek/mtk_hdmi.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_HDMI_CTRL_H
#define _MTK_HDMI_CTRL_H
struct platform_driver;
extern struct platform_driver mtk_cec_driver;
extern struct platform_driver mtk_hdmi_ddc_driver;
extern struct platform_driver mtk_hdmi_phy_driver;
#endif /* _MTK_HDMI_CTRL_H */

358
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c Normal file
View File

@ -0,0 +1,358 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#define SIF1_CLOK (288)
#define DDC_DDCMCTL0 (0x0)
#define DDCM_ODRAIN BIT(31)
#define DDCM_CLK_DIV_OFFSET (16)
#define DDCM_CLK_DIV_MASK (0xfff << 16)
#define DDCM_CS_STATUS BIT(4)
#define DDCM_SCL_STATE BIT(3)
#define DDCM_SDA_STATE BIT(2)
#define DDCM_SM0EN BIT(1)
#define DDCM_SCL_STRECH BIT(0)
#define DDC_DDCMCTL1 (0x4)
#define DDCM_ACK_OFFSET (16)
#define DDCM_ACK_MASK (0xff << 16)
#define DDCM_PGLEN_OFFSET (8)
#define DDCM_PGLEN_MASK (0x7 << 8)
#define DDCM_SIF_MODE_OFFSET (4)
#define DDCM_SIF_MODE_MASK (0x7 << 4)
#define DDCM_START (0x1)
#define DDCM_WRITE_DATA (0x2)
#define DDCM_STOP (0x3)
#define DDCM_READ_DATA_NO_ACK (0x4)
#define DDCM_READ_DATA_ACK (0x5)
#define DDCM_TRI BIT(0)
#define DDC_DDCMD0 (0x8)
#define DDCM_DATA3 (0xff << 24)
#define DDCM_DATA2 (0xff << 16)
#define DDCM_DATA1 (0xff << 8)
#define DDCM_DATA0 (0xff << 0)
#define DDC_DDCMD1 (0xc)
#define DDCM_DATA7 (0xff << 24)
#define DDCM_DATA6 (0xff << 16)
#define DDCM_DATA5 (0xff << 8)
#define DDCM_DATA4 (0xff << 0)
struct mtk_hdmi_ddc {
struct i2c_adapter adap;
struct clk *clk;
void __iomem *regs;
};
static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int val)
{
writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
}
static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int val)
{
writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
}
static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int val)
{
return (readl(ddc->regs + offset) & val) == val;
}
static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
unsigned int mask, unsigned int shift,
unsigned int val)
{
unsigned int tmp;
tmp = readl(ddc->regs + offset);
tmp &= ~mask;
tmp |= (val << shift) & mask;
writel(tmp, ddc->regs + offset);
}
static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
unsigned int offset, unsigned int mask,
unsigned int shift)
{
return (readl(ddc->regs + offset) & mask) >> shift;
}
static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
{
u32 val;
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
DDCM_SIF_MODE_OFFSET, mode);
sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
(val & DDCM_TRI) != DDCM_TRI, 4, 20000);
}
static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
{
struct device *dev = ddc->adap.dev.parent;
u32 remain_count, ack_count, ack_final, read_count, temp_count;
u32 index = 0;
u32 ack;
int i;
ddcm_trigger_mode(ddc, DDCM_START);
sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
0x00);
ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
dev_dbg(dev, "ack = 0x%x\n", ack);
if (ack != 0x01) {
dev_err(dev, "i2c ack err!\n");
return -ENXIO;
}
remain_count = msg->len;
ack_count = (msg->len - 1) / 8;
ack_final = 0;
while (remain_count > 0) {
if (ack_count > 0) {
read_count = 8;
ack_final = 0;
ack_count--;
} else {
read_count = remain_count;
ack_final = 1;
}
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
DDCM_PGLEN_OFFSET, read_count - 1);
ddcm_trigger_mode(ddc, (ack_final == 1) ?
DDCM_READ_DATA_NO_ACK :
DDCM_READ_DATA_ACK);
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
DDCM_ACK_OFFSET);
temp_count = 0;
while (((ack & (1 << temp_count)) != 0) && (temp_count < 8))
temp_count++;
if (((ack_final == 1) && (temp_count != (read_count - 1))) ||
((ack_final == 0) && (temp_count != read_count))) {
dev_err(dev, "Address NACK! ACK(0x%x)\n", ack);
break;
}
for (i = read_count; i >= 1; i--) {
int shift;
int offset;
if (i > 4) {
offset = DDC_DDCMD1;
shift = (i - 5) * 8;
} else {
offset = DDC_DDCMD0;
shift = (i - 1) * 8;
}
msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
0xff << shift,
shift);
}
remain_count -= read_count;
index += read_count;
}
return 0;
}
static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
{
struct device *dev = ddc->adap.dev.parent;
u32 ack;
ddcm_trigger_mode(ddc, DDCM_START);
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
0x1);
ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
dev_dbg(dev, "ack = %d\n", ack);
if (ack != 0x03) {
dev_err(dev, "i2c ack err!\n");
return -EIO;
}
return 0;
}
static int mtk_hdmi_ddc_xfer(struct i2c_adapter *adapter,
struct i2c_msg *msgs, int num)
{
struct mtk_hdmi_ddc *ddc = adapter->algo_data;
struct device *dev = adapter->dev.parent;
int ret;
int i;
if (!ddc) {
dev_err(dev, "invalid arguments\n");
return -EINVAL;
}
sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
dev_err(dev, "ddc line is busy!\n");
return -EBUSY;
}
sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
DDCM_CLK_DIV_OFFSET, SIF1_CLOK);
for (i = 0; i < num; i++) {
struct i2c_msg *msg = &msgs[i];
dev_dbg(dev, "i2c msg, adr:0x%x, flags:%d, len :0x%x\n",
msg->addr, msg->flags, msg->len);
if (msg->flags & I2C_M_RD)
ret = mtk_hdmi_ddc_read_msg(ddc, msg);
else
ret = mtk_hdmi_ddc_write_msg(ddc, msg);
if (ret < 0)
goto xfer_end;
}
ddcm_trigger_mode(ddc, DDCM_STOP);
return i;
xfer_end:
ddcm_trigger_mode(ddc, DDCM_STOP);
dev_err(dev, "ddc failed!\n");
return ret;
}
static u32 mtk_hdmi_ddc_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm mtk_hdmi_ddc_algorithm = {
.master_xfer = mtk_hdmi_ddc_xfer,
.functionality = mtk_hdmi_ddc_func,
};
static int mtk_hdmi_ddc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_hdmi_ddc *ddc;
struct resource *mem;
int ret;
ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
if (!ddc)
return -ENOMEM;
ddc->clk = devm_clk_get(dev, "ddc-i2c");
if (IS_ERR(ddc->clk)) {
dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);
return PTR_ERR(ddc->clk);
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ddc->regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(ddc->regs))
return PTR_ERR(ddc->regs);
ret = clk_prepare_enable(ddc->clk);
if (ret) {
dev_err(dev, "enable ddc clk failed!\n");
return ret;
}
strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
ddc->adap.owner = THIS_MODULE;
ddc->adap.class = I2C_CLASS_DDC;
ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
ddc->adap.retries = 3;
ddc->adap.dev.of_node = dev->of_node;
ddc->adap.algo_data = ddc;
ddc->adap.dev.parent = &pdev->dev;
ret = i2c_add_adapter(&ddc->adap);
if (ret < 0) {
dev_err(dev, "failed to add bus to i2c core\n");
goto err_clk_disable;
}
platform_set_drvdata(pdev, ddc);
dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
dev_dbg(dev, "physical adr: %pa, end: %pa\n", &mem->start,
&mem->end);
return 0;
err_clk_disable:
clk_disable_unprepare(ddc->clk);
return ret;
}
static int mtk_hdmi_ddc_remove(struct platform_device *pdev)
{
struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
i2c_del_adapter(&ddc->adap);
clk_disable_unprepare(ddc->clk);
return 0;
}
static const struct of_device_id mtk_hdmi_ddc_match[] = {
{ .compatible = "mediatek,mt8173-hdmi-ddc", },
{},
};
struct platform_driver mtk_hdmi_ddc_driver = {
.probe = mtk_hdmi_ddc_probe,
.remove = mtk_hdmi_ddc_remove,
.driver = {
.name = "mediatek-hdmi-ddc",
.of_match_table = mtk_hdmi_ddc_match,
},
};
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
MODULE_LICENSE("GPL v2");

238
drivers/gpu/drm/mediatek/mtk_hdmi_regs.h Normal file
View File

@ -0,0 +1,238 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MTK_HDMI_REGS_H
#define _MTK_HDMI_REGS_H
#define GRL_INT_MASK 0x18
#define GRL_IFM_PORT 0x188
#define GRL_CH_SWAP 0x198
#define LR_SWAP BIT(0)
#define LFE_CC_SWAP BIT(1)
#define LSRS_SWAP BIT(2)
#define RLS_RRS_SWAP BIT(3)
#define LR_STATUS_SWAP BIT(4)
#define GRL_I2S_C_STA0 0x140
#define GRL_I2S_C_STA1 0x144
#define GRL_I2S_C_STA2 0x148
#define GRL_I2S_C_STA3 0x14C
#define GRL_I2S_C_STA4 0x150
#define GRL_I2S_UV 0x154
#define I2S_UV_V BIT(0)
#define I2S_UV_U BIT(1)
#define I2S_UV_CH_EN_MASK 0x3c
#define I2S_UV_CH_EN(x) BIT((x) + 2)
#define I2S_UV_TMDS_DEBUG BIT(6)
#define I2S_UV_NORMAL_INFO_INV BIT(7)
#define GRL_ACP_ISRC_CTRL 0x158
#define VS_EN BIT(0)
#define ACP_EN BIT(1)
#define ISRC1_EN BIT(2)
#define ISRC2_EN BIT(3)
#define GAMUT_EN BIT(4)
#define GRL_CTS_CTRL 0x160
#define CTS_CTRL_SOFT BIT(0)
#define GRL_INT 0x14
#define INT_MDI BIT(0)
#define INT_HDCP BIT(1)
#define INT_FIFO_O BIT(2)
#define INT_FIFO_U BIT(3)
#define INT_IFM_ERR BIT(4)
#define INT_INF_DONE BIT(5)
#define INT_NCTS_DONE BIT(6)
#define INT_CTRL_PKT_DONE BIT(7)
#define GRL_INT_MASK 0x18
#define GRL_CTRL 0x1C
#define CTRL_GEN_EN BIT(2)
#define CTRL_SPD_EN BIT(3)
#define CTRL_MPEG_EN BIT(4)
#define CTRL_AUDIO_EN BIT(5)
#define CTRL_AVI_EN BIT(6)
#define CTRL_AVMUTE BIT(7)
#define GRL_STATUS 0x20
#define STATUS_HTPLG BIT(0)
#define STATUS_PORD BIT(1)
#define GRL_DIVN 0x170
#define NCTS_WRI_ANYTIME BIT(6)
#define GRL_AUDIO_CFG 0x17C
#define AUDIO_ZERO BIT(0)
#define HIGH_BIT_RATE BIT(1)
#define SACD_DST BIT(2)
#define DST_NORMAL_DOUBLE BIT(3)
#define DSD_INV BIT(4)
#define LR_INV BIT(5)
#define LR_MIX BIT(6)
#define DSD_SEL BIT(7)
#define GRL_NCTS 0x184
#define GRL_CH_SW0 0x18C
#define GRL_CH_SW1 0x190
#define GRL_CH_SW2 0x194
#define CH_SWITCH(from, to) ((from) << ((to) * 3))
#define GRL_INFOFRM_VER 0x19C
#define GRL_INFOFRM_TYPE 0x1A0
#define GRL_INFOFRM_LNG 0x1A4
#define GRL_MIX_CTRL 0x1B4
#define MIX_CTRL_SRC_EN BIT(0)
#define BYPASS_VOLUME BIT(1)
#define MIX_CTRL_FLAT BIT(7)
#define GRL_AOUT_CFG 0x1C4
#define AOUT_BNUM_SEL_MASK 0x03
#define AOUT_24BIT 0x00
#define AOUT_20BIT 0x02
#define AOUT_16BIT 0x03
#define AOUT_FIFO_ADAP_CTRL BIT(6)
#define AOUT_BURST_PREAMBLE_EN BIT(7)
#define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \
AOUT_FIFO_ADAP_CTRL)
#define GRL_SHIFT_L1 0x1C0
#define GRL_SHIFT_R2 0x1B0
#define AUDIO_PACKET_OFF BIT(6)
#define GRL_CFG0 0x24
#define CFG0_I2S_MODE_MASK 0x3
#define CFG0_I2S_MODE_RTJ 0x1
#define CFG0_I2S_MODE_LTJ 0x0
#define CFG0_I2S_MODE_I2S 0x2
#define CFG0_W_LENGTH_MASK 0x30
#define CFG0_W_LENGTH_24BIT 0x00
#define CFG0_W_LENGTH_16BIT 0x10
#define GRL_CFG1 0x28
#define CFG1_EDG_SEL BIT(0)
#define CFG1_SPDIF BIT(1)
#define CFG1_DVI BIT(2)
#define CFG1_HDCP_DEBUG BIT(3)
#define GRL_CFG2 0x2c
#define CFG2_MHL_DE_SEL BIT(3)
#define CFG2_MHL_FAKE_DE_SEL BIT(4)
#define CFG2_MHL_DATA_REMAP BIT(5)
#define CFG2_NOTICE_EN BIT(6)
#define CFG2_ACLK_INV BIT(7)
#define GRL_CFG3 0x30
#define CFG3_AES_KEY_INDEX_MASK 0x3f
#define CFG3_CONTROL_PACKET_DELAY BIT(6)
#define CFG3_KSV_LOAD_START BIT(7)
#define GRL_CFG4 0x34
#define CFG4_AES_KEY_LOAD BIT(4)
#define CFG4_AV_UNMUTE_EN BIT(5)
#define CFG4_AV_UNMUTE_SET BIT(6)
#define CFG4_MHL_MODE BIT(7)
#define GRL_CFG5 0x38
#define CFG5_CD_RATIO_MASK 0x8F
#define CFG5_FS128 (0x1 << 4)
#define CFG5_FS256 (0x2 << 4)
#define CFG5_FS384 (0x3 << 4)
#define CFG5_FS512 (0x4 << 4)
#define CFG5_FS768 (0x6 << 4)
#define DUMMY_304 0x304
#define CHMO_SEL (0x3 << 2)
#define CHM1_SEL (0x3 << 4)
#define CHM2_SEL (0x3 << 6)
#define AUDIO_I2S_NCTS_SEL BIT(1)
#define AUDIO_I2S_NCTS_SEL_64 (1 << 1)
#define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
#define NEW_GCP_CTRL BIT(0)
#define NEW_GCP_CTRL_MERGE BIT(0)
#define GRL_L_STATUS_0 0x200
#define GRL_L_STATUS_1 0x204
#define GRL_L_STATUS_2 0x208
#define GRL_L_STATUS_3 0x20c
#define GRL_L_STATUS_4 0x210
#define GRL_L_STATUS_5 0x214
#define GRL_L_STATUS_6 0x218
#define GRL_L_STATUS_7 0x21c
#define GRL_L_STATUS_8 0x220
#define GRL_L_STATUS_9 0x224
#define GRL_L_STATUS_10 0x228
#define GRL_L_STATUS_11 0x22c
#define GRL_L_STATUS_12 0x230
#define GRL_L_STATUS_13 0x234
#define GRL_L_STATUS_14 0x238
#define GRL_L_STATUS_15 0x23c
#define GRL_L_STATUS_16 0x240
#define GRL_L_STATUS_17 0x244
#define GRL_L_STATUS_18 0x248
#define GRL_L_STATUS_19 0x24c
#define GRL_L_STATUS_20 0x250
#define GRL_L_STATUS_21 0x254
#define GRL_L_STATUS_22 0x258
#define GRL_L_STATUS_23 0x25c
#define GRL_R_STATUS_0 0x260
#define GRL_R_STATUS_1 0x264
#define GRL_R_STATUS_2 0x268
#define GRL_R_STATUS_3 0x26c
#define GRL_R_STATUS_4 0x270
#define GRL_R_STATUS_5 0x274
#define GRL_R_STATUS_6 0x278
#define GRL_R_STATUS_7 0x27c
#define GRL_R_STATUS_8 0x280
#define GRL_R_STATUS_9 0x284
#define GRL_R_STATUS_10 0x288
#define GRL_R_STATUS_11 0x28c
#define GRL_R_STATUS_12 0x290
#define GRL_R_STATUS_13 0x294
#define GRL_R_STATUS_14 0x298
#define GRL_R_STATUS_15 0x29c
#define GRL_R_STATUS_16 0x2a0
#define GRL_R_STATUS_17 0x2a4
#define GRL_R_STATUS_18 0x2a8
#define GRL_R_STATUS_19 0x2ac
#define GRL_R_STATUS_20 0x2b0
#define GRL_R_STATUS_21 0x2b4
#define GRL_R_STATUS_22 0x2b8
#define GRL_R_STATUS_23 0x2bc
#define GRL_ABIST_CTRL0 0x2D4
#define GRL_ABIST_CTRL1 0x2D8
#define ABIST_EN BIT(7)
#define ABIST_DATA_FMT (0x7 << 0)
#define VIDEO_CFG_0 0x380
#define VIDEO_CFG_1 0x384
#define VIDEO_CFG_2 0x388
#define VIDEO_CFG_3 0x38c
#define VIDEO_CFG_4 0x390
#define VIDEO_SOURCE_SEL BIT(7)
#define NORMAL_PATH (1 << 7)
#define GEN_RGB (0 << 7)
#define HDMI_SYS_CFG1C 0x000
#define HDMI_ON BIT(0)
#define HDMI_RST BIT(1)
#define ANLG_ON BIT(2)
#define CFG10_DVI BIT(3)
#define HDMI_TST BIT(3)
#define SYS_KEYMASK1 (0xff << 8)
#define SYS_KEYMASK2 (0xff << 16)
#define AUD_OUTSYNC_EN BIT(24)
#define AUD_OUTSYNC_PRE_EN BIT(25)
#define I2CM_ON BIT(26)
#define E2PROM_TYPE_8BIT BIT(27)
#define MCM_E2PROM_ON BIT(28)
#define EXT_E2PROM_ON BIT(29)
#define HTPLG_PIN_SEL_OFF BIT(30)
#define AES_EFUSE_ENABLE BIT(31)
#define HDMI_SYS_CFG20 0x004
#define DEEP_COLOR_MODE_MASK (3 << 1)
#define COLOR_8BIT_MODE (0 << 1)
#define COLOR_10BIT_MODE (1 << 1)
#define COLOR_12BIT_MODE (2 << 1)
#define COLOR_16BIT_MODE (3 << 1)
#define DEEP_COLOR_EN BIT(0)
#define HDMI_AUDIO_TEST_SEL BIT(8)
#define HDMI2P0_EN BIT(11)
#define HDMI_OUT_FIFO_EN BIT(16)
#define HDMI_OUT_FIFO_CLK_INV BIT(17)
#define MHL_MODE_ON BIT(28)
#define MHL_PP_MODE BIT(29)
#define MHL_SYNC_AUTO_EN BIT(30)
#define HDMI_PCLK_FREE_RUN BIT(31)
#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
#endif

515
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c Normal file
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@ -0,0 +1,515 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
#define PLL_FBKDIV_SHIFT 24
#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
#define PLL_FBKSEL_SHIFT 22
#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
#define PREDIV_SHIFT 20
#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
#define POSDIV_SHIFT 18
#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
#define RG_HDMITX_PLL_IR (0xf << 12)
#define PLL_IR_SHIFT 12
#define RG_HDMITX_PLL_IC (0xf << 8)
#define PLL_IC_SHIFT 8
#define RG_HDMITX_PLL_BP (0xf << 4)
#define PLL_BP_SHIFT 4
#define RG_HDMITX_PLL_BR (0x3 << 2)
#define PLL_BR_SHIFT 2
#define RG_HDMITX_PLL_BC (0x3 << 0)
#define PLL_BC_SHIFT 0
#define HDMI_CON1 0x04
#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
#define PLL_DIVEN_SHIFT 29
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
#define RG_HDMITX_PLL_BAND (0x3f << 16)
#define RG_HDMITX_PLL_REF_SEL BIT(15)
#define RG_HDMITX_PLL_BIAS_EN BIT(14)
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
#define PLL_TXDIV_SHIFT 10
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
#define RG_HDMITX_PLL_MONREF_EN BIT(6)
#define RG_HDMITX_PLL_TST_EN BIT(5)
#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
#define HDMI_CON2 0x08
#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
#define HDMI_CON3 0x0c
#define RG_HDMITX_SER_EN (0xf << 28)
#define RG_HDMITX_PRD_EN (0xf << 24)
#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
#define RG_HDMITX_DRV_EN (0xf << 16)
#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
#define DRV_IMP_EN_SHIFT 12
#define RG_HDMITX_MHLCK_FORCE BIT(10)
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
#define RG_HDMITX_MHLCK_EN BIT(8)
#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
#define RG_HDMITX_SER_BIST_TOG BIT(2)
#define RG_HDMITX_SER_DIN_TOG BIT(1)
#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
#define HDMI_CON4 0x10
#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
#define PRD_IBIAS_CLK_SHIFT 24
#define PRD_IBIAS_D2_SHIFT 16
#define PRD_IBIAS_D1_SHIFT 8
#define PRD_IBIAS_D0_SHIFT 0
#define HDMI_CON5 0x14
#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
#define DRV_IBIAS_CLK_SHIFT 24
#define DRV_IBIAS_D2_SHIFT 16
#define DRV_IBIAS_D1_SHIFT 8
#define DRV_IBIAS_D0_SHIFT 0
#define HDMI_CON6 0x18
#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
#define DRV_IMP_CLK_SHIFT 24
#define DRV_IMP_D2_SHIFT 16
#define DRV_IMP_D1_SHIFT 8
#define DRV_IMP_D0_SHIFT 0
#define HDMI_CON7 0x1c
#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
#define RG_HDMITX_SER_DIN (0x3ff << 16)
#define RG_HDMITX_CHLDC_TST (0xf << 12)
#define RG_HDMITX_CHLCK_TST (0xf << 8)
#define RG_HDMITX_RESERVE (0xff << 0)
#define HDMI_CON8 0x20
#define RGS_HDMITX_2T1_LEV (0xf << 16)
#define RGS_HDMITX_2T1_EDG (0xf << 12)
#define RGS_HDMITX_5T1_LEV (0xf << 8)
#define RGS_HDMITX_5T1_EDG (0xf << 4)
#define RGS_HDMITX_PLUG_TST BIT(0)
struct mtk_hdmi_phy {
void __iomem *regs;
struct device *dev;
struct clk *pll;
struct clk_hw pll_hw;
unsigned long pll_rate;
u8 drv_imp_clk;
u8 drv_imp_d2;
u8 drv_imp_d1;
u8 drv_imp_d0;
u32 ibias;
u32 ibias_up;
};
static const u8 PREDIV[3][4] = {
{0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
{0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
{0x1, 0x1, 0x1, 0x1} /* 148Mhz */
};
static const u8 TXDIV[3][4] = {
{0x3, 0x3, 0x3, 0x2}, /* 27Mhz */
{0x2, 0x1, 0x1, 0x1}, /* 74Mhz */
{0x1, 0x0, 0x0, 0x0} /* 148Mhz */
};
static const u8 FBKSEL[3][4] = {
{0x1, 0x1, 0x1, 0x1}, /* 27Mhz */
{0x1, 0x0, 0x1, 0x1}, /* 74Mhz */
{0x1, 0x0, 0x1, 0x1} /* 148Mhz */
};
static const u8 FBKDIV[3][4] = {
{19, 24, 29, 19}, /* 27Mhz */
{19, 24, 14, 19}, /* 74Mhz */
{19, 24, 14, 19} /* 148Mhz */
};
static const u8 DIVEN[3][4] = {
{0x2, 0x1, 0x1, 0x2}, /* 27Mhz */
{0x2, 0x2, 0x2, 0x2}, /* 74Mhz */
{0x2, 0x2, 0x2, 0x2} /* 148Mhz */
};
static const u8 HTPLLBP[3][4] = {
{0xc, 0xc, 0x8, 0xc}, /* 27Mhz */
{0xc, 0xf, 0xf, 0xc}, /* 74Mhz */
{0xc, 0xf, 0xf, 0xc} /* 148Mhz */
};
static const u8 HTPLLBC[3][4] = {
{0x2, 0x3, 0x3, 0x2}, /* 27Mhz */
{0x2, 0x3, 0x3, 0x2}, /* 74Mhz */
{0x2, 0x3, 0x3, 0x2} /* 148Mhz */
};
static const u8 HTPLLBR[3][4] = {
{0x1, 0x1, 0x0, 0x1}, /* 27Mhz */
{0x1, 0x2, 0x2, 0x1}, /* 74Mhz */
{0x1, 0x2, 0x2, 0x1} /* 148Mhz */
};
static void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
u32 bits)
{
void __iomem *reg = hdmi_phy->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp &= ~bits;
writel(tmp, reg);
}
static void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
u32 bits)
{
void __iomem *reg = hdmi_phy->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp |= bits;
writel(tmp, reg);
}
static void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
u32 val, u32 mask)
{
void __iomem *reg = hdmi_phy->regs + offset;
u32 tmp;
tmp = readl(reg);
tmp = (tmp & ~mask) | (val & mask);
writel(tmp, reg);
}
static inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
{
return container_of(hw, struct mtk_hdmi_phy, pll_hw);
}
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
dev_dbg(hdmi_phy->dev, "%s\n", __func__);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
usleep_range(100, 150);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
usleep_range(100, 150);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
return 0;
}
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
dev_dbg(hdmi_phy->dev, "%s\n", __func__);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
usleep_range(100, 150);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
usleep_range(100, 150);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
usleep_range(100, 150);
}
static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
unsigned int pre_div;
unsigned int div;
dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
rate, parent_rate);
if (rate <= 27000000) {
pre_div = 0;
div = 3;
} else if (rate <= 74250000) {
pre_div = 1;
div = 2;
} else {
pre_div = 1;
div = 1;
}
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
(pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
(0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
(div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
(0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
(0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
(0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
(0x1 << PLL_BR_SHIFT),
RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
RG_HDMITX_PLL_BR);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
(0x3 << PRD_IBIAS_CLK_SHIFT) |
(0x3 << PRD_IBIAS_D2_SHIFT) |
(0x3 << PRD_IBIAS_D1_SHIFT) |
(0x3 << PRD_IBIAS_D0_SHIFT),
RG_HDMITX_PRD_IBIAS_CLK |
RG_HDMITX_PRD_IBIAS_D2 |
RG_HDMITX_PRD_IBIAS_D1 |
RG_HDMITX_PRD_IBIAS_D0);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
(0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
(hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
(hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
(hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
(hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
return 0;
}
static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy->pll_rate = rate;
if (rate <= 74250000)
*parent_rate = rate;
else
*parent_rate = rate / 2;
return rate;
}
static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
return hdmi_phy->pll_rate;
}
static const struct clk_ops mtk_hdmi_pll_ops = {
.prepare = mtk_hdmi_pll_prepare,
.unprepare = mtk_hdmi_pll_unprepare,
.set_rate = mtk_hdmi_pll_set_rate,
.round_rate = mtk_hdmi_pll_round_rate,
.recalc_rate = mtk_hdmi_pll_recalc_rate,
};
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
{
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
RG_HDMITX_DRV_EN);
usleep_range(100, 150);
}
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
{
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
RG_HDMITX_SER_EN);
}
static int mtk_hdmi_phy_power_on(struct phy *phy)
{
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
int ret;
ret = clk_prepare_enable(hdmi_phy->pll);
if (ret < 0)
return ret;
mtk_hdmi_phy_enable_tmds(hdmi_phy);
return 0;
}
static int mtk_hdmi_phy_power_off(struct phy *phy)
{
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
mtk_hdmi_phy_disable_tmds(hdmi_phy);
clk_disable_unprepare(hdmi_phy->pll);
return 0;
}
static const struct phy_ops mtk_hdmi_phy_ops = {
.power_on = mtk_hdmi_phy_power_on,
.power_off = mtk_hdmi_phy_power_off,
.owner = THIS_MODULE,
};
static int mtk_hdmi_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_hdmi_phy *hdmi_phy;
struct resource *mem;
struct clk *ref_clk;
const char *ref_clk_name;
struct clk_init_data clk_init = {
.ops = &mtk_hdmi_pll_ops,
.num_parents = 1,
.parent_names = (const char * const *)&ref_clk_name,
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
};
struct phy *phy;
struct phy_provider *phy_provider;
int ret;
hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
if (!hdmi_phy)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
hdmi_phy->regs = devm_ioremap_resource(dev, mem);
if (IS_ERR(hdmi_phy->regs)) {
ret = PTR_ERR(hdmi_phy->regs);
dev_err(dev, "Failed to get memory resource: %d\n", ret);
return ret;
}
ref_clk = devm_clk_get(dev, "pll_ref");
if (IS_ERR(ref_clk)) {
ret = PTR_ERR(ref_clk);
dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
ret);
return ret;
}
ref_clk_name = __clk_get_name(ref_clk);
ret = of_property_read_string(dev->of_node, "clock-output-names",
&clk_init.name);
if (ret < 0) {
dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
return ret;
}
hdmi_phy->pll_hw.init = &clk_init;
hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
if (IS_ERR(hdmi_phy->pll)) {
ret = PTR_ERR(hdmi_phy->pll);
dev_err(dev, "Failed to register PLL: %d\n", ret);
return ret;
}
ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
&hdmi_phy->ibias);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
return ret;
}
ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
&hdmi_phy->ibias_up);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
return ret;
}
dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
hdmi_phy->drv_imp_clk = 0x30;
hdmi_phy->drv_imp_d2 = 0x30;
hdmi_phy->drv_imp_d1 = 0x30;
hdmi_phy->drv_imp_d0 = 0x30;
phy = devm_phy_create(dev, NULL, &mtk_hdmi_phy_ops);
if (IS_ERR(phy)) {
dev_err(dev, "Failed to create HDMI PHY\n");
return PTR_ERR(phy);
}
phy_set_drvdata(phy, hdmi_phy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
hdmi_phy->dev = dev;
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
hdmi_phy->pll);
}
static int mtk_hdmi_phy_remove(struct platform_device *pdev)
{
return 0;
}
static const struct of_device_id mtk_hdmi_phy_match[] = {
{ .compatible = "mediatek,mt8173-hdmi-phy", },
{},
};
struct platform_driver mtk_hdmi_phy_driver = {
.probe = mtk_hdmi_phy_probe,
.remove = mtk_hdmi_phy_remove,
.driver = {
.name = "mediatek-hdmi-phy",
.of_match_table = mtk_hdmi_phy_match,
},
};
MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
MODULE_LICENSE("GPL v2");

9
drivers/gpu/drm/msm/msm_drv.c
View File

@ -197,8 +197,6 @@ static int msm_drm_uninit(struct device *dev)
drm_kms_helper_poll_fini(ddev);
drm_connector_unregister_all(ddev);
drm_dev_unregister(ddev);
#ifdef CONFIG_DRM_FBDEV_EMULATION
@ -431,12 +429,6 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
if (ret)
goto fail;
ret = drm_connector_register_all(ddev);
if (ret) {
dev_err(dev, "failed to register connectors\n");
goto fail;
}
drm_mode_config_reset(ddev);
#ifdef CONFIG_DRM_FBDEV_EMULATION
@ -730,7 +722,6 @@ static struct drm_driver msm_driver = {
.open = msm_open,
.preclose = msm_preclose,
.lastclose = msm_lastclose,
.set_busid = drm_platform_set_busid,
.irq_handler = msm_irq,
.irq_preinstall = msm_irq_preinstall,
.irq_postinstall = msm_irq_postinstall,

1
drivers/gpu/drm/nouveau/nouveau_drm.c
View File

@ -1070,7 +1070,6 @@ nouveau_drm_init(void)
driver_pci = driver_stub;
driver_pci.set_busid = drm_pci_set_busid;
driver_platform = driver_stub;
driver_platform.set_busid = drm_platform_set_busid;
nouveau_display_options();

1
drivers/gpu/drm/omapdrm/omap_drv.c
View File

@ -801,7 +801,6 @@ static struct drm_driver omap_drm_driver = {
.unload = dev_unload,
.open = dev_open,
.lastclose = dev_lastclose,
.set_busid = drm_platform_set_busid,
.get_vblank_counter = drm_vblank_no_hw_counter,
.enable_vblank = omap_irq_enable_vblank,
.disable_vblank = omap_irq_disable_vblank,

3
drivers/gpu/drm/omapdrm/omap_fbdev.c
View File

@ -279,9 +279,6 @@ struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev)
if (ret)
goto fini;
/* disable all the possible outputs/crtcs before entering KMS mode */
drm_helper_disable_unused_functions(dev);
ret = drm_fb_helper_initial_config(helper, 32);
if (ret)
goto fini;

15
drivers/gpu/drm/rcar-du/rcar_du_drv.c
View File

@ -278,7 +278,6 @@ static int rcar_du_remove(struct platform_device *pdev)
struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
struct drm_device *ddev = rcdu->ddev;
drm_connector_unregister_all(ddev);
drm_dev_unregister(ddev);
if (rcdu->fbdev)
@ -320,8 +319,6 @@ static int rcar_du_probe(struct platform_device *pdev)
if (!ddev)
return -ENOMEM;
drm_dev_set_unique(ddev, dev_name(&pdev->dev));
rcdu->ddev = ddev;
ddev->dev_private = rcdu;
@ -339,15 +336,15 @@ static int rcar_du_probe(struct platform_device *pdev)
* disabled for all CRTCs.
*/
ret = drm_vblank_init(ddev, (1 << rcdu->info->num_crtcs) - 1);
if (ret < 0) {
dev_err(&pdev->dev, "failed to initialize vblank\n");
if (ret < 0)
goto error;
}
/* DRM/KMS objects */
ret = rcar_du_modeset_init(rcdu);
if (ret < 0) {
dev_err(&pdev->dev, "failed to initialize DRM/KMS (%d)\n", ret);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev,
"failed to initialize DRM/KMS (%d)\n", ret);
goto error;
}
@ -360,10 +357,6 @@ static int rcar_du_probe(struct platform_device *pdev)
if (ret)
goto error;
ret = drm_connector_register_all(ddev);
if (ret < 0)
goto error;
DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
return 0;

5
drivers/gpu/drm/rcar-du/rcar_du_regs.h
View File

@ -195,9 +195,10 @@
#define DEFR6_ODPM12_DISP (2 << 8)
#define DEFR6_ODPM12_CDE (3 << 8)
#define DEFR6_ODPM12_MASK (3 << 8)
#define DEFR6_TCNE2 (1 << 6)
#define DEFR6_TCNE1 (1 << 6)
#define DEFR6_TCNE0 (1 << 4)
#define DEFR6_MLOS1 (1 << 2)
#define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE2)
#define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1)
/* -----------------------------------------------------------------------------
* R8A7790-only Control Registers

1
drivers/gpu/drm/rockchip/Kconfig
View File

@ -2,6 +2,7 @@ config DRM_ROCKCHIP
tristate "DRM Support for Rockchip"
depends on DRM && ROCKCHIP_IOMMU
depends on RESET_CONTROLLER
select DRM_GEM_CMA_HELPER
select DRM_KMS_HELPER
select DRM_KMS_FB_HELPER
select DRM_PANEL

21
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@ -146,16 +146,12 @@ static int rockchip_drm_bind(struct device *dev)
if (!drm_dev)
return -ENOMEM;
ret = drm_dev_register(drm_dev, 0);
if (ret)
goto err_free;
dev_set_drvdata(dev, drm_dev);
private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL);
if (!private) {
ret = -ENOMEM;
goto err_unregister;
goto err_free;
}
drm_dev->dev_private = private;
@ -197,12 +193,6 @@ static int rockchip_drm_bind(struct device *dev)
if (ret)
goto err_detach_device;
ret = drm_connector_register_all(drm_dev);
if (ret) {
dev_err(dev, "failed to register connectors\n");
goto err_unbind;
}
/* init kms poll for handling hpd */
drm_kms_helper_poll_init(drm_dev);
@ -222,14 +212,19 @@ static int rockchip_drm_bind(struct device *dev)
if (ret)
goto err_vblank_cleanup;
ret = drm_dev_register(drm_dev, 0);
if (ret)
goto err_fbdev_fini;
if (is_support_iommu)
arm_iommu_release_mapping(mapping);
return 0;
err_fbdev_fini:
rockchip_drm_fbdev_fini(drm_dev);
err_vblank_cleanup:
drm_vblank_cleanup(drm_dev);
err_kms_helper_poll_fini:
drm_kms_helper_poll_fini(drm_dev);
err_unbind:
component_unbind_all(dev, drm_dev);
err_detach_device:
if (is_support_iommu)
@ -240,8 +235,6 @@ err_release_mapping:
err_config_cleanup:
drm_mode_config_cleanup(drm_dev);
drm_dev->dev_private = NULL;
err_unregister:
drm_dev_unregister(drm_dev);
err_free:
drm_dev_unref(drm_dev);
return ret;

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@ -626,6 +626,7 @@ static int vop_plane_atomic_check(struct drm_plane *plane,
ret = drm_plane_helper_check_update(plane, crtc, state->fb,
src, dest, &clip,
state->rotation,
min_scale,
max_scale,
true, true, &visible);

1
drivers/gpu/drm/shmobile/shmob_drm_drv.c
View File

@ -259,7 +259,6 @@ static struct drm_driver shmob_drm_driver = {
| DRIVER_PRIME,
.load = shmob_drm_load,
.unload = shmob_drm_unload,
.set_busid = drm_platform_set_busid,
.irq_handler = shmob_drm_irq,
.get_vblank_counter = drm_vblank_no_hw_counter,
.enable_vblank = shmob_drm_enable_vblank,

2
drivers/gpu/drm/sis/sis_mm.c
View File

@ -316,7 +316,7 @@ void sis_reclaim_buffers_locked(struct drm_device *dev,
struct sis_file_private *file_priv = file->driver_priv;
struct sis_memblock *entry, *next;
if (!(file->minor->master && file->master->lock.hw_lock))
if (!(dev->master && file->master->lock.hw_lock))
return;
drm_legacy_idlelock_take(&file->master->lock);

20
drivers/gpu/drm/sti/sti_compositor.c
View File

@ -55,6 +55,26 @@ struct sti_compositor_data stih416_compositor_data = {
},
};
int sti_compositor_debufs_init(struct sti_compositor *compo,
struct drm_minor *minor)
{
int ret = 0, i;
for (i = 0; compo->vid[i]; i++) {
ret = vid_debugfs_init(compo->vid[i], minor);
if (ret)
return ret;
}
for (i = 0; compo->mixer[i]; i++) {
ret = sti_mixer_debugfs_init(compo->mixer[i], minor);
if (ret)
return ret;
}
return 0;
}
static int sti_compositor_bind(struct device *dev,
struct device *master,
void *data)

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