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drm/msm/dpu: Add SM8350 to hw catalog
Add compatibility for SM8350 display subsystem, including required entries in DPU hw catalog. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/516340/ Link: https://lore.kernel.org/r/20221230153554.105856-4-robert.foss@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Robert Foss
Dmitry Baryshkov
parent
430e11f42b
commit
0e91bcbb00
@ -111,6 +111,15 @@
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BIT(MDP_INTF3_INTR) | \
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BIT(MDP_INTF4_INTR))
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#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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BIT(MDP_INTF0_7xxx_INTR) | \
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BIT(MDP_INTF1_7xxx_INTR) | \
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BIT(MDP_INTF2_7xxx_INTR) | \
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BIT(MDP_INTF3_7xxx_INTR) | \
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0)
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#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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@ -386,6 +395,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sm8350_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
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.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
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.ubwc_version = DPU_HW_UBWC_VER_40,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sm8450_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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@ -550,6 +573,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sm8350_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2ac, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
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.reg_off = 0x2b4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
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.reg_off = 0x2bc, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
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.reg_off = 0x2c4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2ac, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2b4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.reg_off = 0x2bc, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.reg_off = 0x2c4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
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.reg_off = 0x2bc, .bit_off = 20},
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},
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};
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static const struct dpu_mdp_cfg sm8450_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -735,6 +785,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg sm8350_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1e8,
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.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1e8,
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.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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{
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.name = "ctl_4", .id = CTL_4,
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.base = 0x19000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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},
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{
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.name = "ctl_5", .id = CTL_5,
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.base = 0x1a000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
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},
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};
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static const struct dpu_ctl_cfg sm8450_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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@ -744,32 +833,32 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x204,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
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.base = 0x16000, .len = 0x1e8,
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.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x204,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
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.base = 0x17000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x204,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
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.base = 0x18000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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{
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.name = "ctl_4", .id = CTL_4,
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.base = 0x19000, .len = 0x204,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
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.base = 0x19000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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},
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{
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.name = "ctl_5", .id = CTL_5,
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.base = 0x1a000, .len = 0x204,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
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.base = 0x1a000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
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},
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};
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@ -1328,6 +1417,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
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-1),
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};
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static const struct dpu_pingpong_cfg sm8350_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
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PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
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PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
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PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
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-1),
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PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
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-1),
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};
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static const struct dpu_pingpong_cfg sc7280_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
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@ -1386,6 +1496,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
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MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
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};
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static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
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MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
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MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
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MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
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};
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static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
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MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
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MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
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@ -1410,6 +1526,11 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
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DSC_BLK("dsc_3", DSC_3, 0x80c00),
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};
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static struct dpu_dsc_cfg sm8350_dsc[] = {
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DSC_BLK("dsc_0", DSC_0, 0x80000),
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DSC_BLK("dsc_1", DSC_1, 0x81000),
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};
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/*************************************************************
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* INTF sub blocks config
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*************************************************************/
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@ -1457,6 +1578,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
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INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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static const struct dpu_intf_cfg sm8350_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
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INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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};
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static const struct dpu_intf_cfg sc8180x_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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@ -1592,6 +1720,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
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.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
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};
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static const struct dpu_reg_dma_cfg sm8350_regdma = {
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.base = 0x400,
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.version = 0x00020000,
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.trigger_sel_off = 0x119c,
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.xin_id = 7,
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.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
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};
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static const struct dpu_reg_dma_cfg sm8450_regdma = {
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.base = 0x0,
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.version = 0x00020000,
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@ -1962,6 +2098,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sm8350_perf_data = {
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.max_bw_low = 11800000,
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.max_bw_high = 15500000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 800000,
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.min_prefill_lines = 40,
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/* FIXME: lut tables */
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.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
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.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg qcm2290_perf_data = {
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.max_bw_low = 2700000,
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.max_bw_high = 2700000,
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@ -2160,6 +2326,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
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.mdss_irqs = IRQ_SM8250_MASK,
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};
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static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
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.caps = &sm8350_dpu_caps,
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.mdp_count = ARRAY_SIZE(sm8350_mdp),
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.mdp = sm8350_mdp,
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.ctl_count = ARRAY_SIZE(sm8350_ctl),
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.ctl = sm8350_ctl,
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.sspp_count = ARRAY_SIZE(sm8250_sspp),
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.sspp = sm8250_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.dspp_count = ARRAY_SIZE(sm8150_dspp),
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.dspp = sm8150_dspp,
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.pingpong_count = ARRAY_SIZE(sm8350_pp),
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.pingpong = sm8350_pp,
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.dsc_count = ARRAY_SIZE(sm8350_dsc),
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.dsc = sm8350_dsc,
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.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
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.merge_3d = sm8350_merge_3d,
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.intf_count = ARRAY_SIZE(sm8350_intf),
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.intf = sm8350_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.reg_dma_count = 1,
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.dma_cfg = &sm8250_regdma,
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.perf = &sm8350_perf_data,
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.mdss_irqs = IRQ_SM8350_MASK,
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};
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static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
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.caps = &sm8450_dpu_caps,
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.mdp_count = ARRAY_SIZE(sm8450_mdp),
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@ -2244,6 +2438,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
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{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
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{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
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{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
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{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
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{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
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};
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@ -46,6 +46,7 @@
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#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
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#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
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#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
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#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
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||||
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
|
||||
#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user