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ARM: devicetree updates for 6.6

Browse Source 
These are the devicetree updates for Arm and RISC-V based SoCs,
 mainly from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips,
 Samsung, ST and Starfive.
 
 Only a few new SoC got added:
 
  - TI AM62P5, a variant of the existing Sitara AM62x family
 
  - Intel Agilex5, an FPGFA platform that includes an
    Cortex-A76/A55 SoC.
 
  - Qualcomm ipq5018 is used in wireless access points
 
  - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile
    phone platform.
 
 In total, 29 machines get added, which is low because of the summer
 break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
 Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head.  Most of
 these are development and reference boards.
 
 Despite not adding a lot of new machines, there are over 700 patches in
 total, most of which are cleanups and minor fixes.
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Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
 "These are the devicetree updates for Arm and RISC-V based SoCs, mainly
  from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and
  Starfive.

  Only a few new SoC got added:

   - TI AM62P5, a variant of the existing Sitara AM62x family

   - Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55
     SoC.

   - Qualcomm ipq5018 is used in wireless access points

   - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone
     platform.

  In total, 29 machines get added, which is low because of the summer
  break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
  Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
  these are development and reference boards.

  Despite not adding a lot of new machines, there are over 700 patches
  in total, most of which are cleanups and minor fixes"

* tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits)
  arm64: dts: use capital "OR" for multiple licenses in SPDX
  ARM: dts: use capital "OR" for multiple licenses in SPDX
  arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
  ARM: dts: qcom: apq8064: add support to gsbi4 uart
  riscv: dts: change TH1520 files to dual license
  riscv: dts: thead: add BeagleV Ahead board device tree
  dt-bindings: riscv: Add BeagleV Ahead board compatibles
  ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
  ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
  dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
  ARM: dts: stm32: support display on stm32f746-disco board
  ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
  ARM: dts: stm32: add pin map for LTDC on stm32f7
  ARM: dts: stm32: add ltdc support on stm32f746 MCU
  arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Add PDC
  riscv: dts: starfive: fix jh7110 qspi sort order
  ...
This commit is contained in:
Linus Torvalds 2023-08-30 16:53:46 -07:00
commit 0e72db7767
923 changed files with 39059 additions and 10839 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -218,6 +218,14 @@ properties:
- amlogic,aq222
- const: amlogic,s4
- description: Boards with the Amlogic T7 A311D2 SoC
items:
- enum:
- amlogic,an400
- khadas,vim4
- const: amlogic,a311d2
- const: amlogic,t7
additionalProperties: true
...

2
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
View File

@ -79,9 +79,11 @@ properties:
- facebook,elbert-bmc
- facebook,fuji-bmc
- facebook,greatlakes-bmc
- facebook,yosemite4-bmc
- ibm,everest-bmc
- ibm,rainier-bmc
- ibm,tacoma-bmc
- inventec,starscream-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
- qcom,dc-scm-v1-bmc

1
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml
View File

@ -66,6 +66,7 @@ properties:
- description: BCM47094 based boards
items:
- enum:
- asus,rt-ac3100
- asus,rt-ac88u
- dlink,dir-885l
- dlink,dir-890l

39
Documentation/devicetree/bindings/arm/bcm/brcm,bcm53573.yaml Normal file
View File

@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm53573.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53573 SoCs family
description:
Broadcom BCM53573 / BCM47189 Wi-Fi SoCs derived from Northstar.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM53573 based boards
items:
- enum:
- tenda,ac6-v1
- tenda,w15e-v1
- const: brcm,bcm53573
- description: BCM47189 based boards
items:
- enum:
- brcm,bcm947189acdbmr
- luxul,xap-810-v1
- luxul,xap-1440-v1
- tenda,ac9
- const: brcm,bcm47189
- const: brcm,bcm53573
additionalProperties: true
...

49
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -909,6 +909,7 @@ properties:
- fsl,imx8mm-evk # i.MX8MM EVK Board
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
- gateworks,imx8mm-gw7904
- gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
@ -1031,10 +1032,11 @@ properties:
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- polyhex,imx8mp-debix # Polyhex Debix boards
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
@ -1068,6 +1070,20 @@ properties:
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
- const: fsl,imx8mp
- description: Polyhex DEBIX i.MX8MP based SBCs
items:
- enum:
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- const: polyhex,imx8mp-debix # Polyhex i.MX8MP Debix SBCs
- const: fsl,imx8mp
- description: Polyhex DEBIX i.MX8MP SOM A based boards
items:
- enum:
- polyhex,imx8mp-debix-som-a-bmb-08 # Polyhex Debix SOM A on SOM A I/O board
- const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A
- const: fsl,imx8mp
- description: Toradex Boards with Verdin iMX8M Plus Modules
items:
- enum:
@ -1219,6 +1235,25 @@ properties:
- fsl,imxrt1170-evk # i.MXRT1170 EVK Board
- const: fsl,imxrt1170
- description:
TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM
using NXP i.MX93 SOC in 11x11 mm package.
TQMa93xxLA is designed to be soldered on different carrier boards.
TQMa93xxCA is a compatible variant using board to board connectors.
All SOM and CPU variants use the same device tree hence only one
compatible is needed. Bootloader disables all features not present
in the assembled SOC.
MBa93xxCA mainboard can be used as starterkit for the SOM
soldered on an adapter board or for the connector variant
MBa93xxLA mainboard is a single board computer using the solderable
SOM variant
items:
- enum:
- tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA
- tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
- const: fsl,imx93
- description:
Freescale Vybrid Platform Device Tree Bindings
@ -1289,6 +1324,16 @@ properties:
- fsl,ls1021a-twr
- const: fsl,ls1021a
- description:
TQ-Systems TQMLS102xA is a series of socketable SOM featuring
LS102x system-on-chip variants. MBLS102xA mainboard can be used as
starterkit.
items:
- enum:
- tq,ls1021a-tqmls1021a-mbls102xa
- const: tq,ls1021a-tqmls1021a
- const: fsl,ls1021a
- description: LS1028A based Boards
items:
- enum:

5
Documentation/devicetree/bindings/arm/intel,socfpga.yaml
View File

@ -21,6 +21,11 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
- description: Agilex5 boards
items:
- enum:
- intel,socfpga-agilex5-socdk
- const: intel,socfpga-agilex5
additionalProperties: true

99
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@ -41,14 +41,6 @@ SoC Type (optional):
SoC Families:
- OMAP2 generic - defaults to OMAP2420
compatible = "ti,omap2"
- OMAP3 generic
compatible = "ti,omap3"
- OMAP4 generic - defaults to OMAP4430
compatible = "ti,omap4"
- OMAP5 generic - defaults to OMAP5430
compatible = "ti,omap5"
- DRA7 generic - defaults to DRA742
compatible = "ti,dra7"
- AM33x generic
@ -58,32 +50,6 @@ SoC Families:
SoCs:
- OMAP2420
compatible = "ti,omap2420", "ti,omap2"
- OMAP2430
compatible = "ti,omap2430", "ti,omap2"
- OMAP3430
compatible = "ti,omap3430", "ti,omap3"
legacy: "ti,omap34xx" - please do not use any more
- AM3517
compatible = "ti,am3517", "ti,omap3"
- OMAP3630
compatible = "ti,omap3630", "ti,omap3"
legacy: "ti,omap36xx" - please do not use any more
- AM335x
compatible = "ti,am33xx"
- OMAP4430
compatible = "ti,omap4430", "ti,omap4"
- OMAP4460
compatible = "ti,omap4460", "ti,omap4"
- OMAP5430
compatible = "ti,omap5430", "ti,omap5"
- OMAP5432
compatible = "ti,omap5432", "ti,omap5"
- DRA762
compatible = "ti,dra762", "ti,dra7"
@ -116,65 +82,6 @@ SoCs:
Boards (incomplete list of examples):
- OMAP3 BeagleBoard : Low cost community board
compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk
compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"
- OMAP4 SDP : Software Development Board
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"
- OMAP4 PandaBoard : Low cost community board
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN
compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen
compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
compatible = "ti,omap3-evm", "ti,omap3630", "ti,omap3"
- AM335X EVM : Software Development Board for AM335x
compatible = "ti,am335x-evm", "ti,am33xx"
- AM335X Bone : Low cost community board
compatible = "ti,am335x-bone", "ti,am33xx"
- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
compatible = "ti,am3359-icev2", "ti,am33xx"
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
- AM335X phyBOARD-WEGA: Single Board Computer dev kit
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4
compatible = "compulab,cm-t335", "ti,am33xx"
- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
- AM335X phyCORE-AM335x: Development kit
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335x phyBOARD-REGOR: Single Board Computer
compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
compatible = "moxa,uc-8100-me-t", "ti,am33xx";
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
- AM437x CM-T43
compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
@ -217,9 +124,3 @@ Boards (incomplete list of examples):
- DRA718 EVM: Software Development Board for DRA718
compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"
- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"

2
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@ -31,7 +31,7 @@ properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$"
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,

14
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
ipq5018
ipq5332
ipq6018
ipq8074
@ -72,6 +73,7 @@ description: |
sdx65
sdx75
sm4250
sm4450
sm6115
sm6115p
sm6125
@ -104,6 +106,7 @@ description: |
hk10-c2
idp
liquid
rdp432-c2
mtp
qrd
rb2
@ -186,6 +189,7 @@ properties:
- items:
- enum:
- samsung,a7
- sony,kanuti-tulip
- square,apq8039-t2
- const: qcom,msm8939
@ -339,6 +343,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
- items:
- enum:
- qcom,ipq5018-rdp432-c2
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
@ -902,6 +911,11 @@ properties:
- const: qcom,qrb4210
- const: qcom,sm4250
- items:
- enum:
- qcom,sm4450-qrd
- const: qcom,sm4450
- items:
- enum:
- fxtec,pro1x

15
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -196,6 +196,11 @@ properties:
- const: firefly,rk3566-roc-pc
- const: rockchip,rk3566
- description: Firefly Station P2
items:
- const: firefly,rk3568-roc-pc
- const: rockchip,rk3568
- description: FriendlyElec NanoPi R2 series boards
items:
- enum:
@ -222,6 +227,11 @@ properties:
- friendlyarm,nanopi-r5s
- const: rockchip,rk3568
- description: FriendlyElec NanoPC T6
items:
- const: friendlyarm,nanopc-t6
- const: rockchip,rk3588
- description: GeekBuying GeekBox
items:
- const: geekbuying,geekbox
@ -694,6 +704,11 @@ properties:
- const: radxa,rock-4c-plus
- const: rockchip,rk3399
- description: Radxa ROCK 4SE
items:
- const: radxa,rock-4se
- const: rockchip,rk3399
- description: Radxa ROCK Pi E
items:
- const: radxa,rockpi-e

4
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@ -143,7 +143,9 @@ properties:
- description: Octavo OSD32MP15x System-in-Package based boards
items:
- enum:
- lxa,stm32mp157c-mc1 # Linux Automation MC-1
- lxa,stm32mp157c-mc1 # Linux Automation MC-1
- lxa,stm32mp157c-tac-gen1 # Linux Automation TAC (Generation 1)
- lxa,stm32mp157c-tac-gen2 # Linux Automation TAC (Generation 2)
- const: oct,stm32mp15xx-osd32
- enum:
- st,stm32mp157

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -997,4 +997,9 @@ properties:
- const: xunlong,orangepi-zero2
- const: allwinner,sun50i-h616
- description: Xunlong OrangePi Zero 3
items:
- const: xunlong,orangepi-zero3
- const: allwinner,sun50i-h618
additionalProperties: true

21
Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt
View File

@ -1,21 +0,0 @@
NVIDIA compliant embedded controller
Required properties:
- compatible : should be "nvidia,nvec".
- reg : the iomem of the i2c slave controller
- interrupts : the interrupt line of the i2c slave controller
- clock-frequency : the frequency of the i2c bus
- gpios : the gpio used for ec request
- slave-addr: the i2c address of the slave controller
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
Tegra20/Tegra30:
- div-clk
- fast-clk
Tegra114:
- div-clk
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- i2c

17
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt
View File

@ -1,17 +0,0 @@
NVIDIA Tegra AHB
Required properties:
- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
'"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
tegra132, or tegra210.
- reg : Should contain 1 register ranges(address and length). For
Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
be be <0x6000c000 0x150>.
Example (for a Tegra20 chip):
ahb: ahb@6000c004 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
};

18
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
View File

@ -1,18 +0,0 @@
NVIDIA Tegra Flow Controller
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra20-flowctrl": for Tegra20
- "nvidia,tegra30-flowctrl": for Tegra30
- "nvidia,tegra114-flowctrl": for Tegra114
- "nvidia,tegra124-flowctrl": for Tegra124
- "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
- "nvidia,tegra210-flowctrl": for Tegra210
- reg: Should contain one register range (address and length)
Example:
flow-controller@60007000 {
compatible = "nvidia,tegra20-flowctrl";
reg = <0x60007000 0x1000>;
};

13
Documentation/devicetree/bindings/arm/ti/k3.yaml
View File

@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM62P5 SoC and Boards
items:
- enum:
- ti,am62p5-sk
- const: ti,am62p5
- description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am625-phyboard-lyra-rdk
@ -72,6 +78,13 @@ properties:
- const: phytec,am64-phycore-som
- const: ti,am642
- description: K3 AM642 SoC on TQ-Systems TQMaX4XxL SoM
items:
- enum:
- tq,am642-tqma6442l-mbax4xxl # MBaX4XxL base board
- const: tq,am642-tqma6442l
- const: ti,am642
- description: K3 AM654 SoC
items:
- enum:

176
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@ -0,0 +1,176 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/omap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments OMAP SoC architecture
maintainers:
- Tony Lindgren <tony@atomide.com>
description: Platforms based on Texas Instruments OMAP SoC architecture.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: TI OMAP2420 SoC based platforms
items:
- enum:
- nokia,n800
- nokia,n810
- nokia,n810-wimax
- ti,omap2420-h4
- const: ti,omap2420
- const: ti,omap2
- description: TI OMAP2430 SoC based platforms
items:
- enum:
- ti,omap2430-sdp # TI OMAP2430 SDP
- const: ti,omap2430
- const: ti,omap2
- description: TI OMAP3430 SoC based platforms
items:
- enum:
- compulab,omap3-cm-t3530
- logicpd,dm3730-som-lv-devkit # LogicPD Zoom OMAP35xx SOM-LV Development Kit
- logicpd,dm3730-torpedo-devkit # LogicPD Zoom OMAP35xx Torpedo Development Kit
- nokia,omap3-n900
- openpandora,omap3-pandora-600mhz
- ti,omap3430-sdp
- ti,omap3-beagle
- ti,omap3-evm # TI OMAP35XX EVM (TMDSEVM3530)
- ti,omap3-ldp # TI OMAP3430 LDP (Zoom1 Labrador)
- timll,omap3-devkit8000
- const: ti,omap3430
- const: ti,omap3
- description: Early BeagleBoard revisions A to B4 with a timer quirk
items:
- const: ti,omap3-beagle-ab4
- const: ti,omap3-beagle
- const: ti,omap3430
- const: ti,omap3
- description: Gumstix Overo TI OMAP 3430/3630 boards + expansion boards
items:
- enum:
- gumstix,omap3-overo-alto35
- gumstix,omap3-overo-chestnut43
- gumstix,omap3-overo-gallop43
- gumstix,omap3-overo-palo35
- gumstix,omap3-overo-palo43
- gumstix,omap3-overo-summit
- gumstix,omap3-overo-tobi
- gumstix,omap3-overo-tobiduo
- const: gumstix,omap3-overo
- enum:
- ti,omap3430
- ti,omap3630
- description: TI OMAP3630 SoC based platforms
items:
- enum:
- amazon,omap3-echo # Amazon Echo (first generation)
- compulab,omap3-cm-t3730
- goldelico,gta04
- lg,omap3-sniper # LG Optimus Black
- logicpd,dm3730-som-lv-devkit # LogicPD Zoom DM3730 SOM-LV Development Kit
- logicpd,dm3730-torpedo-devkit # LogicPD Zoom DM3730 Torpedo + Wireless Development Kit
- nokia,omap3-n9
- nokia,omap3-n950
- openpandora,omap3-pandora-1ghz
- ti,omap3-beagle-xm
- ti,omap3-evm-37xx # TI OMAP37XX EVM (TMDSEVM3730)
- ti,omap3-zoom3
- const: ti,omap3630
- const: ti,omap3
- description: TI AM35 SoC based platforms
items:
- enum:
- compulab,omap3-sbc-t3517 # CompuLab SBC-T3517 with CM-T3517
- teejet,mt_ventoux
- ti,am3517-craneboard # TI AM3517 CraneBoard (TMDSEVM3517)
- ti,am3517-evm # TI AM3517 EVM (AM3517/05 TMDSEVM3517)
- const: ti,am3517
- const: ti,omap3
- description: TI AM33 based platform
items:
- enum:
- compulab,cm-t335
- moxa,uc-8100-me-t
- novatech,am335x-lxm
- ti,am335x-bone
- ti,am335x-evm
- ti,am3359-icev2
- const: ti,am33xx
- description: Compulab board variants based on TI AM33
items:
- enum:
- compulab,sbc-t335
- const: compulab,cm-t335
- const: ti,am33xx
- description: Phytec boards based on TI AM33
items:
- enum:
- phytec,am335x-wega
- phytec,am335x-pcm-953
- phytec,am335x-regor
- const: phytec,am335x-phycore-som
- const: ti,am33xx
- description: TI OMAP4430 SoC based platforms
items:
- enum:
- amazon,omap4-kc1 # Amazon Kindle Fire (first generation)
- motorola,droid4 # Motorola Droid 4 XT894
- motorola,droid-bionic # Motorola Droid Bionic XT875
- ti,omap4-panda
- ti,omap4-sdp
- const: ti,omap4430
- const: ti,omap4
- description: OMAP4 DuoVero with Parlor expansion board/daughter board
items:
- const: gumstix,omap4-duovero-parlor
- const: gumstix,omap4-duovero
- const: ti,omap4430
- const: ti,omap4
- description: TI OMAP4460 SoC based platforms
items:
- enum:
- epson,embt2ws # Epson Moverio BT-200
- ti,omap4-panda-es
- const: ti,omap4460
- const: ti,omap4
- description: VAR-OM44 boards
items:
- enum:
- variscite,var-dvk-om44
- variscite,var-stk-om44
- const: variscite,var-som-om44
- const: ti,omap4460
- const: ti,omap4
- description: TI OMAP5 SoC based platforms
items:
- enum:
- compulab,omap5-cm-t54
- isee,omap5-igep0050
- ti,omap5-uevm
- const: ti,omap5
additionalProperties: true
...

40
Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml Normal file
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@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA Agilex5 clock manager
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description:
The Intel Agilex5 Clock Manager is an integrated clock controller, which
generates and supplies clock to all the modules.
properties:
compatible:
const: intel,agilex5-clkmgr
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
#clock-cells = <1>;
};
...

4
Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml
View File

@ -27,7 +27,9 @@ description: |
properties:
compatible:
const: nvidia,tegra124-car
enum:
- nvidia,tegra124-car
- nvidia,tegra132-car
reg:
maxItems: 1

63
Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml Normal file
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5018
maintainers:
- Sricharan Ramabadhran <quic_srichara@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5018
See also::
include/dt-bindings/clock/qcom,ipq5018-gcc.h
include/dt-bindings/reset/qcom,ipq5018-gcc.h
properties:
compatible:
const: qcom,gcc-ipq5018
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE20 PHY0 pipe clock source
- description: PCIE20 PHY1 pipe clock source
- description: USB3 PHY pipe clock source
- description: GEPHY RX clock source
- description: GEPHY TX clock source
- description: UNIPHY RX clock source
- description: UNIPHY TX clk source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq5018";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&pcie20_phy0_pipe_clk>,
<&pcie20_phy1_pipe_clk>,
<&usb3_phy0_pipe_clk>,
<&gephy_rx_clk>,
<&gephy_tx_clk>,
<&uniphy_rx_clk>,
<&uniphy_tx_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

87
Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml Normal file
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@ -0,0 +1,87 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
maintainers:
- Xingyu Wu <xingyu.wu@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-ispcrg
reg:
maxItems: 1
clocks:
items:
- description: ISP Top core
- description: ISP Top Axi
- description: NOC ISP Bus
- description: external DVP
clock-names:
items:
- const: isp_top_core
- const: isp_top_axi
- const: noc_bus_isp_axi
- const: dvp_clk
resets:
items:
- description: ISP Top core
- description: ISP Top Axi
- description: NOC ISP Bus
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
'#reset-cells':
const: 1
description:
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
power-domains:
maxItems: 1
description:
ISP domain power
required:
- compatible
- reg
- clocks
- clock-names
- resets
- '#clock-cells'
- '#reset-cells'
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/power/starfive,jh7110-pmu.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
ispcrg: clock-controller@19810000 {
compatible = "starfive,jh7110-ispcrg";
reg = <0x19810000 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
<&dvp_clk>;
clock-names = "isp_top_core", "isp_top_axi",
"noc_bus_isp_axi", "dvp_clk";
resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
#clock-cells = <1>;
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_ISP>;
};

46
Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 PLL Clock Generator
description:
These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
Each PLL works in integer mode or fraction mode, with configuration
registers in the sys syscon. So the PLLs node should be a child of
SYS-SYSCON node.
The formula for calculating frequency is
Fvco = Fref * (NI + NF) / M / Q1
maintainers:
- Xingyu Wu <xingyu.wu@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-pll
clocks:
maxItems: 1
description: Main Oscillator (24 MHz)
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
required:
- compatible
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller {
compatible = "starfive,jh7110-pll";
clocks = <&osc>;
#clock-cells = <1>;
};

82
Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml Normal file
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@ -0,0 +1,82 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 System-Top-Group Clock and Reset Generator
maintainers:
- Xingyu Wu <xingyu.wu@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-stgcrg
reg:
maxItems: 1
clocks:
items:
- description: Main Oscillator (24 MHz)
- description: HIFI4 core
- description: STG AXI/AHB
- description: USB (125 MHz)
- description: CPU Bus
- description: HIFI4 Axi
- description: NOC STG Bus
- description: APB Bus
clock-names:
items:
- const: osc
- const: hifi4_core
- const: stg_axiahb
- const: usb_125m
- const: cpu_bus
- const: hifi4_axi
- const: nocstg_bus
- const: apb_bus
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
'#reset-cells':
const: 1
description:
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/starfive,jh7110-crg.h>
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x10230000 0x10000>;
clocks = <&osc>,
<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
<&syscrg JH7110_SYSCLK_USB_125M>,
<&syscrg JH7110_SYSCLK_CPU_BUS>,
<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
<&syscrg JH7110_SYSCLK_APB_BUS>;
clock-names = "osc", "hifi4_core",
"stg_axiahb", "usb_125m",
"cpu_bus", "hifi4_axi",
"nocstg_bus", "apb_bus";
#clock-cells = <1>;
#reset-cells = <1>;
};

18
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
View File

@ -27,6 +27,9 @@ properties:
- description: External I2S RX left/right channel clock
- description: External TDM clock
- description: External audio master clock
- description: PLL0
- description: PLL1
- description: PLL2
- items:
- description: Main Oscillator (24 MHz)
@ -38,6 +41,9 @@ properties:
- description: External I2S RX left/right channel clock
- description: External TDM clock
- description: External audio master clock
- description: PLL0
- description: PLL1
- description: PLL2
clock-names:
oneOf:
@ -52,6 +58,9 @@ properties:
- const: i2srx_lrck_ext
- const: tdm_ext
- const: mclk_ext
- const: pll0_out
- const: pll1_out
- const: pll2_out
- items:
- const: osc
@ -63,6 +72,9 @@ properties:
- const: i2srx_lrck_ext
- const: tdm_ext
- const: mclk_ext
- const: pll0_out
- const: pll1_out
- const: pll2_out
'#clock-cells':
const: 1
@ -93,12 +105,14 @@ examples:
<&gmac1_rgmii_rxin>,
<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>;
<&tdm_ext>, <&mclk_ext>,
<&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
"i2stx_bclk_ext", "i2stx_lrck_ext",
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext";
"tdm_ext", "mclk_ext",
"pll0_out", "pll1_out", "pll2_out";
#clock-cells = <1>;
#reset-cells = <1>;
};

90
Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml Normal file
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@ -0,0 +1,90 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 Video-Output Clock and Reset Generator
maintainers:
- Xingyu Wu <xingyu.wu@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-voutcrg
reg:
maxItems: 1
clocks:
items:
- description: Vout Top core
- description: Vout Top Ahb
- description: Vout Top Axi
- description: Vout Top HDMI MCLK
- description: I2STX0 BCLK
- description: external HDMI pixel
clock-names:
items:
- const: vout_src
- const: vout_top_ahb
- const: vout_top_axi
- const: vout_top_hdmitx0_mclk
- const: i2stx0_bclk
- const: hdmitx0_pixelclk
resets:
maxItems: 1
description: Vout Top core
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
'#reset-cells':
const: 1
description:
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
power-domains:
maxItems: 1
description:
Vout domain power
required:
- compatible
- reg
- clocks
- clock-names
- resets
- '#clock-cells'
- '#reset-cells'
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/power/starfive,jh7110-pmu.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
voutcrg: clock-controller@295C0000 {
compatible = "starfive,jh7110-voutcrg";
reg = <0x295C0000 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
<&hdmitx0_pixelclk>;
clock-names = "vout_src", "vout_top_ahb",
"vout_top_axi", "vout_top_hdmitx0_mclk",
"i2stx0_bclk", "hdmitx0_pixelclk";
resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_VOUT>;
};

37
Documentation/devicetree/bindings/cpu/nvidia,tegra186-ccplex-cluster.yaml Normal file
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@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cpu/nvidia,tegra186-ccplex-cluster.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 CCPLEX Cluster
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra186-ccplex-cluster
reg:
maxItems: 1
nvidia,bpmp:
description: phandle to the BPMP used to query CPU frequency tables
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: false
required:
- compatible
- reg
- nvidia,bpmp
examples:
- |
ccplex@e000000 {
compatible = "nvidia,tegra186-ccplex-cluster";
reg = <0x0e000000 0x400000>;
nvidia,bpmp = <&bpmp>;
};

14
Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml
View File

@ -66,10 +66,22 @@ patternProperties:
required:
- compatible
- reg
- power-domains
- dmas
- dma-names
allOf:
- if:
properties:
compatible:
contains:
const: ti,am62-sa3ul
then:
properties:
power-domains: false
else:
required:
- power-domains
additionalProperties: false
examples:

3
Documentation/devicetree/bindings/eeprom/at24.yaml
View File

@ -101,6 +101,9 @@ properties:
pattern: spd$
# These are special cases that don't conform to the above pattern.
# Each requires a standard at24 model as fallback.
- items:
- const: belling,bl24c16a
- const: atmel,24c16
- items:
- enum:
- rohm,br24g01

39
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
View File

@ -57,8 +57,11 @@ description: |
"#address-cells" or "#size-cells" property.
The shared memory area for the IPC TX and RX between CPU and BPMP are
predefined and work on top of sysram, which is an SRAM inside the
chip. See ".../sram/sram.yaml" for the bindings.
predefined and work on top of either sysram, which is an SRAM inside the
chip, or in normal SDRAM.
See ".../sram/sram.yaml" for the bindings for the SRAM case.
See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
the SDRAM case.
properties:
compatible:
@ -81,6 +84,11 @@ properties:
minItems: 2
maxItems: 2
memory-region:
description: phandle to reserved memory region used for IPC between
CPU-NS and BPMP.
maxItems: 1
"#clock-cells":
const: 1
@ -115,10 +123,15 @@ properties:
additionalProperties: false
oneOf:
- required:
- memory-region
- required:
- shmem
required:
- compatible
- mboxes
- shmem
- "#clock-cells"
- "#power-domain-cells"
- "#reset-cells"
@ -165,8 +178,7 @@ examples:
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#power-domain-cells = <1>;
@ -184,3 +196,20 @@ examples:
#thermal-sensor-cells = <1>;
};
};
- |
#include <dt-bindings/mailbox/tegra186-hsp.h>
bpmp {
compatible = "nvidia,tegra186-bpmp";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
memory-region = <&dram_cpu_bpmp_mail>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
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@ -126,7 +126,7 @@ required:
- clock-names
- bosch,mram-cfg
additionalProperties: false
unevaluatedProperties: false
examples:
- |

3
Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
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@ -49,6 +49,9 @@ properties:
Set if the output SYNCLKO clock should be disabled. Do not mix with
microchip,synclko-125.
interrupts:
maxItems: 1
required:
- compatible
- reg

17
Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
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@ -20,12 +20,17 @@ description: |+
properties:
compatible:
enum:
- samsung,s3c2410-pwm # 16-bit, S3C24xx
- samsung,s3c6400-pwm # 32-bit, S3C64xx
- samsung,s5p6440-pwm # 32-bit, S5P64x0
- samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
- samsung,exynos4210-pwm # 32-bit, Exynos
oneOf:
- enum:
- samsung,s3c2410-pwm # 16-bit, S3C24xx
- samsung,s3c6400-pwm # 32-bit, S3C64xx
- samsung,s5p6440-pwm # 32-bit, S5P64x0
- samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
- samsung,exynos4210-pwm # 32-bit, Exynos
- items:
- enum:
- samsung,exynosautov9-pwm
- const: samsung,exynos4210-pwm
reg:
maxItems: 1

47
Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml Normal file
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@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra CPU-NS - BPMP IPC reserved memory
maintainers:
- Peter De Schrijver <pdeschrijver@nvidia.com>
description: |
Define a memory region used for communication between CPU-NS and BPMP.
Typically this node is created by the bootloader as the physical address
has to be known to both CPU-NS and BPMP for correct IPC operation.
The memory region is defined using a child node under /reserved-memory.
The sub-node is named shmem@<address>.
allOf:
- $ref: reserved-memory.yaml
properties:
compatible:
const: nvidia,tegra264-bpmp-shmem
reg:
description: The physical address and size of the shared SDRAM region
unevaluatedProperties: false
required:
- compatible
- reg
- no-map
examples:
- |
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
dram_cpu_bpmp_mail: shmem@f1be0000 {
compatible = "nvidia,tegra264-bpmp-shmem";
reg = <0x0 0xf1be0000 0x0 0x2000>;
no-map;
};
};
...

4
Documentation/devicetree/bindings/riscv/thead.yaml
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@ -17,6 +17,10 @@ properties:
const: '/'
compatible:
oneOf:
- description: BeagleV Ahead single board computer
items:
- const: beagle,beaglev-ahead
- const: thead,th1520
- description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
items:
- enum:

73
Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
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@ -1,73 +0,0 @@
NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
Required properties:
- compatible : should be,
"nvidia,tegra20-hsuart" for Tegra20,
"nvidia,tegra30-hsuart" for Tegra30,
"nvidia,tegra186-hsuart" for Tegra186,
"nvidia,tegra194-hsuart" for Tegra194.
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- serial
- dmas : Must contain an entry for each entry in dma-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
Optional properties:
- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
only if all 8 lines of UART controller are pinmuxed.
- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate
adjustment within a range.
Each entry contains sets of 3 values. Range low/high and adjusted rate.
<range_low range_high adjusted_rate>
When baud rate set on controller falls within the range mentioned in this
field, baud rate will be adjusted by percentage mentioned here.
Ex: <9600 115200 200>
Increase baud rate by 2% when set baud rate falls within range 9600 to 115200
Baud Rate tolerance:
Standard UART devices are expected to have tolerance for baud rate error by
-4 to +4 %. All Tegra devices till Tegra210 had this support. However,
Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level
is 0% to +4% in 1-stop config. Otherwise, the received data will have
corruption/invalid framing errors. Parker errata suggests adjusting baud
rate to be higher than the deviations observed in Tx.
Tx deviation of connected device can be captured over scope (or noted from
its spec) for valid range and Tegra baud rate has to be set above actual
Tx baud rate observed. To do this we use nvidia,adjust-baud-rates
As an example, consider there is deviation observed in Tx for baud rates as
listed below.
0 to 9600 has 1% deviation
9600 to 115200 2% deviation
This slight deviation is expcted and Tegra UART is expected to handle it. Due
to the issue stated above, baud rate on Tegra UART should be set equal to or
above deviation observed for avoiding frame errors.
Property should be set like this
nvidia,adjust-baud-rates = <0 9600 100>,
<9600 115200 200>;
Example:
serial@70006000 {
compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
nvidia,enable-modem-interrupt;
clocks = <&tegra_car 6>;
resets = <&tegra_car 6>;
reset-names = "serial";
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */
};

125
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@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/nvidia,tegra20-hsuart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-hsuart
- nvidia,tegra30-hsuart
- nvidia,tegra186-hsuart
- nvidia,tegra194-hsuart
- items:
- const: nvidia,tegra124-hsuart
- const: nvidia,tegra30-hsuart
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
resets:
items:
- description: module reset
reset-names:
items:
- const: serial
dmas:
items:
- description: DMA channel used for reception
- description: DMA channel used for transmission
dma-names:
items:
- const: rx
- const: tx
nvidia,enable-modem-interrupt:
$ref: /schemas/types.yaml#/definitions/flag
description: Enable modem interrupts. Should be enable only if all 8 lines of UART controller
are pinmuxed.
nvidia,adjust-baud-rates:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
List of entries providing percentage of baud rate adjustment within a range. Each entry
contains a set of 3 values: range low/high and adjusted rate. When the baud rate set on the
controller falls within the range mentioned in this field, the baud rate will be adjusted by
percentage mentioned here.
Example: <9600 115200 200>
Increase baud rate by 2% when set baud rate falls within range 9600 to 115200.
Standard UART devices are expected to have tolerance for baud rate error by -4 to +4 %. All
Tegra devices till Tegra210 had this support. However, Tegra186 chip has a known hardware
issue. UART RX baud rate tolerance level is 0% to +4% in 1-stop config. Otherwise, the
received data will have corruption/invalid framing errors. Parker errata suggests adjusting
baud rate to be higher than the deviations observed in TX.
TX deviation of connected device can be captured over scope (or noted from its spec) for
valid range and Tegra baud rate has to be set above actual TX baud rate observed. To do this
we use nvidia,adjust-baud-rates.
As an example, consider there is deviation observed in TX for baud rates as listed below. 0
to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expcted and
Tegra UART is expected to handle it. Due to the issue stated above, baud rate on Tegra UART
should be set equal to or above deviation observed for avoiding frame errors. Property
should be set like this:
nvidia,adjust-baud-rates = <0 9600 100>,
<9600 115200 200>;
items:
items:
- description: range lower bound
- description: range upper bound
- description: adjustment (in permyriad, i.e. 0.01%)
allOf:
- $ref: serial.yaml
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- resets
- reset-names
- dmas
- dma-names
examples:
- |
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
serial@70006000 {
compatible = "nvidia,tegra30-hsuart";
reg = <0x70006000 0x40>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
nvidia,enable-modem-interrupt;
clocks = <&tegra_car TEGRA30_CLK_UARTA>;
resets = <&tegra_car 6>;
reset-names = "serial";
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */
};

93
Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml Normal file
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@ -0,0 +1,93 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 SoC system controller
maintainers:
- William Qiu <william.qiu@starfivetech.com>
description:
The StarFive JH7110 SoC system controller provides register information such
as offset, mask and shift to configure related modules such as MMC and PCIe.
properties:
compatible:
oneOf:
- items:
- const: starfive,jh7110-sys-syscon
- const: syscon
- const: simple-mfd
- items:
- enum:
- starfive,jh7110-aon-syscon
- starfive,jh7110-stg-syscon
- const: syscon
reg:
maxItems: 1
clock-controller:
$ref: /schemas/clock/starfive,jh7110-pll.yaml#
type: object
"#power-domain-cells":
const: 1
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
const: starfive,jh7110-sys-syscon
then:
required:
- clock-controller
else:
properties:
clock-controller: false
- if:
properties:
compatible:
contains:
const: starfive,jh7110-aon-syscon
then:
required:
- "#power-domain-cells"
else:
properties:
"#power-domain-cells": false
additionalProperties: false
examples:
- |
syscon@10240000 {
compatible = "starfive,jh7110-stg-syscon", "syscon";
reg = <0x10240000 0x1000>;
};
syscon@13030000 {
compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
reg = <0x13030000 0x1000>;
clock-controller {
compatible = "starfive,jh7110-pll";
clocks = <&osc>;
#clock-cells = <1>;
};
};
syscon@17010000 {
compatible = "starfive,jh7110-aon-syscon", "syscon";
reg = <0x17010000 0x1000>;
#power-domain-cells = <1>;
};
...

84
Documentation/devicetree/bindings/soc/tegra/nvidia,nvec.yaml Normal file
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@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/tegra/nvidia,nvec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA compliant embedded controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,nvec
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: divider clock
- description: fast clock
clock-names:
minItems: 1
items:
- const: div-clk
- const: fast-clk
resets:
items:
- description: module reset
reset-names:
items:
- const: i2c
clock-frequency: true
request-gpios:
description: phandle to the GPIO used for EC request
slave-addr:
$ref: /schemas/types.yaml#/definitions/uint32
description: I2C address of the slave controller
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- clock-frequency
- request-gpios
- slave-addr
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@7000c500 {
compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <80000>;
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
};

40
Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-ahb.yaml Normal file
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@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
title: NVIDIA Tegra AHB
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-ahb
- nvidia,tegra30-ahb
- items:
- enum:
- nvidia,tegra114-ahb
- nvidia,tegra124-ahb
- nvidia,tegra210-ahb
- const: nvidia,tegra30-ahb
reg:
maxItems: 1
additionalProperties: false
required:
- compatible
- reg
examples:
- |
ahb@6000c004 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
};

41
Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-flowctrl.yaml Normal file
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@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-flowctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Flow Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra20-flowctrl
- nvidia,tegra30-flowctrl
- nvidia,tegra114-flowctrl
- nvidia,tegra124-flowctrl
- nvidia,tegra210-flowctrl
- items:
- const: nvidia,tegra132-flowctrl
- const: nvidia,tegra124-flowctrl
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
flow-controller@60007000 {
compatible = "nvidia,tegra20-flowctrl";
reg = <0x60007000 0x1000>;
};

9
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
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@ -34,18 +34,22 @@ properties:
- const: ti,am654-navss-ringacc
reg:
minItems: 4
items:
- description: real time registers regions
- description: fifos registers regions
- description: proxy gcfg registers regions
- description: proxy target registers regions
- description: configuration registers region
reg-names:
minItems: 4
items:
- const: rt
- const: fifos
- const: proxy_gcfg
- const: proxy_target
- const: cfg
msi-parent: true
@ -80,8 +84,9 @@ examples:
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
<0x0 0x33000000 0x0 0x40000>,
<0x0 0x31080000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
ti,sci = <&dmsc>;

238
Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
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@ -1,238 +0,0 @@
Tegra124 SOCTHERM thermal management system
The SOCTHERM IP block contains thermal sensors, support for polled
or interrupt-based thermal monitoring, CPU and GPU throttling based
on temperature trip points, and handling external overcurrent
notifications. It is also used to manage emergency shutdown in an
overheating situation.
Required properties :
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
For Tegra132, must contain "nvidia,tegra132-soctherm".
For Tegra210, must contain "nvidia,tegra210-soctherm".
- reg : Should contain at least 2 entries for each entry in reg-names:
- SOCTHERM register set
- Tegra CAR register set: Required for Tegra124 and Tegra210.
- CCROC register set: Required for Tegra132.
- reg-names : Should contain at least 2 entries:
- soctherm-reg
- car-reg
- ccroc-reg
- interrupts : Defines the interrupt used by SOCTHERM
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- tsensor
- soctherm
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- soctherm
- #thermal-sensor-cells : Should be 1. For a description of this property, see
Documentation/devicetree/bindings/thermal/thermal-sensor.yaml.
See <dt-bindings/thermal/tegra124-soctherm.h> for a list of valid values
when referring to thermal sensors.
- throttle-cfgs: A sub-node which is a container of configuration for each
hardware throttle events. These events can be set as cooling devices.
* throttle events: Sub-nodes must be named as "light" or "heavy".
Properties:
- nvidia,priority: Each throttles has its own throttle settings, so the
SW need to set priorities for various throttle, the HW arbiter can select
the final throttle settings.
Bigger value indicates higher priority, In general, higher priority
translates to lower target frequency. SW needs to ensure that critical
thermal alarms are given higher priority, and ensure that there is
no race if priority of two vectors is set to the same value.
The range of this value is 1~100.
- nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
It is the throttling depth of pulse skippers, it's the percentage
throttling.
- nvidia,cpu-throt-level: This property is only for Tegra132, it is the
level of pulse skippers, which used to throttle clock frequencies. It
indicates cpu clock throttling depth, and the depth can be programmed.
Must set as following values:
TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
- nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
It is the level of pulse skippers, which used to throttle clock
frequencies. It indicates gpu clock throttling depth and can be
programmed to any of the following values which represent a throttling
percentage:
TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
- #cooling-cells: Should be 1. This cooling device only support on/off state.
For a description of this property see:
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
Optional properties: The following properties are T210 specific and
valid only for OCx throttle events.
- nvidia,count-threshold: Specifies the number of OC events that are
required for triggering an interrupt. Interrupts are not triggered if
the property is missing. A value of 0 will interrupt on every OC alarm.
- nvidia,polarity-active-low: Configures the polarity of the OC alaram
signal. If present, this means assert low, otherwise assert high.
- nvidia,alarm-filter: Number of clocks to filter event. When the filter
expires (which means the OC event has not occurred for a long time),
the counter is cleared and filter is rearmed. Default value is 0.
- nvidia,throttle-period-us: Specifies the number of uSec for which
throttling is engaged after the OC event is deasserted. Default value
is 0.
Optional properties:
- nvidia,thermtrips : When present, this property specifies the temperature at
which the soctherm hardware will assert the thermal trigger signal to the
Power Management IC, which can be configured to reset or shutdown the device.
It is an array of pairs where each pair represents a tsensor id followed by a
temperature in milli Celcius. In the absence of this property the critical
trip point will be used for thermtrip temperature.
Note:
- the "critical" type trip points will be used to set the temperature at which
the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
property is missing. When the thermtrips property is present, the breach of a
critical trip point is reported back to the thermal framework to implement
software shutdown.
- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
temperature. Once the temperature of this thermal zone is higher
than it, it will trigger the HW throttle event.
Example :
soctherm@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
0x0 0x60006000 0x0 0x400 /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
<&tegra_car TEGRA124_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car 78>;
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
throttle-cfgs {
/*
* When the "heavy" cooling device triggered,
* the HW will skip cpu clock's pulse in 85% depth,
* skip gpu clock's pulse in 85% level
*/
throttle_heavy: heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-percent = <85>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <1>;
};
/*
* When the "light" cooling device triggered,
* the HW will skip cpu clock's pulse in 50% depth,
* skip gpu clock's pulse in 50% level
*/
throttle_light: light {
nvidia,priority = <80>;
nvidia,cpu-throt-percent = <50>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
#cooling-cells = <1>;
};
/*
* If these two devices are triggered in same time, the HW throttle
* arbiter will select the highest priority as the final throttle
* settings to skip cpu pulse.
*/
throttle_oc1: oc1 {
nvidia,priority = <50>;
nvidia,polarity-active-low;
nvidia,count-threshold = <100>;
nvidia,alarm-filter = <5100000>;
nvidia,throttle-period-us = <0>;
nvidia,cpu-throt-percent = <75>;
nvidia,gpu-throt-level =
<TEGRA_SOCTHERM_THROT_LEVEL_MED>;
};
};
};
Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
soctherm@700e2000 {
compatible = "nvidia,tegra132-soctherm";
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
reg-names = "soctherm-reg", "ccroc-reg";
throttle-cfgs {
/*
* When the "heavy" cooling device triggered,
* the HW will skip cpu clock's pulse in HIGH level
*/
throttle_heavy: heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <1>;
};
/*
* When the "light" cooling device triggered,
* the HW will skip cpu clock's pulse in MED level
*/
throttle_light: light {
nvidia,priority = <80>;
nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
#cooling-cells = <1>;
};
/*
* If these two devices are triggered in same time, the HW throttle
* arbiter will select the highest priority as the final throttle
* settings to skip cpu pulse.
*/
};
};
Example: referring to thermal sensors :
thermal-zones {
cpu {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
trips {
cpu_shutdown_trip: shutdown-trip {
temperature = <102500>;
hysteresis = <1000>;
type = "critical";
};
cpu_throttle_trip: throttle-trip {
temperature = <100000>;
hysteresis = <1000>;
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&cpu_throttle_trip>;
cooling-device = <&throttle_heavy 1 1>;
};
};
};
};

380
Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml Normal file
View File

@ -0,0 +1,380 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SOCTHERM Thermal Management System
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: The SOCTHERM IP block contains thermal sensors, support for
polled or interrupt-based thermal monitoring, CPU and GPU throttling based
on temperature trip points, and handling external overcurrent notifications.
It is also used to manage emergency shutdown in an overheating situation.
properties:
compatible:
enum:
- nvidia,tegra124-soctherm
- nvidia,tegra132-soctherm
- nvidia,tegra210-soctherm
reg:
maxItems: 2
reg-names:
maxItems: 2
interrupts:
items:
- description: module interrupt
- description: EDP interrupt
interrupt-names:
items:
- const: thermal
- const: edp
clocks:
items:
- description: thermal sensor clock
- description: module clock
clock-names:
items:
- const: tsensor
- const: soctherm
resets:
items:
- description: module reset
reset-names:
items:
- const: soctherm
"#thermal-sensor-cells":
const: 1
throttle-cfgs:
$ref: thermal-cooling-devices.yaml
description: A sub-node which is a container of configuration for each
hardware throttle events. These events can be set as cooling devices.
Throttle event sub-nodes must be named as "light" or "heavy".
unevaluatedProperties: false
patternProperties:
"^(light|heavy|oc1)$":
type: object
properties:
nvidia,priority:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 100
description: Each throttles has its own throttle settings, so the
SW need to set priorities for various throttle, the HW arbiter
can select the final throttle settings. Bigger value indicates
higher priority, In general, higher priority translates to lower
target frequency. SW needs to ensure that critical thermal
alarms are given higher priority, and ensure that there is no
race if priority of two vectors is set to the same value.
nvidia,cpu-throt-percent:
description: This property is for Tegra124 and Tegra210. It is the
throttling depth of pulse skippers, it's the percentage
throttling.
minimum: 0
maximum: 100
nvidia,cpu-throt-level:
$ref: /schemas/types.yaml#/definitions/uint32
description: This property is only for Tegra132, it is the level
of pulse skippers, which used to throttle clock frequencies. It
indicates cpu clock throttling depth, and the depth can be
programmed.
enum:
# none (TEGRA_SOCTHERM_THROT_LEVEL_NONE)
- 0
# low (TEGRA_SOCTHERM_THROT_LEVEL_LOW)
- 1
# medium (TEGRA_SOCTHERM_THROT_LEVEL_MED)
- 2
# high (TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
- 3
nvidia,gpu-throt-level:
$ref: /schemas/types.yaml#/definitions/uint32
description: This property is for Tegra124 and Tegra210. It is the
level of pulse skippers, which used to throttle clock
frequencies. It indicates gpu clock throttling depth and can be
programmed to any of the following values which represent a
throttling percentage.
enum:
# none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE)
- 0
# low (50%, TEGRA_SOCTHERM_THROT_LEVEL_LOW)
- 1
# medium (75%, TEGRA_SOCTHERM_THROT_LEVEL_MED)
- 2
# high (85%, TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
- 3
# optional
# Tegra210 specific and valid only for OCx throttle events
nvidia,count-threshold:
$ref: /schemas/types.yaml#/definitions/uint32
description: Specifies the number of OC events that are required
for triggering an interrupt. Interrupts are not triggered if the
property is missing. A value of 0 will interrupt on every OC
alarm.
nvidia,polarity-active-low:
$ref: /schemas/types.yaml#/definitions/flag
description: Configures the polarity of the OC alaram signal. If
present, this means assert low, otherwise assert high.
nvidia,alarm-filter:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of clocks to filter event. When the filter
expires (which means the OC event has not occurred for a long
time), the counter is cleared and filter is rearmed.
default: 0
nvidia,throttle-period-us:
description: Specifies the number of microseconds for which
throttling is engaged after the OC event is deasserted.
default: 0
# optional
nvidia,thermtrips:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
When present, this property specifies the temperature at which the
SOCTHERM hardware will assert the thermal trigger signal to the Power
Management IC, which can be configured to reset or shutdown the device.
It is an array of pairs where each pair represents a tsensor ID followed
by a temperature in milli Celcius. In the absence of this property the
critical trip point will be used for thermtrip temperature.
Note:
- the "critical" type trip points will be used to set the temperature at
which the SOCTHERM hardware will assert a thermal trigger if the
"nvidia,thermtrips" property is missing. When the thermtrips property
is present, the breach of a critical trip point is reported back to
the thermal framework to implement software shutdown.
- the "hot" type trip points will be set to SOCTHERM hardware as the
throttle temperature. Once the temperature of this thermal zone is
higher than it, it will trigger the HW throttle event.
items:
items:
- description: sensor ID
oneOf:
- description: CPU sensor
const: 0
- description: MEM sensor
const: 1
- description: GPU sensor
const: 2
- description: PLLX sensor
const: 3
- description: temperature threshold (in millidegree Celsius)
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
- resets
- reset-names
- "#thermal-sensor-cells"
allOf:
- $ref: thermal-sensor.yaml
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-soctherm
- nvidia,tegra210-soctherm
then:
properties:
reg:
items:
- description: SOCTHERM register set
- description: clock and reset controller registers
reg-names:
items:
- const: soctherm-reg
- const: car-reg
else:
properties:
reg:
items:
- description: SOCTHERM register set
- description: CCROC registers
reg-names:
items:
- const: soctherm-reg
- const: ccroc-reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
soctherm@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
<0x60006000 0x400>; /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "thermal", "edp";
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
<&tegra_car TEGRA124_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car 78>;
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500>,
<TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
throttle-cfgs {
/*
* When the "heavy" cooling device triggered,
* the HW will skip cpu clock's pulse in 85% depth,
* skip gpu clock's pulse in 85% level
*/
heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-percent = <85>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <2>;
};
/*
* When the "light" cooling device triggered,
* the HW will skip cpu clock's pulse in 50% depth,
* skip gpu clock's pulse in 50% level
*/
light {
nvidia,priority = <80>;
nvidia,cpu-throt-percent = <50>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
#cooling-cells = <2>;
};
/*
* If these two devices are triggered in same time, the HW throttle
* arbiter will select the highest priority as the final throttle
* settings to skip cpu pulse.
*/
oc1 {
nvidia,priority = <50>;
nvidia,polarity-active-low;
nvidia,count-threshold = <100>;
nvidia,alarm-filter = <5100000>;
nvidia,throttle-period-us = <0>;
nvidia,cpu-throt-percent = <75>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
};
};
};
# referring to Tegra132's "reg", "reg-names" and "throttle-cfgs"
- |
thermal-sensor@700e2000 {
compatible = "nvidia,tegra132-soctherm";
reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
<0x70040000 0x200>; /* CCROC reg_base */
reg-names = "soctherm-reg", "ccroc-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "thermal", "edp";
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
<&tegra_car TEGRA124_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car 78>;
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
throttle-cfgs {
/*
* When the "heavy" cooling device triggered,
* the HW will skip cpu clock's pulse in HIGH level
*/
heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <2>;
};
/*
* When the "light" cooling device triggered,
* the HW will skip cpu clock's pulse in MED level
*/
light {
nvidia,priority = <80>;
nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
#cooling-cells = <2>;
};
/*
* If these two devices are triggered in same time, the HW throttle
* arbiter will select the highest priority as the final throttle
* settings to skip cpu pulse.
*/
};
};
# referring to thermal sensors
- |
thermal-zones {
cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
trips {
cpu_shutdown_trip: shutdown-trip {
temperature = <102500>;
hysteresis = <1000>;
type = "critical";
};
cpu_throttle_trip: throttle-trip {
temperature = <100000>;
hysteresis = <1000>;
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&cpu_throttle_trip>;
cooling-device = <&throttle_heavy 1 1>;
};
};
};
};

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -190,6 +190,8 @@ patternProperties:
description: Compass Electronics Group, LLC
"^beagle,.*":
description: BeagleBoard.org Foundation
"^belling,.*":
description: Shanghai Belling Co., Ltd.
"^bhf,.*":
description: Beckhoff Automation GmbH & Co. KG
"^bitmain,.*":

7
MAINTAINERS
View File

@ -20369,6 +20369,12 @@ S: Supported
F: Documentation/devicetree/bindings/mmc/starfive*
F: drivers/mmc/host/dw_mmc-starfive.c
STARFIVE JH7110 SYSCON
M: William Qiu <william.qiu@starfivetech.com>
M: Xingyu Wu <xingyu.wu@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
STARFIVE JH7110 TDM DRIVER
M: Walker Chen <walker.chen@starfivetech.com>
S: Maintained
@ -20418,6 +20424,7 @@ STARFIVE SOC DRIVERS
M: Conor Dooley <conor@kernel.org>
S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: Documentation/devicetree/bindings/soc/starfive/
F: drivers/soc/starfive/
STARFIVE TRNG DRIVER

19
arch/arm/boot/dts/allwinner/Makefile
View File

@ -179,6 +179,25 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-pcduino3-nano.dtb \
sun7i-a20-wexler-tab7200.dtb \
sun7i-a20-wits-pro-a20-dkt.dtb
# Enables support for device-tree overlays for all pis
DTC_FLAGS_sun8i-h3-orangepi-lite := -@
DTC_FLAGS_sun8i-h3-bananapi-m2-plus := -@
DTC_FLAGS_sun8i-h3-nanopi-m1-plus := -@
DTC_FLAGS_sun8i-h3-nanopi-m1 := -@
DTC_FLAGS_sun8i-h3-nanopi-duo2 := -@
DTC_FLAGS_sun8i-h3-orangepi-plus2e := -@
DTC_FLAGS_sun8i-h3-orangepi-one := -@
DTC_FLAGS_sun8i-h3-orangepi-plus := -@
DTC_FLAGS_sun8i-h3-orangepi-2 := -@
DTC_FLAGS_sun8i-h3-orangepi-zero-plus2 := -@
DTC_FLAGS_sun8i-h3-nanopi-neo-air := -@
DTC_FLAGS_sun8i-h3-zeropi := -@
DTC_FLAGS_sun8i-h3-nanopi-neo := -@
DTC_FLAGS_sun8i-h3-nanopi-r1 := -@
DTC_FLAGS_sun8i-h3-orangepi-pc := -@
DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@
DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \

2
arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2022 Arm Ltd.
#include <dt-bindings/interrupt-controller/irq.h>

2
arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2022 Arm Ltd.
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr

2
arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2022 Arm Ltd.
/*
* Common peripherals and configurations for MangoPi MQ-R boards.

2
arch/arm/boot/dts/aspeed/Makefile
View File

@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-wedge400.dtb \
aspeed-bmc-facebook-yamp.dtb \
aspeed-bmc-facebook-yosemitev2.dtb \
aspeed-bmc-facebook-yosemite4.dtb \
aspeed-bmc-ibm-bonnell.dtb \
aspeed-bmc-ibm-everest.dtb \
aspeed-bmc-ibm-rainier.dtb \
@ -53,6 +54,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-quanta-q71l.dtb \
aspeed-bmc-quanta-s6q.dtb \
aspeed-bmc-supermicro-x11spi.dtb \
aspeed-bmc-inventec-starscream.dtb \
aspeed-bmc-inventec-transformers.dtb \
aspeed-bmc-tyan-s7106.dtb \
aspeed-bmc-tyan-s8036.dtb \

129
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
View File

@ -4,12 +4,18 @@
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Ampere Mt.Mitchell BMC";
compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
aliases {
serial7 = &uart8;
serial8 = &uart9;
};
chosen {
stdout-path = &uart5;
};
@ -61,174 +67,192 @@
adc0mux: adc0mux {
compatible = "io-channel-mux";
io-channels = <&adc0 0>;
io-channels = <&adc_i2c_0 0>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc1mux: adc1mux {
compatible = "io-channel-mux";
io-channels = <&adc0 1>;
io-channels = <&adc_i2c_0 1>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc2mux: adc2mux {
compatible = "io-channel-mux";
io-channels = <&adc0 2>;
io-channels = <&adc_i2c_0 2>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc3mux: adc3mux {
compatible = "io-channel-mux";
io-channels = <&adc0 3>;
io-channels = <&adc_i2c_0 3>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc4mux: adc4mux {
compatible = "io-channel-mux";
io-channels = <&adc0 4>;
io-channels = <&adc_i2c_0 4>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc5mux: adc5mux {
compatible = "io-channel-mux";
io-channels = <&adc0 5>;
io-channels = <&adc_i2c_0 5>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc6mux: adc6mux {
compatible = "io-channel-mux";
io-channels = <&adc0 6>;
io-channels = <&adc_i2c_0 6>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc7mux: adc7mux {
compatible = "io-channel-mux";
io-channels = <&adc0 7>;
io-channels = <&adc_i2c_0 7>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc8mux: adc8mux {
compatible = "io-channel-mux";
io-channels = <&adc1 0>;
io-channels = <&adc_i2c_0 8>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc9mux: adc9mux {
compatible = "io-channel-mux";
io-channels = <&adc1 1>;
io-channels = <&adc_i2c_0 9>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc10mux: adc10mux {
compatible = "io-channel-mux";
io-channels = <&adc1 2>;
io-channels = <&adc_i2c_0 10>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc11mux: adc11mux {
compatible = "io-channel-mux";
io-channels = <&adc1 3>;
io-channels = <&adc_i2c_0 11>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc12mux: adc12mux {
compatible = "io-channel-mux";
io-channels = <&adc1 4>;
io-channels = <&adc_i2c_0 12>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc13mux: adc13mux {
compatible = "io-channel-mux";
io-channels = <&adc1 5>;
io-channels = <&adc_i2c_0 13>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc14mux: adc14mux {
compatible = "io-channel-mux";
io-channels = <&adc1 6>;
io-channels = <&adc_i2c_0 14>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
adc15mux: adc15mux {
compatible = "io-channel-mux";
io-channels = <&adc1 7>;
io-channels = <&adc_i2c_0 15>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
settle-time-us = <10000>;
channels = "s0", "s1";
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0mux 0>, <&adc0mux 1>,
<&adc1mux 0>, <&adc1mux 1>,
<&adc2mux 0>, <&adc2mux 1>,
<&adc3mux 0>, <&adc3mux 1>,
<&adc4mux 0>, <&adc4mux 1>,
<&adc5mux 0>, <&adc5mux 1>,
<&adc6mux 0>, <&adc6mux 1>,
<&adc7mux 0>, <&adc7mux 1>,
<&adc8mux 0>, <&adc8mux 1>,
<&adc9mux 0>, <&adc9mux 1>,
<&adc10mux 0>, <&adc10mux 1>,
<&adc11mux 0>, <&adc11mux 1>,
<&adc12mux 0>, <&adc12mux 1>,
<&adc13mux 0>, <&adc13mux 1>,
<&adc14mux 0>, <&adc14mux 1>,
<&adc15mux 0>, <&adc15mux 1>,
<&adc_i2c 0>, <&adc_i2c 1>,
<&adc_i2c 2>, <&adc_i2c 3>,
<&adc_i2c 4>, <&adc_i2c 5>,
<&adc_i2c 6>, <&adc_i2c 7>,
<&adc_i2c 8>, <&adc_i2c 9>,
<&adc_i2c 10>, <&adc_i2c 11>,
<&adc_i2c 12>, <&adc_i2c 13>,
<&adc_i2c 14>, <&adc_i2c 15>;
io-channels = <&adc0mux 0>, <&adc0mux 1>,
<&adc1mux 0>, <&adc1mux 1>,
<&adc2mux 0>, <&adc2mux 1>,
<&adc3mux 0>, <&adc3mux 1>,
<&adc4mux 0>, <&adc4mux 1>,
<&adc5mux 0>, <&adc5mux 1>,
<&adc6mux 0>, <&adc6mux 1>,
<&adc7mux 0>, <&adc7mux 1>,
<&adc8mux 0>, <&adc8mux 1>,
<&adc9mux 0>, <&adc9mux 1>,
<&adc10mux 0>, <&adc10mux 1>,
<&adc11mux 0>, <&adc11mux 1>,
<&adc12mux 0>, <&adc12mux 1>,
<&adc13mux 0>, <&adc13mux 1>,
<&adc14mux 0>, <&adc14mux 1>,
<&adc15mux 0>, <&adc15mux 1>,
<&adc_i2c_1 0>, <&adc_i2c_1 1>,
<&adc_i2c_1 2>, <&adc_i2c_1 3>,
<&adc_i2c_1 4>, <&adc_i2c_1 5>,
<&adc_i2c_1 6>, <&adc_i2c_1 7>,
<&adc_i2c_1 8>, <&adc_i2c_1 9>,
<&adc_i2c_1 10>, <&adc_i2c_1 11>,
<&adc_i2c_1 12>, <&adc_i2c_1 13>,
<&adc_i2c_1 14>, <&adc_i2c_1 15>,
<&adc0 0>, <&adc0 1>,
<&adc0 2>;
};
};
@ -307,6 +331,14 @@
status = "okay";
};
&uart8 {
status = "okay";
};
&uart9 {
status = "okay";
};
&i2c0 {
status = "okay";
@ -336,12 +368,27 @@
&i2c3 {
status = "okay";
bus-frequency = <1000000>;
multi-master;
mctp-controller;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
};
&i2c4 {
status = "okay";
adc_i2c: adc@16 {
adc_i2c_0: adc@14 {
compatible = "lltc,ltc2497";
reg = <0x14>;
vref-supply = <&voltage_mon_reg>;
#io-channel-cells = <1>;
};
adc_i2c_1: adc@16 {
compatible = "lltc,ltc2497";
reg = <0x16>;
vref-supply = <&voltage_mon_reg>;

18
arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts
View File

@ -424,7 +424,7 @@
&i2c3 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -471,7 +471,7 @@
&i2c6 {
status = "okay";
i2c-switch@72 {
i2c-mux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
#address-cells = <1>;
@ -524,7 +524,7 @@
};
};
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -533,7 +533,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
@ -569,7 +569,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
@ -605,7 +605,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
@ -640,7 +640,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
@ -808,7 +808,7 @@
&i2c10 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -838,7 +838,7 @@
};
};
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;

10
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts
View File

@ -132,7 +132,7 @@
* PCA9548 (1-0070) provides 8 channels connecting to SMB (Switch
* Main Board).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -194,7 +194,7 @@
* PCA9548 (2-0070) provides 8 channels connecting to SCM (System
* Controller Module).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -256,7 +256,7 @@
* PCA9548 (3-0070) provides 8 channels connecting to SMB (Switch
* Main Board).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -423,7 +423,7 @@
* PCA9548 (8-0070) provides 8 channels connecting to PDB (Power
* Delivery Board).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -486,7 +486,7 @@
* PCA9548 (15-0076) provides 8 channels connecting to FCM (Fan
* Controller Module).
*/
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

46
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts
View File

@ -328,7 +328,7 @@
&i2c1 {
status = "okay";
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -341,7 +341,7 @@
#size-cells = <0>;
reg = <0>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -390,7 +390,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -446,7 +446,7 @@
#size-cells = <0>;
reg = <1>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -495,7 +495,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -551,7 +551,7 @@
#size-cells = <0>;
reg = <2>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -600,7 +600,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -656,7 +656,7 @@
#size-cells = <0>;
reg = <3>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -705,7 +705,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -761,7 +761,7 @@
#size-cells = <0>;
reg = <4>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -810,7 +810,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -866,7 +866,7 @@
#size-cells = <0>;
reg = <5>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -915,7 +915,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -971,7 +971,7 @@
#size-cells = <0>;
reg = <6>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1020,7 +1020,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1076,7 +1076,7 @@
#size-cells = <0>;
reg = <7>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1125,7 +1125,7 @@
};
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1183,7 +1183,7 @@
&i2c2 {
status = "okay";
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1281,7 +1281,7 @@
&i2c8 {
status = "okay";
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1294,7 +1294,7 @@
#size-cells = <0>;
reg = <0>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1350,7 +1350,7 @@
#size-cells = <0>;
reg = <1>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1406,7 +1406,7 @@
#size-cells = <0>;
reg = <2>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1462,7 +1462,7 @@
#size-cells = <0>;
reg = <3>;
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts
View File

@ -65,7 +65,7 @@
};
&i2c2 {
i2c-switch@75 {
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -123,7 +123,7 @@
};
&i2c5 {
i2c-switch@75 {
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

30
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts
View File

@ -233,7 +233,7 @@
* PCA9548 (2-0070) provides 8 channels connecting to SCM (System
* Controller Module).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -303,7 +303,7 @@
* PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch
* Main Board).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -315,7 +315,7 @@
#size-cells = <0>;
reg = <0>;
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -481,7 +481,7 @@
#size-cells = <0>;
reg = <1>;
i2c-switch@72 {
i2c-mux@72 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -544,7 +544,7 @@
#size-cells = <0>;
reg = <2>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -615,7 +615,7 @@
#size-cells = <0>;
reg = <3>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -715,7 +715,7 @@
* PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch
* Main Board).
*/
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -727,7 +727,7 @@
#size-cells = <0>;
reg = <0>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -790,7 +790,7 @@
#size-cells = <0>;
reg = <1>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -853,7 +853,7 @@
#size-cells = <0>;
reg = <2>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -916,7 +916,7 @@
#size-cells = <0>;
reg = <3>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -979,7 +979,7 @@
#size-cells = <0>;
reg = <4>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1042,7 +1042,7 @@
#size-cells = <0>;
reg = <5>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1105,7 +1105,7 @@
#size-cells = <0>;
reg = <6>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1168,7 +1168,7 @@
#size-cells = <0>;
reg = <7>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

32
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts
View File

@ -344,7 +344,7 @@
* I2C Switch 2-0070 is connecting to SCM (System Controller
* Module).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -425,7 +425,7 @@
&i2c8 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -441,7 +441,7 @@
#size-cells = <0>;
reg = <0>;
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -507,7 +507,7 @@
#size-cells = <0>;
reg = <1>;
i2c-switch@72 {
i2c-mux@72 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -573,7 +573,7 @@
#size-cells = <0>;
reg = <2>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -639,7 +639,7 @@
#size-cells = <0>;
reg = <3>;
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -729,7 +729,7 @@
* I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB
* (Switch Main Board).
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -793,7 +793,7 @@
&i2c11 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -809,7 +809,7 @@
#size-cells = <0>;
reg = <0>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -875,7 +875,7 @@
#size-cells = <0>;
reg = <1>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -941,7 +941,7 @@
#size-cells = <0>;
reg = <2>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1007,7 +1007,7 @@
#size-cells = <0>;
reg = <3>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1073,7 +1073,7 @@
#size-cells = <0>;
reg = <4>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1139,7 +1139,7 @@
#size-cells = <0>;
reg = <5>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1205,7 +1205,7 @@
#size-cells = <0>;
reg = <6>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -1271,7 +1271,7 @@
#size-cells = <0>;
reg = <7>;
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

8
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts
View File

@ -211,7 +211,7 @@
&i2c1 {
status = "okay";
//X24 Riser
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
@ -243,7 +243,7 @@
pagesize = <32>;
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
@ -303,7 +303,7 @@
pagesize = <32>;
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
@ -363,7 +363,7 @@
pagesize = <32>;
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts
View File

@ -44,7 +44,7 @@
};
&i2c7 {
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

10
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts
View File

@ -59,7 +59,8 @@
ast-adc-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
<&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>;
};
/*
@ -138,7 +139,7 @@
&i2c2 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -218,7 +219,7 @@
&i2c8 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -287,7 +288,7 @@
&i2c11 {
status = "okay";
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -366,6 +367,7 @@
};
&sdhci1 {
max-frequency = <25000000>;
/*
* DMA mode needs to be disabled to avoid conflicts with UHCI
* Controller in AST2500 SoC.

2
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts
View File

@ -57,7 +57,7 @@
&i2c2 {
status = "okay";
i2c-switch@75 {
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;

624
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts Normal file
View File

@ -0,0 +1,624 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2022 Facebook Inc.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
#include <dt-bindings/i2c/i2c.h>
/ {
model = "Facebook Yosemite 4 BMC";
compatible = "facebook,yosemite4-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
};
chosen {
stdout-path = "serial4:57600n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 1>;
};
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&uart6 {
status = "okay";
};
&uart7 {
status = "okay";
};
&uart8 {
status = "okay";
};
&uart9 {
status = "okay";
};
&wdt1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
aspeed,reset-type = "soc";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
aspeed,ext-pulse-duration = <256>;
};
&mac2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii3_default>;
use-ncsi;
mlx,multi-host;
};
&mac3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
use-ncsi;
mlx,multi-host;
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
};
};
&i2c0 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c1 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c2 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c3 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c4 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c5 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c6 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c7 {
status = "okay";
mctp-controller;
bus-frequency = <400000>;
multi-master;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
power-sensor@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c8 {
status = "okay";
bus-frequency = <400000>;
i2c-mux@70 {
compatible = "nxp,pca9544";
idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x70>;
};
};
&i2c9 {
status = "okay";
bus-frequency = <400000>;
i2c-mux@71 {
compatible = "nxp,pca9544";
idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x71>;
};
};
&i2c10 {
status = "okay";
bus-frequency = <400000>;
};
&i2c11 {
status = "okay";
power-sensor@10 {
compatible = "adi, adm1272";
reg = <0x10>;
};
power-sensor@12 {
compatible = "adi, adm1272";
reg = <0x12>;
};
gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@21 {
compatible = "nxp,pca9555";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@22 {
compatible = "nxp,pca9555";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
temperature-sensor@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
temperature-sensor@4a {
compatible = "ti,tmp75";
reg = <0x4a>;
};
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4b>;
};
eeprom@54 {
compatible = "atmel,24c256";
reg = <0x54>;
};
};
&i2c12 {
status = "okay";
bus-frequency = <400000>;
temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
rtc@6f {
compatible = "nuvoton,nct3018y";
reg = <0x6f>;
};
};
&i2c13 {
status = "okay";
bus-frequency = <400000>;
};
&i2c14 {
status = "okay";
bus-frequency = <400000>;
adc@1d {
compatible = "ti,adc128d818";
reg = <0x1d>;
ti,mode = /bits/ 8 <2>;
};
adc@35 {
compatible = "ti,adc128d818";
reg = <0x35>;
ti,mode = /bits/ 8 <2>;
};
adc@37 {
compatible = "ti,adc128d818";
reg = <0x37>;
ti,mode = /bits/ 8 <2>;
};
power-sensor@40 {
compatible = "ti,ina230";
reg = <0x40>;
};
power-sensor@41 {
compatible = "ti,ina230";
reg = <0x41>;
};
power-sensor@42 {
compatible = "ti,ina230";
reg = <0x42>;
};
power-sensor@43 {
compatible = "ti,ina230";
reg = <0x43>;
};
power-sensor@44 {
compatible = "ti,ina230";
reg = <0x44>;
};
temperature-sensor@4e {
compatible = "ti,tmp75";
reg = <0x4e>;
};
temperature-sensor@4f {
compatible = "ti,tmp75";
reg = <0x4f>;
};
eeprom@51 {
compatible = "atmel,24c128";
reg = <0x51>;
};
i2c-mux@71 {
compatible = "nxp,pca9846";
#address-cells = <1>;
#size-cells = <0>;
idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x71>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
ti,mode = /bits/ 8 <2>;
};
pwm@20{
compatible = "max31790";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
};
pwm@23{
compatible = "max31790";
reg = <0x23>;
#address-cells = <1>;
#size-cells = <0>;
};
adc@33 {
compatible = "maxim,max11615";
reg = <0x33>;
};
eeprom@52 {
compatible = "atmel,24c128";
reg = <0x52>;
};
gpio@61 {
compatible = "nxp,pca9552";
reg = <0x61>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
ti,mode = /bits/ 8 <2>;
};
pwm@20{
compatible = "max31790";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
};
pwm@23{
compatible = "max31790";
reg = <0x23>;
#address-cells = <1>;
#size-cells = <0>;
};
adc@33 {
compatible = "maxim,max11615";
reg = <0x33>;
};
eeprom@52 {
compatible = "atmel,24c128";
reg = <0x52>;
};
gpio@61 {
compatible = "nxp,pca9552";
reg = <0x61>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
i2c-mux@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x73>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc@35 {
compatible = "maxim,max11617";
reg = <0x35>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adc@35 {
compatible = "maxim,max11617";
reg = <0x35>;
};
};
};
};
&i2c15 {
status = "okay";
mctp-controller;
multi-master;
bus-frequency = <400000>;
mctp@10 {
compatible = "mctp-i2c-controller";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
i2c-mux@72 {
compatible = "nxp,pca9544";
idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x72>;
};
};
&adc0 {
ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
ref_voltage = <2500>;
status = "okay";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&uhci {
status = "okay";
};

364
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts
View File

@ -12,38 +12,11 @@
compatible = "ibm,bonnell-bmc", "aspeed,ast2600";
aliases {
i2c100 = &cfam0_i2c0;
i2c101 = &cfam0_i2c1;
i2c110 = &cfam0_i2c10;
i2c111 = &cfam0_i2c11;
i2c112 = &cfam0_i2c12;
i2c113 = &cfam0_i2c13;
i2c114 = &cfam0_i2c14;
i2c115 = &cfam0_i2c15;
i2c202 = &cfam1_i2c2;
i2c203 = &cfam1_i2c3;
i2c210 = &cfam1_i2c10;
i2c211 = &cfam1_i2c11;
i2c214 = &cfam1_i2c14;
i2c215 = &cfam1_i2c15;
i2c216 = &cfam1_i2c16;
i2c217 = &cfam1_i2c17;
serial4 = &uart5;
i2c16 = &i2c11mux0chn0;
i2c17 = &i2c11mux0chn1;
i2c18 = &i2c11mux0chn2;
i2c19 = &i2c11mux0chn3;
spi10 = &cfam0_spi0;
spi11 = &cfam0_spi1;
spi12 = &cfam0_spi2;
spi13 = &cfam0_spi3;
spi20 = &cfam1_spi0;
spi21 = &cfam1_spi1;
spi22 = &cfam1_spi2;
spi23 = &cfam1_spi3;
};
chosen {
@ -197,313 +170,6 @@
clk-phase-mmc-hs200 = <180>, <180>;
};
&fsim0 {
status = "okay";
#address-cells = <2>;
#size-cells = <0>;
cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <0>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_i2c0: i2c-bus@0 {
reg = <0>; /* OMI01 */
};
cfam0_i2c1: i2c-bus@1 {
reg = <1>; /* OMI23 */
};
cfam0_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam0_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam0_i2c12: i2c-bus@c {
reg = <12>; /* OP4A */
};
cfam0_i2c13: i2c-bus@d {
reg = <13>; /* OP4B */
};
cfam0_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam0_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ0: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub0: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
};
};
};
&fsi_hub0 {
cfam@1,0 {
reg = <1 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <1>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_i2c2: i2c-bus@2 {
reg = <2>; /* OMI45 */
};
cfam1_i2c3: i2c-bus@3 {
reg = <3>; /* OMI67 */
};
cfam1_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam1_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam1_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam1_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
cfam1_i2c16: i2c-bus@10 {
reg = <16>; /* OP6A */
};
cfam1_i2c17: i2c-bus@11 {
reg = <17>; /* OP6B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ1: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub1: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
};
&ibt {
status = "okay";
};
@ -913,3 +579,33 @@
aspeed,lpc-io-reg = <0xca2>;
aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
#include "ibm-power10-dual.dtsi"
&cfam0_i2c10 {
eeprom@50 {
compatible = "atmel,at30tse004a";
reg = <0x50>;
};
};
&cfam0_i2c11 {
eeprom@50 {
compatible = "atmel,at30tse004a";
reg = <0x50>;
};
};
&cfam0_i2c12 {
eeprom@50 {
compatible = "atmel,at30tse004a";
reg = <0x50>;
};
};
&cfam0_i2c13 {
eeprom@50 {
compatible = "atmel,at30tse004a";
reg = <0x50>;
};
};

2883
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts
View File

File diff suppressed because it is too large Load Diff

691
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts
View File

@ -12,39 +12,6 @@
compatible = "ibm,rainier-bmc", "aspeed,ast2600";
aliases {
i2c100 = &cfam0_i2c0;
i2c101 = &cfam0_i2c1;
i2c110 = &cfam0_i2c10;
i2c111 = &cfam0_i2c11;
i2c112 = &cfam0_i2c12;
i2c113 = &cfam0_i2c13;
i2c114 = &cfam0_i2c14;
i2c115 = &cfam0_i2c15;
i2c202 = &cfam1_i2c2;
i2c203 = &cfam1_i2c3;
i2c210 = &cfam1_i2c10;
i2c211 = &cfam1_i2c11;
i2c214 = &cfam1_i2c14;
i2c215 = &cfam1_i2c15;
i2c216 = &cfam1_i2c16;
i2c217 = &cfam1_i2c17;
i2c300 = &cfam2_i2c0;
i2c301 = &cfam2_i2c1;
i2c310 = &cfam2_i2c10;
i2c311 = &cfam2_i2c11;
i2c312 = &cfam2_i2c12;
i2c313 = &cfam2_i2c13;
i2c314 = &cfam2_i2c14;
i2c315 = &cfam2_i2c15;
i2c402 = &cfam3_i2c2;
i2c403 = &cfam3_i2c3;
i2c410 = &cfam3_i2c10;
i2c411 = &cfam3_i2c11;
i2c414 = &cfam3_i2c14;
i2c415 = &cfam3_i2c15;
i2c416 = &cfam3_i2c16;
i2c417 = &cfam3_i2c17;
serial4 = &uart5;
i2c16 = &i2c2mux0;
i2c17 = &i2c2mux1;
@ -61,23 +28,6 @@
i2c28 = &i2c6mux0chn3;
i2c29 = &i2c11mux0chn0;
i2c30 = &i2c11mux0chn1;
spi10 = &cfam0_spi0;
spi11 = &cfam0_spi1;
spi12 = &cfam0_spi2;
spi13 = &cfam0_spi3;
spi20 = &cfam1_spi0;
spi21 = &cfam1_spi1;
spi22 = &cfam1_spi2;
spi23 = &cfam1_spi3;
spi30 = &cfam2_spi0;
spi31 = &cfam2_spi1;
spi32 = &cfam2_spi2;
spi33 = &cfam2_spi3;
spi40 = &cfam3_spi0;
spi41 = &cfam3_spi1;
spi42 = &cfam3_spi2;
spi43 = &cfam3_spi3;
};
chosen {
@ -301,632 +251,6 @@
clk-phase-mmc-hs200 = <180>, <180>;
};
&fsim0 {
status = "okay";
#address-cells = <2>;
#size-cells = <0>;
/*
* CFAM Reset is supposed to be active low but pass1 hardware is wired
* active high.
*/
cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <0>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_i2c0: i2c-bus@0 {
reg = <0>; /* OMI01 */
};
cfam0_i2c1: i2c-bus@1 {
reg = <1>; /* OMI23 */
};
cfam0_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam0_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam0_i2c12: i2c-bus@c {
reg = <12>; /* OP4A */
};
cfam0_i2c13: i2c-bus@d {
reg = <13>; /* OP4B */
};
cfam0_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam0_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ0: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub0: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
};
};
};
&fsi_hub0 {
cfam@1,0 {
reg = <1 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <1>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_i2c2: i2c-bus@2 {
reg = <2>; /* OMI45 */
};
cfam1_i2c3: i2c-bus@3 {
reg = <3>; /* OMI67 */
};
cfam1_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam1_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam1_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam1_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
cfam1_i2c16: i2c-bus@10 {
reg = <16>; /* OP6A */
};
cfam1_i2c17: i2c-bus@11 {
reg = <17>; /* OP6B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ1: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub1: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
cfam@2,0 {
reg = <2 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <2>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam2_i2c0: i2c-bus@0 {
reg = <0>; /* OM01 */
};
cfam2_i2c1: i2c-bus@1 {
reg = <1>; /* OM23 */
};
cfam2_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam2_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam2_i2c12: i2c-bus@c {
reg = <12>; /* OP4A */
};
cfam2_i2c13: i2c-bus@d {
reg = <13>; /* OP4B */
};
cfam2_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam2_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam2_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ2: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub2: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
cfam@3,0 {
reg = <3 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <3>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam3_i2c2: i2c-bus@2 {
reg = <2>; /* OM45 */
};
cfam3_i2c3: i2c-bus@3 {
reg = <3>; /* OM67 */
};
cfam3_i2c10: i2c-bus@a {
reg = <10>; /* OP3A */
};
cfam3_i2c11: i2c-bus@b {
reg = <11>; /* OP3B */
};
cfam3_i2c14: i2c-bus@e {
reg = <14>; /* OP5A */
};
cfam3_i2c15: i2c-bus@f {
reg = <15>; /* OP5B */
};
cfam3_i2c16: i2c-bus@10 {
reg = <16>; /* OP6A */
};
cfam3_i2c17: i2c-bus@11 {
reg = <17>; /* OP6B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam3_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam3_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam3_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam3_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ3: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub3: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
};
/* Legacy OCC numbering (to get rid of when userspace is fixed) */
&fsi_occ0 {
reg = <1>;
};
&fsi_occ1 {
reg = <2>;
};
&fsi_occ2 {
reg = <3>;
};
&fsi_occ3 {
reg = <4>;
};
&ibt {
status = "okay";
};
@ -1017,7 +341,7 @@
reg = <0x4a>;
};
pca9546@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -1099,7 +423,7 @@
reg = <0x49>;
};
pca9546@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -1201,7 +525,7 @@
reg = <0x4b>;
};
pca9546@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -2031,7 +1355,7 @@
reg = <0x49>;
};
pca9546@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -2092,11 +1416,6 @@
&i2c12 {
status = "okay";
tpm@2e {
compatible = "nuvoton,npct75x";
reg = <0x2e>;
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
@ -2418,3 +1737,5 @@
aspeed,lpc-io-reg = <0xca2>;
aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
#include "ibm-power10-quad.dtsi"

4
arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts
View File

@ -348,7 +348,7 @@
label = "outlet";
};
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -432,7 +432,7 @@
&i2c7 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;

12
arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts
View File

@ -215,7 +215,7 @@
label = "outlet";
};
pca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
};
@ -224,17 +224,17 @@
&i2c3 {
status = "okay";
pca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
};
pca9548@71 {
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
};
pca9548@72 {
i2c-mux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
};
@ -248,7 +248,7 @@
&i2c5 {
status = "okay";
pca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
};
@ -257,7 +257,7 @@
&i2c6 {
status = "okay";
pca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
};

389
arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-starscream.dts Normal file
View File

@ -0,0 +1,389 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2023 Inventec Corp.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include "aspeed-g6-pinctrl.dtsi"
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "STARSCREAM BMC";
compatible = "inventec,starscream-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
video_engine_memory: video {
size = <0x04000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
leds {
compatible = "gpio-leds";
led-uid {
label = "UID_LED";
gpios = <&gpio0 186 GPIO_ACTIVE_LOW>;
};
led-heartbeat {
label = "HB_LED";
gpios = <&gpio0 127 GPIO_ACTIVE_LOW>;
};
};
};
&mdio0 {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mac2 {
status = "okay";
pinctrl-names = "default";
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_rmii3_default>;
use-ncsi;
};
&mac3 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii4_default>;
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
#include "openbmc-flash-layout.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "bios";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&vuart1 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart5 {
status = "okay";
};
&kcs3 {
aspeed,lpc-io-reg = <0xca2>;
status = "okay";
};
&uart_routing {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
// I2C EXPANDER
i2c-mux@71 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// AMD SB-TSI CPU1
sbtsi@4c {
compatible = "amd,sbtsi";
reg = <0x4c>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// AMD SB-TSI CPU2
sbtsi@48 {
compatible = "amd,sbtsi";
reg = <0x48>;
};
};
};
};
&i2c5 {
status = "okay";
// I2C EXPANDER U153
i2c-mux@70 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
usb_hub: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
riser1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
riser2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&i2c6 {
status = "okay";
// Motherboard Temp_U89
temperature-sensor@4e {
compatible = "ti,tmp421";
reg = <0x4e>;
};
// RunBMC Temp_U6
temperature-sensor@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
};
&i2c7 {
status = "okay";
// I2C EXPANDER U40
i2c-mux@70 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&i2c8 {
status = "okay";
// FRU RunBMC
eeprom@51 {
compatible = "atmel,24c512";
reg = <0x51>;
pagesize = <128>;
};
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
// FRU SCM
eeprom@51 {
compatible = "atmel,24c512";
reg = <0x51>;
pagesize = <128>;
};
// SCM Temp_U17
temperature-sensor@4f {
compatible = "ti,tmp75";
reg = <0x4f>;
};
};
&gpio0 {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "alert-psu0-smb-r-n","bmc-ready","","assert-cpu0-prochot-r-n",
"","","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "","","","","reset-sgpio-r-n","","","",
/*G0-G7*/ "","","scm-jtag-mux-select","","","","","",
/*H0-H7*/ "","","","","reset-out","power-out","","",
/*I0-I7*/ "","","","","","","irq-bmc-cpu0-buf-nmi-n","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","ncsi-ocp-clk-en-n","","","","","",
/*O0-O7*/ "","","","","","","cpu1-thermal-trip-n","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "cpu0-prochot-n","","cpu1-prochot-n","","cpu0-pe-rst0","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","",
"","PCH_SLP_S4_BMC_N","cpu0-thermtrip-n","alert-psu1-smb-r-n",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "bios-recovery-buf-n","","assert-cpu1-prochot-r-n","",
"power-chassis-good","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","platform-type","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","cpld-power-break-n","","","","","","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&sgpiom0 {
status = "okay";
ngpios = <64>;
bus-frequency = <1000000>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&emmc_controller {
status = "okay";
};
&emmc {
status = "okay";
non-removable;
max-frequency = <52000000>;
bus-width = <8>;
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&vhub {
status = "okay";
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
};
&rtc {
status = "okay";
};

6
arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts
View File

@ -193,14 +193,14 @@
// I2C EXPANDER
status = "okay";
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
};
i2c-switch@73 {
i2c-mux@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
@ -212,7 +212,7 @@
// I2C EXPANDER
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts
View File

@ -208,7 +208,7 @@
* Slot 3
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
@ -249,7 +249,7 @@
* Slot 2,
* Slot 3
*/
i2c-switch@76 {
i2c-mux@76 {
compatible = "nxp,pca9546";
reg = <0x76>;
#address-cells = <1>;

4
arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts
View File

@ -175,7 +175,7 @@
&i2c0 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
@ -227,7 +227,7 @@
&i2c3 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;

4
arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts
View File

@ -231,7 +231,7 @@
&i2c1 {
status = "okay";
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
@ -282,7 +282,7 @@
&i2c4 {
status = "okay";
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;

6
arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts
View File

@ -197,7 +197,7 @@
* Slot 6,
* Slot 7
*/
i2c-switch@74 {
i2c-mux@74 {
compatible = "nxp,pca9546";
reg = <0x74>;
#address-cells = <1>;
@ -238,7 +238,7 @@
* SSD 1,
* SSD 2
*/
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -325,7 +325,7 @@
* PSU3
* PSU2
*/
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;

10
arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts
View File

@ -285,7 +285,7 @@
reg = <0x4b>;
};
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
@ -321,7 +321,7 @@
&i2c1 {
status = "okay";
i2c-switch@59 {
i2c-mux@59 {
compatible = "nxp,pca9848";
reg = <0x59>;
#address-cells = <1>;
@ -393,7 +393,7 @@
#size-cells = <0>;
reg = <7>;
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9546";
reg = <0x77>;
#address-cells = <1>;
@ -490,7 +490,7 @@
&i2c6 {
status = "okay";
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@ -556,7 +556,7 @@
&i2c7 {
status = "okay";
i2c-switch@75 {
i2c-mux@75 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;

14
arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts
View File

@ -88,16 +88,16 @@
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
mux-expa@73 {
compatible = "nxp,pca9545";
reg = <0x73>;
i2c-mux@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
mux-sata@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
i2c-mux@73 {
compatible = "nxp,pca9545";
reg = <0x73>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
@ -106,7 +106,7 @@
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
mux-expb@71 {
i2c-mux@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;

10
arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts
View File

@ -133,7 +133,7 @@
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
mux-expa@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
@ -144,7 +144,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
rsra-mux@72 {
i2c-mux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
#address-cells = <1>;
@ -165,7 +165,7 @@
};
};
};
mux-sata@71 {
i2c-mux@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
@ -176,7 +176,7 @@
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
mux-expb@71 {
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
@ -187,7 +187,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
rsrb-mux@72 {
i2c-mux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
#address-cells = <1>;

14
arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts
View File

@ -88,16 +88,16 @@
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
mux-expa@73 {
compatible = "nxp,pca9545";
reg = <0x73>;
i2c-mux@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
mux-sata@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
i2c-mux@73 {
compatible = "nxp,pca9545";
reg = <0x73>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
@ -106,7 +106,7 @@
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
mux-expb@71 {
i2c-mux@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;

10
arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
View File

@ -297,6 +297,16 @@
groups = "I2C9";
};
pinctrl_i3c1_default: i3c1_default {
function = "I3C1";
groups = "I3C1";
};
pinctrl_i3c2_default: i3c2_default {
function = "I3C2";
groups = "I3C2";
};
pinctrl_i3c3_default: i3c3_default {
function = "I3C3";
groups = "I3C3";

20
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
View File

@ -729,6 +729,16 @@
status = "disabled";
};
vuart3: serial@1e787800 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787800 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_APB2>;
no-loopback-test;
status = "disabled";
};
vuart2: serial@1e788000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e788000 0x40>;
@ -739,6 +749,16 @@
status = "disabled";
};
vuart4: serial@1e788800 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e788800 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_APB2>;
no-loopback-test;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;

4
arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi
View File

@ -4,6 +4,10 @@
#include "aspeed-g5.dtsi"
/ {
aliases {
spi0 = &fmc;
};
memory@80000000 {
reg = <0x80000000 0x40000000>;
};

380
arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi Normal file
View File

@ -0,0 +1,380 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2023 IBM Corp.
&fsim0 {
status = "okay";
#address-cells = <2>;
#size-cells = <0>;
cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <0>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_i2c0: i2c-bus@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* OMI01 */
};
cfam0_i2c1: i2c-bus@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* OMI23 */
};
cfam0_i2c10: i2c-bus@a {
#address-cells = <1>;
#size-cells = <0>;
reg = <10>; /* OP3A */
};
cfam0_i2c11: i2c-bus@b {
#address-cells = <1>;
#size-cells = <0>;
reg = <11>; /* OP3B */
};
cfam0_i2c12: i2c-bus@c {
#address-cells = <1>;
#size-cells = <0>;
reg = <12>; /* OP4A */
};
cfam0_i2c13: i2c-bus@d {
#address-cells = <1>;
#size-cells = <0>;
reg = <13>; /* OP4B */
};
cfam0_i2c14: i2c-bus@e {
#address-cells = <1>;
#size-cells = <0>;
reg = <14>; /* OP5A */
};
cfam0_i2c15: i2c-bus@f {
#address-cells = <1>;
#size-cells = <0>;
reg = <15>; /* OP5B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ0: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub0: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
};
};
};
&fsi_hub0 {
cfam@1,0 {
reg = <1 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <1>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_i2c2: i2c-bus@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>; /* OMI45 */
};
cfam1_i2c3: i2c-bus@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>; /* OMI67 */
};
cfam1_i2c10: i2c-bus@a {
#address-cells = <1>;
#size-cells = <0>;
reg = <10>; /* OP3A */
};
cfam1_i2c11: i2c-bus@b {
#address-cells = <1>;
#size-cells = <0>;
reg = <11>; /* OP3B */
};
cfam1_i2c14: i2c-bus@e {
#address-cells = <1>;
#size-cells = <0>;
reg = <14>; /* OP5A */
};
cfam1_i2c15: i2c-bus@f {
#address-cells = <1>;
#size-cells = <0>;
reg = <15>; /* OP5B */
};
cfam1_i2c16: i2c-bus@10 {
#address-cells = <1>;
#size-cells = <0>;
reg = <16>; /* OP6A */
};
cfam1_i2c17: i2c-bus@11 {
#address-cells = <1>;
#size-cells = <0>;
reg = <17>; /* OP6B */
};
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi";
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ1: occ {
compatible = "ibm,p10-occ";
occ-hwmon {
compatible = "ibm,p10-occ-hwmon";
ibm,no-poll-on-init;
};
};
};
fsi_hub1: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
};
/* Legacy OCC numbering (to get rid of when userspace is fixed) */
&fsi_occ0 {
reg = <1>;
};
&fsi_occ1 {
reg = <2>;
};
/ {
aliases {
i2c100 = &cfam0_i2c0;
i2c101 = &cfam0_i2c1;
i2c110 = &cfam0_i2c10;
i2c111 = &cfam0_i2c11;
i2c112 = &cfam0_i2c12;
i2c113 = &cfam0_i2c13;
i2c114 = &cfam0_i2c14;
i2c115 = &cfam0_i2c15;
i2c202 = &cfam1_i2c2;
i2c203 = &cfam1_i2c3;
i2c210 = &cfam1_i2c10;
i2c211 = &cfam1_i2c11;
i2c214 = &cfam1_i2c14;
i2c215 = &cfam1_i2c15;
i2c216 = &cfam1_i2c16;
i2c217 = &cfam1_i2c17;
spi10 = &cfam0_spi0;
spi11 = &cfam0_spi1;
spi12 = &cfam0_spi2;
spi13 = &cfam0_spi3;
spi20 = &cfam1_spi0;
spi21 = &cfam1_spi1;
spi22 = &cfam1_spi2;
spi23 = &cfam1_spi3;
};
};

1305
arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

1
arch/arm/boot/dts/broadcom/Makefile
View File

@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-asus-rt-ac3100.dtb \
bcm47094-asus-rt-ac88u.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-dlink-dir-890l.dtb \

4
arch/arm/boot/dts/broadcom/bcm-hr2.dtsi
View File

@ -54,8 +54,8 @@
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
};

18
arch/arm/boot/dts/broadcom/bcm-ns.dtsi
View File

@ -272,14 +272,32 @@
gmac0: ethernet@24000 {
reg = <0x24000 0x800>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
gmac1: ethernet@25000 {
reg = <0x25000 0x800>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
gmac2: ethernet@26000 {
reg = <0x26000 0x800>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
gmac3: ethernet@27000 {

4
arch/arm/boot/dts/broadcom/bcm-nsp.dtsi
View File

@ -72,8 +72,8 @@
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};

13
arch/arm/boot/dts/broadcom/bcm11351.dtsi
View File

@ -111,13 +111,12 @@
gpio: gpio@35003000 {
compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
reg = <0x35003000 0x800>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;

9
arch/arm/boot/dts/broadcom/bcm21664.dtsi
View File

@ -101,11 +101,10 @@
gpio: gpio@35003000 {
compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
reg = <0x35003000 0x524>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;

9
arch/arm/boot/dts/broadcom/bcm23550.dtsi
View File

@ -101,11 +101,10 @@
gpio: gpio@1003000 {
compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
reg = <0x01003000 0x524>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;

4
arch/arm/boot/dts/broadcom/bcm2711.dtsi
View File

@ -76,7 +76,7 @@
};
};
dma: dma@7e007000 {
dma: dma-controller@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xb00>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
@ -278,7 +278,7 @@
clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clock-rates = <10000000>;
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};

100
arch/arm/boot/dts/broadcom/bcm28155-ap.dts
View File

@ -15,64 +15,64 @@
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};
serial@3e000000 {
status = "okay";
&bsc1 {
clock-frequency = <400000>;
status = "okay";
};
&bsc2 {
clock-frequency = <400000>;
status = "okay";
};
&bsc3 {
clock-frequency = <400000>;
status = "okay";
};
&pmu_bsc {
clock-frequency = <100000>;
status = "okay";
pmu: pmu@8 {
reg = <0x08>;
};
};
i2c@3e016000 {
clock-frequency = <400000>;
status = "okay";
};
&pwm {
status = "okay";
};
i2c@3e017000 {
clock-frequency = <400000>;
status = "okay";
};
&sdio2 {
non-removable;
max-frequency = <48000000>;
vmmc-supply = <&camldo1_reg>;
vqmmc-supply = <&iosr1_reg>;
status = "okay";
};
i2c@3e018000 {
clock-frequency = <400000>;
status = "okay";
};
&sdio4 {
max-frequency = <48000000>;
cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
vmmc-supply = <&sdldo_reg>;
vqmmc-supply = <&sdxldo_reg>;
status = "okay";
};
i2c@3500d000 {
clock-frequency = <100000>;
status = "okay";
&uartb {
status = "okay";
};
pmu: pmu@8 {
reg = <0x08>;
};
};
&usbotg {
vusb_d-supply = <&usbldo_reg>;
vusb_a-supply = <&iosr1_reg>;
status = "okay";
};
sdio2: mmc@3f190000 {
non-removable;
max-frequency = <48000000>;
vmmc-supply = <&camldo1_reg>;
vqmmc-supply = <&iosr1_reg>;
status = "okay";
};
sdio4: mmc@3f1b0000 {
max-frequency = <48000000>;
cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
vmmc-supply = <&sdldo_reg>;
vqmmc-supply = <&sdxldo_reg>;
status = "okay";
};
pwm: pwm@3e01a000 {
status = "okay";
};
usbotg: usb@3f120000 {
vusb_d-supply = <&usbldo_reg>;
vusb_a-supply = <&iosr1_reg>;
status = "okay";
};
usbphy: usb-phy@3f130000 {
status = "okay";
};
&usbphy {
status = "okay";
};
#include "bcm59056.dtsi"

2
arch/arm/boot/dts/broadcom/bcm2835-common.dtsi
View File

@ -8,7 +8,7 @@
interrupt-parent = <&intc>;
soc {
dma: dma@7e007000 {
dma: dma-controller@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xf00>;
interrupts = <1 16>,

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts
View File

@ -81,6 +81,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts
View File

@ -83,6 +83,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts
View File

@ -83,6 +83,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts
View File

@ -83,6 +83,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0 &i2s_alt2>;
/* I2S interface */

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts
View File

@ -83,6 +83,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0>;
};

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts
View File

@ -73,6 +73,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0>;
};

2
arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts
View File

@ -97,6 +97,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0>;
};
@ -111,6 +112,7 @@
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
};

1
arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts
View File

@ -85,6 +85,7 @@
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-names = "default";
pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
/* I2S interface */

Some files were not shown because too many files have changed in this diff Show More